JPS6238893B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a counting circuit used as a frequency counting means in a PLL (phase locked loop) circuit or the like for a digital tuner. In recent years, counting circuits, particularly programmable counters, have been used in various fields, and among them, programmable counters used in PLL (phase locked loop) circuits for digital tuners have been significantly improved. The characteristics required for a programmable counter of a PLL circuit for a digital tuner are low power consumption and high-speed operation characteristics. Currently, complementary MOS integrated circuits (CMOS LSI) are mainly used to meet the above requirements.
However, the maximum operating characteristics of CMOS LSI is about 8 to 10 MHz in a 5V power supply system, while the FM digital tuner in Japan has a maximum operating characteristic of 76.0 to 90.0 MHz.
Used in FM digital tuner to use reception frequency of 65.3~7.9MHz and intermediate frequency of 65.3~7.9MHz.
A PLL circuit requires operating characteristics of up to 90MHz, including margin. Therefore, the CMOS structure
In the PLL circuit, a prescaler with an ECL (emitter pull logic) structure is used before the frequency divider circuit, and the received frequency is divided by about 1/20 by this prescaler, and then the frequency divider of the CMOS structure PLL circuit is used. is input. Furthermore, the inter-station frequency Δf in the case of FM broadcasting is set at 100 KHz in Japan. Therefore, the basic configuration of the PLL circuit must be designed to satisfy the following equation. f _l =N′・f _r ………(1) △f=P・f _r ………(2) Here, f _l : Local oscillation frequency, N′: Program frequency division value, P: Prescaler frequency division Value, f _r : comparison frequency. As a characteristic of the PLL circuit, the higher the comparison frequency _fr , the better the carrier-to-noise ratio becomes. Therefore, the smaller the frequency division value P of the prescaler, the better the characteristics of the PLL circuit will be. However, due to the limitations of the operating characteristics of the CMOS structure, the frequency division value P of the prescaler is usually often set to P=20. If P=20, the comparison frequency f
_r is as low as f _r =Δf/P=100/20=5 KHz, and the carrier-to-noise ratio is not good. Also, the lockup time of the PLL circuit can be reduced as the comparison frequency is higher, so in order to improve the response of the PLL circuit,
It is necessary to increase the comparison frequency. At this time, the division ratio required for the programmable counter is 653 to 793.
It was large and had a complicated structure. The purpose of the present invention is to reduce the preset value N by 1/N.
Alternatively, the purpose is to provide a counting circuit that can perform a frequency division ratio of 1/N + 0.5, so that when used as a programmable counter, the reference frequency can be increased without increasing the frequency division ratio. . The counting circuit according to the present invention includes a presettable counter that is preset to a predetermined value in response to a preset signal and counts down from the preset value in synchronization with an input signal, and a count value of this counter that is a specific value. a first delay circuit that delays the detection signal by one cycle of the input signal and outputs the detected signal; a second delay circuit that delays the output by half a cycle;
When the control signal takes a first level, the output of the first delay circuit is generated as the preset signal, and when the control signal takes a second level, the output of the second delay circuit is generated as the preset signal. and means for generating the output of the second delay circuit as the preset signal, inverting the phase of the input signal in response to the generation, and transmitting the inverted signal to the presettable counter. and a means for supplying. Conventional counting circuit (programmable counter)
According to , the frequency division value N' was always an integer value, so the precision of △N' = 1 was the highest, but the frequency division value of the programmable counter according to the present invention
By providing a delay circuit, N′ can be set to △
It is possible to improve the accuracy to N' = 0.5. For example, the difference in local oscillation frequency between adjacent broadcasting stations,
That is, since the inter-station frequency △f is △f=100 KHz, it can be expressed as △ _fl = △f = △N'·f _r (3) from equation (1). Therefore, with the conventional program counter, △
N' = 1, but according to the present invention, △N' = 0.5, and the comparison frequency f _r can be twice as large as the conventional one, greatly improving the carrier-to-noise ratio of the PLL circuit. can be improved. Furthermore, since the frequency division ratio of the programmable counter is the same as in the conventional case where ΔN'=1, the configuration is simple. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a CMOS structured programmable counter applied to a PLL circuit for an FM digital tuner. In Figure 1, 1 is a presettable BCD down counter, and the maximum value of the frequency division value N' is
N′ _nax =399. 2 is a “2” detection circuit,
It outputs the "H" level only when the output of the down counter 1 reaches "2". 3 is a one-bit shift register (it may be a monostable multivibrator), and 4 is a half-bit shift register. 5 is a switching circuit between the output of the 1-bit shift register 3 and the output of the half-bit shift register 4; when the switching signal _J0 is at "H" level, the output signal of the half-bit shift register 4 is output; When ₀ is at the "L" level, the output signal of the 1-bit shift register 3 is output. Reference numeral 6 denotes a phase control circuit, which changes the phase of the input signal CKI by 180 degrees at the rising timing of the output signal of the switching circuit 5 only when the switching signal _J0 is at the "H" level.
is output from. A specific circuit of the phase control circuit 6 is shown in FIG. In Fig. 2, 9 is a toggle flip-flop with reset, and the input signal CK
The output Q, is inverted at the rising timing of J ₀ =
It is reset when it is at the "0" level. The output Q, of this flip-flop 9 is input to NAND gates 8 and 10, respectively, and is controlled by CKI and a signal in which CKI is inverted by an inverter 7, that is, a signal whose phase is shifted by 180°.
1, and CKI or CKI is output from the output terminal CKO.
A signal with a phase shift of 180° is output. Next, the operation will be explained with reference to FIGS. 3 and 4. Note that FIG. 3 shows the control signal J ₀ at the "L" level, and FIG. 4 shows the case when the control signal J 0 is at the "H" level. A predetermined preset value N is set in the down counter 1 according to the signal supplied to the preset enable terminal PE, and down counting is executed from the preset value N in synchronization with the signal supplied to the terminal CK1. As shown in FIGS. 3 and 4, when the count value of counter 1 becomes "2",
The state is detected by the detection circuit 2 and its output CO2
takes the "H" level and is supplied to the 1-bit shift register 3. After a delay of one cycle of the input signal f _io , the output Q _A of the shift register 3 is inverted to the "H" level. When the switching control signal J ₀ is at the “L” level, the switching circuit 5 selects the Q _A output of the shift register 3, and as a result, the output O ₅ of the switching circuit 5 selects the Q A output of the shift register 3.
As shown in the figure, it becomes "H" level in synchronization with the output Q _A. This output _O5 is given to the preset enable terminal PE of the counter 1 as a preset signal. Thus, counter 1 has a preset value N
Take. The output O ₅ changes to the "L" level as the input signal f _io is inverted from "L" to "H" level in the next cycle, and the counter 1 changes to the "L" level as the input signal f io is inverted from "L" to "H" level in the next cycle, and the counter 1 changes to the "L" level as the input signal f _io is inverted from "L" to "H" level in the next cycle.
A down counter is performed in synchronization with the inversion of the "H" level of the signal _o , and if the terminal PE is at the "H" level, the down counter operation is not performed and the preset value N is held. Therefore, as shown in FIG.
The value of changes from “2” to “N” and that value is the signal f
It is held for two periods of _io and then down-counted. Thus, when the signal "J ₀ " is at the "L" level, a frequency division ratio of 1/N is obtained. output
O ₅ is taken out as a divided output signal and output to the PLL described above.
When used as a counter due to the programmability of the circuit, the phase is compared with a reference signal. On the other hand, when the switching control signal _J0 is at the "H" level, the switching circuit 5 switches the half-bit shift register 4
Select the output Q _B of . register 4 is register 3
Since the output Q _A of is output after being delayed by half a period of _the signal f _io , as shown in FIG. Afterwards, the output Q _B becomes "H" level, and the output O ₅ of the circuit 5 becomes "H" level in synchronization with this. Therefore, the count value of counter 1 changes from "2" to "1" and is preset to the preset value "N". Furthermore, the signal
Since J ₀ is at “H” level, output O ₅ is “H”
In response to the level, the phase inversion circuit 6 inverts the phase of the signal f _io . When the output _O5 is at the "H" level, the signal _fio is at the "L" level, so that the terminal CK1 of the counter 1 is at the "H" level as shown in FIG. From then on, the inverted signal of the input signal f _io is applied to the terminal of counter 1 until the signal J ₀ becomes “L” level.
Supplied to CK1. Thus, as shown in FIG. 4, the count value of the counter 1 changes from "2" to "1" for half a period of the input signal f _io , and then changes to "N" for two periods of the inverted signal of the input signal f _io . And the down count continues. That is, 1/N+
A division ratio of 0.5 will be obtained. As is clear from the above operation, according to the program counter of this embodiment, the frequency division value N output from the 1-bit shift register and the frequency division value N+0.5 output from the half-bit shift register can be created. I can do it. This operation is accomplished by switching the "H" and "L" levels of the switching signal _J0 . Therefore, the frequency division values shown in Table 1 below
We can obtain N′.

[Table] The above table shows the FM reception frequency (76.0 [MHz] ~ 90.0
[MHz]), the frequency division value N' of the program counter is shown, but when the switching signal _J0 is at the "H" level, the reception frequency is an even value of 76.0,
It outputs the frequency division value of 76.2, 76.4, ...90.0, and when it is at "L" level, it outputs the odd value reception frequency 76.1, 76.3, ...
..., outputs the division value of 89.9. Therefore, the preset value N set in down counter 1 is 326 to 396.
It will be an integer value between 10 and 10 of the comparison frequency at that time.
[KHz], which can be doubled compared to the conventional comparison frequency of 5 [KHz] with an extremely simple circuit configuration, and the carrier-to-noise ratio characteristics in the PLL circuit can also be significantly improved. In this example, the prescaler frequency division value is set to 1/
Although the case where the prescaler frequency division value is set to 20 has been described, it is clear that the present invention can be applied even if the frequency division value of the prescaler is arbitrarily changed. In addition, 1+ is required for performing delay operation using a monostable multivibrator.
Although a 0.5-bit delay has been described, a 1-0.5-bit delay may be executed, or a predetermined delay operation may be performed by connecting several stages of shift register circuits. Further, the counter is not limited to a down counter, but may be any counter that can count a predetermined value and output the result.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a programmable counter showing an embodiment of the present invention, FIG. 2 shows a block diagram of a phase control circuit, and FIGS. 3 and 4 each show a time chart. 1... Presettable BCD down counter, 2... "2" detection circuit, 3... 1-bit shift register, 4... Half-bit shift register,
5...Switching circuit, 6...Phase control circuit, 7...Inverter, 8, 10, 11...NAND gate, 9
...toggle flipflop.

Claims (1)

[Claims] 1. A presettable counter that is preset to a predetermined value in response to a preset signal and counts down from the preset value in synchronization with the input signal;
a detection means that detects that the counter value of the counter is a specific value and generates a detection signal; a first delay circuit that delays the detection signal by one cycle of the input signal and outputs the detected signal; a second delay circuit that delays the output of the first delay circuit by a half cycle of the input signal and outputs the delayed output; and when the control signal takes a first level, the output of the first delay circuit is used as the preset signal. means for generating the output of the second delay circuit as the preset signal when the control signal takes a second level; and the means generates the output of the second delay circuit as the preset signal. and means for inverting the phase of said input signal in response to said occurrence and supplying said inverted signal to said presettable counter.