JPS6239447B2 - - Google Patents
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- Publication number
- JPS6239447B2 JPS6239447B2 JP53127968A JP12796878A JPS6239447B2 JP S6239447 B2 JPS6239447 B2 JP S6239447B2 JP 53127968 A JP53127968 A JP 53127968A JP 12796878 A JP12796878 A JP 12796878A JP S6239447 B2 JPS6239447 B2 JP S6239447B2
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- voltage
- circuit
- mosfet
- load
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Description
【発明の詳細な説明】
本発明は、CMOS定電圧回路に係るものであ
る。従来、小型の携帯情報機器のエネルギー源と
て銀―亜鉛電池が広く用いれているが、小型であ
るため電池容量に制限があり、短時間で電池寿命
に致り、電池交換の必要がある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMOS constant voltage circuit. Conventionally, silver-zinc batteries have been widely used as an energy source for small portable information devices, but due to their small size, the battery capacity is limited, and the battery life reaches its end in a short time, making it necessary to replace the battery.
そこで電池交換の煩わしさを省くため、電池の
長寿命化が検討されているが、その一方法として
銀―亜鉛電池を２次電池化し、太陽電池などの充
電手段と組み合わせ、２次電池へ充電することに
より、電池寿命を延ばすことが可能である。 Therefore, in order to eliminate the hassle of battery replacement, extending the life of batteries is being considered. One way to do this is to convert silver-zinc batteries into secondary batteries and combine them with charging means such as solar cells to charge the secondary batteries. By doing so, it is possible to extend the battery life.
しかしながら、２次電池の端子電圧は、一般に
充放電により変動し、この電圧変動が、電子回路
に悪影響を及ぼすことがある。一例として電子腕
時計をとり上げると、電圧変動により、時間基準
信号の周波数変動およびステツプモータのトルク
変動などの好ましくない現象を引き起こす。 However, the terminal voltage of a secondary battery generally fluctuates due to charging and discharging, and this voltage fluctuation may have an adverse effect on electronic circuits. Taking an electronic wristwatch as an example, voltage fluctuations cause undesirable phenomena such as frequency fluctuations in the time reference signal and torque fluctuations in the stepper motor.
本発明は、上記の欠点を除去するようにしたも
ので、導電キヤリアの同タイプのエンハンスメン
トタイプMOSFETとデプリージヨンタイプ
MOSFETのスレツシユホルド電圧（以下ＶTHと
略す）の差を利用して、バラツキ及び温度変化率
の小さい定電圧回路を作り、前記の定電圧回路で
負荷への供給電圧を安定化したものである。 The present invention has been made to eliminate the above-mentioned drawbacks, and has an enhancement type MOSFET and a depletion type MOSFET of the same type with conductive carriers.
By utilizing the difference in threshold voltage (hereinafter abbreviated as VTH ) of MOSFETs, a constant voltage circuit with small variations and a small rate of temperature change is created, and the voltage supplied to the load is stabilized by the constant voltage circuit.
以下図面により本発明を説明する。第１図は、
本発明の定電圧回路を示す。１はＰチヤネルエン
ハンスメントMOSFET（以下PEMOSと略す）
で、ソースは電源のプラス側（以下ＶDDと略す）
に接続され、ゲートは図中Ａ点に接続され、ドレ
インは３のＮチヤネルエンハンスメント
MOSFET（以下NMOSと略す）のドレインとゲ
ートに接続される。NMOS３のゲートはNMOS４
のゲートに接続し、ソースは電源のマイナス側
（以下ＶSSと略す）に接続する。 The present invention will be explained below with reference to the drawings. Figure 1 shows
1 shows a constant voltage circuit of the present invention. 1 is P channel enhancement MOSFET (hereinafter abbreviated as PEMOS)
And the source is the positive side of the power supply (hereinafter abbreviated as V DD )
The gate is connected to point A in the figure, and the drain is connected to the N channel enhancement
Connected to the drain and gate of MOSFET (hereinafter abbreviated as NMOS). The gate of NMOS3 is NMOS4
The source is connected to the negative side of the power supply (hereinafter abbreviated as V SS ).
２はＰチヤネルデプリージヨンMOSFET（以
下PDMOSと略す）で、ソースとゲートは共にＶ
DDに接続され、ドレインはNMOS４のドレインに
接続され。NMOS４のソースはＶSSに接続され
る。 2 is a P-channel depletion MOSFET (hereinafter abbreviated as PDMOS), whose source and gate are both connected to V.
It is connected to DD , and its drain is connected to the drain of NMOS4. The source of NMOS4 is connected to V SS .
５はNMOSで、ソースはＶSSに接続され、ゲー
トはNMOS４のドレインに接続され、ドレインは
負荷回路６を介してＶDDに接続される。 5 is an NMOS whose source is connected to V SS , whose gate is connected to the drain of NMOS 4 , and whose drain is connected to V DD via a load circuit 6 .
７はコンデンサで一方の電極をＶDDに接続し、
他方の電極は、Ａ点を介してコンデンサ８の一方
の電極に接続される。コンデンサ８の他方の電極
はNMOS５のドレインに接続される。 7 is a capacitor with one electrode connected to VDD ,
The other electrode is connected to one electrode of the capacitor 8 via point A. The other electrode of capacitor 8 is connected to the drain of NMOS 5.
上記回路構成において、PEMOS１とPDMOS
２とNMOS３とNMOS４で電圧比較回路を形成す
る。電圧比較回路のうち、PEMOS１とPDMOS
２は入力ゲートとして働き、出力信号はNMOS４
のドレインより出て、NMOS５のゲートを制御す
る。NMOS５のゲートは電圧比較回路の出力信号
で制御され、負荷６に定電圧を供給する役割の電
圧降下用MOSFETである。また、コンデンサ７
とコンデンサ８は、定電圧を分圧する回路を構成
している。 In the above circuit configuration, PEMOS1 and PDMOS
2, NMOS3, and NMOS4 form a voltage comparison circuit. Of the voltage comparison circuits, PEMOS1 and PDMOS
2 works as an input gate, and the output signal is NMOS4
It comes out from the drain of and controls the gate of NMOS5. The gate of the NMOS 5 is controlled by the output signal of the voltage comparison circuit, and is a voltage drop MOSFET that serves to supply a constant voltage to the load 6. Also, capacitor 7
and capacitor 8 constitute a circuit that divides a constant voltage.
以下に回路動作を説明する。以下の説明では、
回路アースをＶDDに取り、電圧はすべてＶDD基準
の値とする。負荷６の端子電圧をＶSLとすると、
負荷６と並列に接続されたコンデンサ７とコンデ
ンサ８の直列接続点Ａの電圧ＶAは次式で表わさ
れる。 The circuit operation will be explained below. In the following explanation,
The circuit ground is set to VDD , and all voltages are based on VDD . If the terminal voltage of load 6 is V SL , then
The voltage V A at the series connection point A of capacitor 7 and capacitor 8 connected in parallel with load 6 is expressed by the following equation.
ＶA＝Ｃ８／Ｃ７＋Ｃ８ＶSL ……(1)
ただしC7；コンデンサ７の静電容量
C8；コンデンサ８の静電容量
(1)式で表わされるＶAは電圧比較回路の
PEMOS１に入力される。電圧比較回路の他方の
入力ゲートPDMOS２の入力電圧ＶBは、回路構
成より明らかであるが、以下の(2)式となる。 V A = C 8 / C 7 + C 8 V SL ...(1) However, C 7 ; Capacitance of capacitor 7 C 8 ; Capacitance of capacitor 8 V A expressed by equation (1) is the voltage comparator circuit's
Input to PEMOS1. As is clear from the circuit configuration, the input voltage V B of the other input gate PDMOS2 of the voltage comparison circuit is expressed by the following equation (2).
ＶB＝Ｏ ……(2)
上記の(1)式と(2)式で表わされる電圧が、電圧比
較回路で比較されるわけであるが、本発明の回路
構成では、２つの入力ゲートMOSFETのスレツ
シユホルド電圧（以下ＶTHと略す）が異なつてい
るため、実効的な入力電圧は以下の様に修正され
る。 V B =O...(2) The voltages expressed by equations (1) and (2) above are compared by a voltage comparison circuit, but in the circuit configuration of the present invention, two input gate MOSFETs Since the threshold voltages (hereinafter abbreviated as V TH ) of the two are different, the effective input voltage is modified as follows.
V′A＝ＶA−ＶTPE ……(1)′
V′B＝ＶB−ＶTPD ……(2)′
ただし、V′A；PEMOS１の実効入力電圧
V′B；PDMOS２の実効入力電圧
ＶTPE；PEMOS１のＶTH
ＶTPD；PDMOS２のＶTH
上記(1)′式と(2)′式は、PEMOS１とPDMOS２
の導電係数Ｋが等しい場合に、MOSFETのオン
抵抗値を決める実効ゲート電圧である。 V′ A = V A −V TPE ……(1)′ V′ B = V B −V TPD ……(2)′ However, V′ A ：Effective input voltage of PEMOS1 V′ B ：Effective input voltage of PDMOS2 V TPE ; V TH of PEMOS1 V TPD ; V TH of PDMOS2 Equations (1)' and (2)' above are for PEMOS1 and PDMOS2.
This is the effective gate voltage that determines the on-resistance value of the MOSFET when the conductivity coefficients K are the same.
電圧比較回路の２入力電圧が等しい時、負荷６
の端子電圧がＶSLとなるように設計すると、(1)式
(1)′式および(2)′式より
ＳSL＝（１＋〓）（ＶTPE−ＶTPD） ……(3)
となる。 When the two input voltages of the voltage comparator circuit are equal, load 6
When designing so that the terminal voltage of is V SL , equation (1) is obtained.
From formulas (1)' and (2)', S SL = (1+〓) (V TPE - V TPD ) ... (3).
ＶSLはコンデンサ７とコンデン８の容量比、あ
るいはＶTPEとＶTPDを制御する事で任意の値を選
べる。 Any value can be selected for V SL by controlling the capacitance ratio of capacitor 7 and capacitor 8, or by controlling V TPE and V TPD .
次に負荷６の端子電圧ＶSLが定電圧となる事を
第２図を用いて説明する。第２図は負荷変動が起
きた場合の例である。縦軸は、NMOS５のソー
ス、ドレイン電流ＩDSを表わし、横軸はNMOS５
ののソース・ドレイン電圧ＶDSを表わしている。
負荷６のインピーダンスを抵抗として話を進め
る。安定状態での負荷インピーダンスを表わした
ものが１１の直線で、この時NMOS５のゲート電
圧をＶG1とすると、NMOS５のＩDS―ＶDS特性は
１３として表わされる。動作点はＣ点となり、負
荷６の端子電圧はＶSLである。 Next, the fact that the terminal voltage V SL of the load 6 becomes a constant voltage will be explained using FIG. 2. FIG. 2 is an example of a case where load fluctuation occurs. The vertical axis represents the source and drain current IDS of NMOS5, and the horizontal axis represents the NMOS5
represents the source-drain voltage V DS of .
Let's proceed by assuming that the impedance of the load 6 is a resistance. The line 11 represents the load impedance in a stable state, and if the gate voltage of the NMOS 5 is V G1 at this time, the I DS -V DS characteristic of the NMOS 5 is represented as 13. The operating point is point C, and the terminal voltage of the load 6 is VSL .
前記の安定状態から、１２で示すごとく負荷が
重くなつた場合は、瞬間的に動作点がＤ点に移
り、負荷６の端子電圧が、ＶSLからＶDに増加す
る。負荷６の端子電圧の増加により(1)式で表わさ
れるＶAも増加し、２入力電圧の関係はＶA＞ＶB
となり、電圧比較回路の出力電圧は、増加する。
前記の出力電圧の増加により、NMOS５のゲート
電圧ＶGは低下する。これは以下の式より明らか
である。 When the load becomes heavy from the above-mentioned stable state as shown at 12, the operating point instantaneously shifts to point D, and the terminal voltage of the load 6 increases from V SL to V D . As the terminal voltage of load 6 increases, V A expressed by equation (1) also increases, and the relationship between the two input voltages is V A > V B
Therefore, the output voltage of the voltage comparison circuit increases.
Due to the above-mentioned increase in the output voltage, the gate voltage V G of the NMOS 5 decreases. This is clear from the equation below.
ＶG＝ＶO―ＶSS
｜ＶO｜＜｜ＶSS｜
ただしＶOは電圧比較回路の出力電圧・NMOS
５のゲート電圧は、負荷６の端子電圧がＶSLにな
るまで低下する。この状態を第２図に示したもの
が、NMOV５のＩDS―ＶDS特性１４であり、ゲ
ート電圧がＶO2まで低下すると、動作点はＥ点と
なり、負荷６の端子電圧はＶSLとなり、安定す
る。 V G =V O -V SS |V O |<|V SS | However, V O is the output voltage of the voltage comparator circuit/NMOS
The gate voltage of 5 decreases until the terminal voltage of load 6 reaches V SL . This state is shown in FIG. 2 as the I DS -V DS characteristic 14 of NMOV5. When the gate voltage drops to V O2 , the operating point becomes point E, and the terminal voltage of the load 6 becomes V SL , Stabilize.
負荷が軽くなつた場合も、同様にしてNMOS５
のゲート電圧が増加し、負荷６の端子電圧はＶSL
に安定する。上記のごとく負荷６の端子電圧は、
負荷変動が起きた場合、定電圧化される。電源電
圧が変動した場合にも、全く同様にして、負荷６
の端子電圧が定電圧化される。 Similarly, when the load becomes lighter, NMOS5
The gate voltage of load 6 increases, and the terminal voltage of load 6 becomes V SL
becomes stable. As mentioned above, the terminal voltage of load 6 is
When load fluctuation occurs, the voltage is made constant. Even when the power supply voltage fluctuates, the load 6
The terminal voltage of is made constant.
また本発明の回路構成によれば、定電圧ＶSLの
設計にPMOSの異るＶTHの差（ＶTPE―ＶTPD）と
コンデンサの静電容量比を用いているため、回路
のIC化を行つた場合、プロセスのバラツキの影
響を少なくでき、良好なる定電圧精度を保証でき
る。この理由を以下に述べる。 Furthermore, according to the circuit configuration of the present invention, since the difference in V TH between different PMOSs (V TPE - V TPD ) and the capacitance ratio of the capacitor are used to design the constant voltage V SL , it is possible to integrate the circuit into an IC. If this is done, the influence of process variations can be reduced and good constant voltage accuracy can be guaranteed. The reason for this will be explained below.
一般にMOSFETのＶTHのバラツキは、±0.1V程
度で、充分に制御されているとは言いにくい。こ
のＶTHバラツキの要因は、IC表面電荷や基板不
純物濃度のバラツキと考えられている。このよう
に一つのＶTHについて見ればバラツキは大きい
が、同一ICチツプ上に、イオン打込みなどの手
段でＶTHの異る値を持つ、２つのPMOSFETに
ついて見れば、各々のＶTHのバラツキは同じ傾向
と考えられる。したがつて２つのPMOSFETの
ＶTHの差をとれば、表面電荷や基板不純物濃度の
バラツキは相殺され、そのバラツキは非常に小さ
くなる。 Generally, the variation in MOSFET V TH is about ±0.1V, and it is difficult to say that it is sufficiently controlled. The cause of this V TH variation is considered to be variation in IC surface charge and substrate impurity concentration. In this way, when looking at one V TH , the variation is large, but when looking at two PMOSFETs on the same IC chip that have different values of V TH due to means such as ion implantation, the variation in each V TH is small. It is thought that the same trend exists. Therefore, by taking the difference in V TH between the two PMOSFETs, the variations in surface charge and substrate impurity concentration are canceled out, and the variations become extremely small.
またコンデンサをIC内に作つた場合、静電容
量のバラツキは有るが、複数個のコンデンサの静
電容量比は、コンデンサの面積比で決まり、IC
上の幾可学寸法の比は、高精度で作れるため、バ
ラツキが小さい。 Furthermore, when capacitors are built inside an IC, there are variations in capacitance, but the capacitance ratio of multiple capacitors is determined by the area ratio of the capacitors, and the
The ratio of the above geometric dimensions can be made with high precision, so the variation is small.
上記理由で、(3)式で表わされる定電圧は高精度
に作れる。 For the above reasons, the constant voltage expressed by equation (3) can be created with high precision.
また本発明の回路構成によれば、定電圧分圧回
路をコンデンサ７とコンデンサ８の２つのコンデ
ンサの直列接続で構成しているため、定電圧分圧
回路での消費電流はほとんど無い。 Further, according to the circuit configuration of the present invention, since the constant voltage voltage divider circuit is configured by connecting two capacitors, capacitor 7 and capacitor 8, in series, there is almost no current consumption in the constant voltage voltage divider circuit.
以上の説明は、電圧比較回路の入力ゲートに、
PEMOSとPDMOSを用いた場合について行つた
が、ＮチヤンネルエンハンスメントMOSFETと
ＮチヤネルデブリージヨンMOSFETで回路を構
成できることは言うまでもない。 In the above explanation, at the input gate of the voltage comparator circuit,
Although we have discussed the case where PEMOS and PDMOS are used, it goes without saying that the circuit can be configured with an N-channel enhancement MOSFET and an N-channel debridement MOSFET.
上記のように本発明では、Ｐチヤネルエンハン
スメントMOSFETとＰチヤネルデブリージヨン
MOSFETとい、同極性でＶTHの異なるMOSFET
を入力ゲートとした電圧比較回路と、電圧降下用
MOSFETと、定電圧分圧用コンデンサを用い
て、定電圧回路を構成しており、定電圧が、静電
容量の比と、ＶTH差の積で表わされ、したがつて
定電圧レベルを任意に選ぶことができ、高精度
で、負荷変動および電圧変動に強く、低消費電力
の定電圧回路を作ることができるため、充電シス
テムで長寿命化をねらう機器に使用すれば、２次
電池の電圧変動を受けずに、信頼性の高い電子回
路を提供できる。 As described above, the present invention uses a P channel enhancement MOSFET and a P channel debridement MOSFET.
MOSFETs are MOSFETs with the same polarity but different V TH
A voltage comparator circuit with an input gate and a voltage drop
A constant voltage circuit is constructed using a MOSFET and a constant voltage dividing capacitor, and the constant voltage is expressed as the product of the capacitance ratio and the V TH difference. Therefore, the constant voltage level can be set arbitrarily. It is possible to create a constant voltage circuit that is highly accurate, resistant to load fluctuations and voltage fluctuations, and has low power consumption.If used in devices that aim to extend the life of the charging system, it can be used to A highly reliable electronic circuit can be provided without undergoing voltage fluctuations.
第１図は、本発明の定電圧回路の実施例を示す
図、第２図は、MOSFET５と負荷６の電圧―電
流特性を示す図である。
１……Ｐチヤネルエンハンスメントタイプ
MOSFET、２……Ｐチヤネルデブリージヨンタ
イプMOSFET、３，４……Ｎチヤネルエンスメ
ントタイプMOSFET、５……電圧降下用
MOSFET、６……負荷、７，８……定電圧分圧
用コンデンサ。
FIG. 1 is a diagram showing an embodiment of the constant voltage circuit of the present invention, and FIG. 2 is a diagram showing the voltage-current characteristics of the MOSFET 5 and the load 6. 1...P channel enhancement type
MOSFET, 2...P channel debridement type MOSFET, 3, 4...N channel enforcement type MOSFET, 5...For voltage drop
MOSFET, 6...Load, 7, 8...Capacitor for constant voltage division.
Claims (1)
直列接続される複数のコンデンサと、前記複数の
コンデンサの接続点より出力される分圧電圧を入
力する電圧比較回路と、電源の他方の端子と前記
出力端子との間に接続され前記電圧比較回路の出
力を受けて接続端子間の電圧を変化させる電圧降
下用MOSFETとで構成される定電圧回路におい
て、 前記電圧比較回路は、前記分圧電圧を入力する
入力トランジスタがエンハンスメント型の第一の
MOSFETで構成され、他方の入力トランジスタ
が前記第一のMOSFETと同極性でかつデプリー
ジヨン型の特性を有しゲート電極とソース電極を
接続した第二のMOSFETで構成され、 前記複数のコンデンサは、前記電圧比較回路と
同一のICに内蔵されていることを特徴とする定
電圧回路。[Claims] 1. A voltage comparison circuit that receives a plurality of capacitors connected in series between one terminal of a power supply and an output terminal of a circuit, and a divided voltage output from a connection point of the plurality of capacitors. and a voltage drop MOSFET that is connected between the other terminal of the power supply and the output terminal and receives the output of the voltage comparison circuit to change the voltage between the connection terminals, the voltage In the comparator circuit, the input transistor that inputs the divided voltage is an enhancement type first transistor.
a second MOSFET whose other input transistor has the same polarity as the first MOSFET and has depletion type characteristics and whose gate electrode and source electrode are connected; A constant voltage circuit characterized by being built into the same IC as the voltage comparison circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12796878A JPS5553709A (en) | 1978-10-18 | 1978-10-18 | Constant voltage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12796878A JPS5553709A (en) | 1978-10-18 | 1978-10-18 | Constant voltage circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5553709A JPS5553709A (en) | 1980-04-19 |
| JPS6239447B2 true JPS6239447B2 (en) | 1987-08-24 |
Family
ID=14973131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12796878A Granted JPS5553709A (en) | 1978-10-18 | 1978-10-18 | Constant voltage circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5553709A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60215223A (en) * | 1984-04-10 | 1985-10-28 | Mitsubishi Electric Corp | Dc voltage generating circuit |
| KR910007740B1 (en) * | 1989-05-02 | 1991-09-30 | 삼성전자 주식회사 | Power voltage tracking circuit for bit line stabilization |
| JP3494488B2 (en) * | 1994-11-25 | 2004-02-09 | 株式会社ルネサステクノロジ | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3975648A (en) * | 1975-06-16 | 1976-08-17 | Hewlett-Packard Company | Flat-band voltage reference |
| JPS52123101A (en) * | 1976-04-08 | 1977-10-17 | Fujitsu Ltd | Power source circuit for mosic |
-
1978
- 1978-10-18 JP JP12796878A patent/JPS5553709A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5553709A (en) | 1980-04-19 |
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