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JPS6239708B2 - - Google Patents
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JPS6239708B2 - - Google Patents

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Publication number
JPS6239708B2
JPS6239708B2 JP55051471A JP5147180A JPS6239708B2 JP S6239708 B2 JPS6239708 B2 JP S6239708B2 JP 55051471 A JP55051471 A JP 55051471A JP 5147180 A JP5147180 A JP 5147180A JP S6239708 B2 JPS6239708 B2 JP S6239708B2
Authority
JP
Japan
Prior art keywords
circuit board
circuit
check
voltage
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55051471A
Other languages
Japanese (ja)
Other versions
JPS56148072A (en
Inventor
Takeshi Ooami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP5147180A priority Critical patent/JPS56148072A/en
Publication of JPS56148072A publication Critical patent/JPS56148072A/en
Publication of JPS6239708B2 publication Critical patent/JPS6239708B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

【発明の詳細な説明】 本発明はプリント基板等の回路基板の検査装置
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection device for circuit boards such as printed circuit boards.

プリント基板等の回路基板の検査方法には、回
路動作させることによつて動作確認をなす動作チ
エツク方式や各測定箇所の電圧を測定するDCチ
エツク方点等がある。前者はローコストにて検査
可能である反面異なる回路素子を基板に挿入接続
した場合に回路定数が異常であつても回路動作異
常として認識しえないケースがあつて信頼性に乏
しい欠点がある。後者のDCチエツク方式では各
チエツクポイントの電圧値の標準値を定めてこれ
を記憶装置に記憶せしめておき、この記憶データ
と測定データとの比較を行う必要があり、装置の
価格が高くなる欠点がある。更には測定データを
デイジタル値に変換する関係上、低速動作をよぎ
なくされるA/D変換器が必要となつて測定時間
の増大を招来している。また、測定点の増大は避
けられずよつて接触子の接触不良による信頼度低
下をも招来することになる。
Inspection methods for circuit boards such as printed circuit boards include an operation check method in which the operation of the circuit is confirmed by operating the circuit, and a DC check method in which the voltage at each measurement point is measured. Although the former method can be tested at low cost, it has the disadvantage of poor reliability because even if a circuit constant is abnormal when a different circuit element is inserted and connected to a board, it may not be recognized as an abnormality in circuit operation. In the latter DC check method, it is necessary to determine a standard voltage value for each check point, store it in a memory device, and then compare this stored data with measured data, which has the disadvantage of increasing the price of the device. There is. Furthermore, in order to convert measurement data into digital values, an A/D converter that operates at low speed is required, resulting in an increase in measurement time. Furthermore, an increase in the number of measurement points is unavoidable, which leads to a decrease in reliability due to poor contact of the contacts.

本発明の目的は極めて簡単な構成で信頼性の良
好な回路基板の検査装置を提供することである。
An object of the present invention is to provide a circuit board inspection device with an extremely simple configuration and high reliability.

本発明の検査装置は、被検査回路基板とこの基
板に対して標準となるべき回路網を有する基準回
路基板を準備し、これら両回路基板の各回路網上
の任意のそれぞれ対応する第1及び第2チエツク
箇所を選択し、被検査回路基板の第1チエツク箇
所と基準回路基板の第2チエツク箇所とを接続
し、被検査回路基板の第2チエツク箇所と基準回
路基板の第1チエツク箇所との間に一定電圧Vを
印加し、上記チエツク箇所の接続点の電圧状態に
より被検査回路基板の第1及び第2チエツク箇所
間の回路の良否を判別しつつこれら第1及び第2
チエツク箇所の選択を順次切換えることによつて
回路基板の良否を検査するようにした装置であつ
て、接続点の電圧状態を検出する検出手段は当該
接続点の電圧がV/2(1±δ)(δは一定)の範
囲内にあることを検出して良信号を出力する回路
を有することを特徴としている。
The inspection apparatus of the present invention prepares a reference circuit board having a circuit board to be tested and a circuit network that is to be a standard for this board, and selects arbitrary corresponding first and second circuit boards on each circuit network of both circuit boards. Select the second check point, connect the first check point on the circuit board under test and the second check point on the reference circuit board, and connect the second check point on the circuit board under test to the first check point on the reference circuit board. A constant voltage V is applied between the first and second check points, and the quality of the circuit between the first and second check points of the circuit board to be inspected is determined based on the voltage state of the connection point of the above-mentioned check points.
This is a device that tests the quality of a circuit board by sequentially switching the selection of check points, and the detection means for detecting the voltage state of a connection point is such that the voltage at the connection point is V/2 (1 ± δ ) (where δ is constant) and outputs a good signal.

この誤差範囲を示す±δなる値を所望に可変設
定すべく、可変抵抗器や複数の異なる値の抵抗を
用いることを特徴としている。
It is characterized by using a variable resistor or a plurality of resistors with different values in order to variably set the value of ±δ indicating this error range as desired.

以下に本発明を図面を用いて説明する。 The present invention will be explained below using the drawings.

第1図は被検査回路基板の回路網の模式図であ
り、Z0〜Z11は基本となる回路又は素子を示し、
TP1〜TP5はチエツク箇所を示すチエツク端子で
ある。第2図はこの被検査回路基板に対して標準
となるべき回路網を有する基準回路基板すなわち
正常回路網を有する良品サンプル回路基板の回路
網の模式図であり、第1図と同様Z0′〜Z11′は基本
となる回路又は回路素子を示し、TP0′〜TP5′は
チエツク箇所を示すチエツク端子である。両図に
おいて各チエツク端子TP0〜TP11とTP0′〜
TP11′とはそれぞれ回路網上の対応する等しい箇
所に設けられているものとする。
FIG. 1 is a schematic diagram of the circuit network of the circuit board to be inspected, where Z 0 to Z 11 indicate basic circuits or elements,
TP 1 to TP 5 are check terminals indicating check points. FIG. 2 is a schematic diagram of the circuit network of a reference circuit board that has a circuit network that should be the standard for this circuit board to be tested, that is, a good sample circuit board that has a normal circuit network . -Z11 ' indicate basic circuits or circuit elements, and TP0 ' to TP5 ' are check terminals indicating check points. In both figures, each check terminal TP 0 ~ TP 11 and TP 0 ′ ~
It is assumed that TP 11 ' are provided at corresponding and equal locations on the circuit network.

このような二つの回路基板を準備した後、例え
ば第3図に示す如き接続状態の動作を考える。す
なわち第1図に示す被検査回路基板の第1及び第
2のチエツク端子TP0とTP1との間の回路の良否
を判別する場合において、チエツク端子TP0に例
えば正の一定電圧+Vを印加し、他方のチエツク
端子TP1を基準回路基板の対応する第1のチエツ
ク端子TP0′に直接接続し、基準回路基板の対応
する他方の第2チエツク端子TP1′を接地する構
成とする。このとき、両回路基板の回路網には何
ら電源電圧は印加しないものとすると、被検査回
路基板の第1及び第2のチエツク端子TP0とTP1
との間の直流インピーダンス成分X1と基準回路
基板の第1及び第2のチエツク端子TP0′と
TP1′との間の直流インピーダンス成分X1′とが等
しければ、端子TP1とTP0′との間の接続点の電位
V0はV/2となることは明白である。換言すれ
ば、端子TP0とTP1との間において半田ブリツジ
による短絡、パターン切れによる開放、誤抵抗、
欠品、半導体素子の逆挿入等の不良が存在すれ
ば、当該接続点の電位V0はV/2からはずれる
ことになり、結果としてこの接続点の電位状態を
知ることにより両端子間の回路の良否が判別可能
となることが判る。ここで、回路素子間には当然
一定範囲のバツラキが存在するために、当該接続
点の電位V0はV/2(1±δ)なる範囲の値をもつ
て変動するものであるから、これ以上の値にあれ
ば両端子間の回路は良と判定するようにすればよ
い。尚δは一定の誤差範囲を示す値であつて回路
網等により決定されるものである。
After preparing such two circuit boards, consider the operation of the connected state shown in FIG. 3, for example. That is, when determining the quality of the circuit between the first and second check terminals TP 0 and TP 1 of the circuit board to be inspected shown in FIG. 1, for example, a constant positive voltage +V is applied to the check terminal TP 0 . The other check terminal TP 1 is directly connected to the corresponding first check terminal TP 0 ' of the reference circuit board, and the other corresponding second check terminal TP 1 ' of the reference circuit board is grounded. At this time, assuming that no power supply voltage is applied to the circuit networks of both circuit boards, the first and second check terminals TP 0 and TP 1 of the circuit board to be tested are
and the DC impedance component X 1 between the first and second check terminals TP 0 ' of the reference circuit board and
If the DC impedance component X 1 ′ between terminals TP 1 and
It is clear that V 0 is V/2. In other words, short circuits due to solder bridges, open circuits due to pattern breakage , erroneous resistance, and
If there is a defect such as a missing item or reverse insertion of a semiconductor element, the potential V 0 of the connection point will deviate from V/2, and as a result, by knowing the potential state of this connection point, the circuit between both terminals can be corrected. It can be seen that it is possible to determine the quality of the product. Here, since there is naturally a certain range of variation between circuit elements, the potential V 0 at the connection point fluctuates within a range of V/2 (1 ± δ). If the value is above, it may be determined that the circuit between both terminals is good. Note that δ is a value indicating a certain error range and is determined by the circuit network or the like.

第3図に示した原理を一般的に示した例が第4
図であつて、本発明の一実施例を説明する模式的
等価回路図である。一定電圧+Vを被検査回路基
板の1チエツク端子に選択的に印加すべく選択ス
イツチS1が設けられ、このスイツチS1により選択
されたチエツク端子TP2との間の回路良否を判別
する他方のチエツク端子TP3を選択する選択スイ
ツチS2が設けられている。そして基準回路基板の
被検査回路基板におけるスイツチS1により選択さ
れたチエツク端子TP2と対応するチエツク端子
TP2′を選択して、先のスイツチS2により選択さ
れた被検査回路基板のチエツク端子TP3とを接続
するスイツチS3が設けられ、また、スイツチS2
より選択されたチエツク端子TP3と対応する基準
回路基板のチエツク端子TP3′を選択して接地す
るスイツチS4が設けられる。
A general example of the principle shown in Figure 3 is shown in Figure 4.
1 is a schematic equivalent circuit diagram illustrating an embodiment of the present invention. FIG. A selection switch S1 is provided to selectively apply a constant voltage +V to one check terminal of the circuit board to be inspected, and a selection switch S1 is provided to selectively apply a constant voltage + V to one check terminal of the circuit board under test. A selection switch S2 is provided for selecting the check terminal TP3 . and a check terminal corresponding to check terminal TP 2 selected by switch S 1 on the circuit board to be tested of the reference circuit board.
A switch S3 is provided which selects TP2' and connects it to the check terminal TP3 of the circuit board to be inspected selected by the previous switch S2 , and also connects the check terminal TP3 selected by the switch S2 . A switch S4 is provided for selecting and grounding the check terminal TP3 ' of the reference circuit board corresponding to the reference circuit board.

スイツチS2とS3との共通接続点の電位V0を検
出すべく、第1及び第2のコンパレータ1及び2
が設けられて、この電位V0が1入力となつてい
る。そして各他入力としては、基準電圧源+Vを
分圧する分圧回路3の分圧出力V1及びV2がそれ
ぞれ用いられる。この分圧回路3は例えば図のよ
うに抵抗R1,R2及び可変抵抗VRの直列接続回路
より成つており、可変抵抗VRの値を任意に設定
することによつて先述した回路素子のバラツキに
起因する誤差範囲±δを定めることが可能であ
る。こうすることによつて+V/2(1±δ)を
越える電圧V0がコンパレータ1,2へ入力され
るとそれに応じてコンパレータ1,2のいずれか
の出力OUT−1又はOUT−2が変化して異常が
判別可能である。当該コンパレータ1,2により
いわゆるウインドコンパレータ回路が構成されて
いるものである。
In order to detect the potential V 0 at the common connection point of switches S 2 and S 3 , first and second comparators 1 and 2 are connected.
is provided, and this potential V 0 serves as one input. As the other inputs, the divided voltage outputs V 1 and V 2 of the voltage dividing circuit 3 that divides the reference voltage source +V are used, respectively. For example, as shown in the figure, this voltage divider circuit 3 is made up of a series connection circuit of resistors R 1 and R 2 and a variable resistor VR, and by setting the value of the variable resistor VR arbitrarily, the above-mentioned variations in circuit elements can be eliminated. It is possible to define an error range ±δ due to . By doing this, when a voltage V0 exceeding +V/2 (1±δ) is input to comparators 1 and 2, the output OUT-1 or OUT-2 of either comparator 1 or 2 changes accordingly. Abnormalities can be determined by The comparators 1 and 2 constitute a so-called window comparator circuit.

そして、各スイツチS1〜S4をそれぞれ適当に制
御して被検査回路基板の任意の2つのチエツク端
子間の回路の良否が検査可能となることは明白で
ある。
It is clear that the circuits between any two check terminals of the circuit board to be tested can be inspected by appropriately controlling each of the switches S1 to S4 .

尚、基準回路基板側のチエツク端子の1つに正
(又は負)の一定電圧を印加するようにしても良
く、要は、両回路基板の1組の対応するチエツク
端子の互いに反対のチエツク端子間に、例えば第
4図においてはTP3とTP2′との間に一定電圧を印
加するようにすれば良いことは勿論である。
Incidentally, a constant positive (or negative) voltage may be applied to one of the check terminals on the reference circuit board side, and in short, a set of corresponding check terminals on both circuit boards is applied to the opposite check terminals. Of course, a constant voltage may be applied between TP 3 and TP 2 ' in FIG. 4, for example.

スイツチS1〜S4の制御はマイクロコンピユータ
等の制御装置により決められたプログラムに従つ
て行われるようにすることができ、また、出力
OUT−1,2の判別もマイクロコンピユータ等
のプロセツサによつて処理判断すれば、極めて高
速の検査装置となりうる。
The switches S 1 to S 4 can be controlled according to a program determined by a control device such as a microcomputer, and the output
If the discrimination between OUT-1 and OUT-2 is also processed and determined by a processor such as a microcomputer, it can be an extremely high-speed inspection device.

第4図の例においては誤差範囲±δの設定のた
めに可変抵抗器VRを用いているが、かかる方法
では回路素子のバラツキをある一定値δに定めれ
ば、後は可変が困難である。しかしながら実際に
は回路基板上の多数のチエツク箇所間におけるイ
ンピーダンスは良品であつてもバラツキが大きい
箇所も多く存在して一様ではない。故に誤差±δ
は最大値に設定せざるを得ずその結果不良箇所の
検出能力が低下することになる。
In the example shown in Fig. 4, a variable resistor VR is used to set the error range ±δ, but with this method, once the variation in circuit elements is set to a certain constant value δ, it is difficult to change it afterwards. . However, in reality, the impedance among the many check points on the circuit board is not uniform, as there are many places where there are large variations even if the board is of good quality. Therefore, the error ±δ
must be set to the maximum value, and as a result, the ability to detect defective locations is reduced.

かかる欠点を解決した例が第5図に示されてお
り、第4図と同等部分は同一符号により示されて
いる。図において誤差範囲±δを定める回路とし
て、可変抵抗器の代りに値の異なる複数の抵抗
R10〜R1oを設けてこれ等抵抗の1つをスイツチ
S5及びS6により選択して基準電圧V1,V2を得る
ようにしたものである。従つて抵抗R1及びR2
共に等しくRとして1つの抵抗R1i(i=0〜
n)を選択した場合には誤差範囲の値δiは次式
となる。
An example in which this drawback has been solved is shown in FIG. 5, in which parts equivalent to those in FIG. 4 are designated by the same reference numerals. In the figure, as a circuit to determine the error range ±δ, multiple resistors with different values are used instead of a variable resistor.
Set R 10 to R 1o and switch one of these resistors.
The reference voltages V 1 and V 2 are obtained by selecting S 5 and S 6 . Therefore, assuming that both resistors R 1 and R 2 are equally R, one resistor R 1i (i=0 to
When n) is selected, the value δi of the error range becomes the following equation.

δi=R1i/2R+R1i ………(1) 例えばR=1KΩ、R10=100Ω、R11=220Ω、
R12=470Ω、R13=2KΩ、R14=12KΩとすればそ
れぞれδiはδ=4.8%、δ=9.9%、δ
19%、δ=50%、δ=86%となるから、スイ
ツチS5及びS6を互いに同期して切換え制御するよ
うにすれば、誤差範囲の選定が所望になされる。
δi=R 1i /2R+R 1i (1) For example, R=1KΩ, R10 =100Ω, R11 =220Ω,
If R 12 = 470Ω, R 13 = 2KΩ, and R 14 = 12KΩ, δi is δ 0 = 4.8%, δ 1 = 9.9%, δ 2 =
19%, δ 3 =50%, and δ 4 =86%. Therefore, if the switches S 5 and S 6 are switched and controlled in synchronization with each other, the error range can be selected as desired.

以上の如く、本発明によれば極めて簡単な構成
にて高速かつ高信頼性を有する検査方式が可能と
なる利点を有する。
As described above, the present invention has the advantage of enabling a high-speed and highly reliable inspection method with an extremely simple configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は被検査回路基板の回路網の模式図、第
2図は第1図の被検査回路基板に対して標準とな
るべき基準回路基板の回路網の模式図、第3図は
本発明の原理を説明するための模式図、第4図は
本発明の一実施例を説明するための模式図、第5
図は本発明の他の実施例を説明するための模式図
である。 主要部分の符号の説明、TP0〜TPo……被検査
回路基板チエツク端子、TP0′〜TPo′……基準回
路基板チエツク端子、VR……誤差範囲設定用可
変抵抗器、R10〜R1o……誤差範囲設定用抵抗、
S1〜S6……スイツチ。
Fig. 1 is a schematic diagram of the circuit network of the circuit board to be tested, Fig. 2 is a schematic diagram of the circuit network of the reference circuit board that is to be the standard for the circuit board to be tested in Fig. 1, and Fig. 3 is a schematic diagram of the circuit network of the circuit board to be tested. FIG. 4 is a schematic diagram for explaining an embodiment of the present invention, and FIG.
The figure is a schematic diagram for explaining another embodiment of the present invention. Explanation of the symbols of the main parts, TP 0 ~ TP o ... Tested circuit board check terminal, TP 0 ′ ~ TP o ′ ... Reference circuit board check terminal, VR ... Variable resistor for setting error range, R 10 ... R1o ...Resistance for error range setting,
S 1 ~ S 6 ... switch.

Claims (1)

【特許請求の範囲】 1 被検査回路基板及びこの被検査回路基板に対
して標準となるべき回路網を有する基準回路基板
の各回路網の任意のそれぞれ対応する第1チエツ
ク箇所と同じくそれぞれ対応する第2チエツク箇
所とを選択する手段と、前記被検査回路基板の第
1チエツク箇所と前記基準回路基板の第2チエツ
ク箇所とを共通接続点にて接続する手段と、前記
被検査回路基板の第2チエツク箇所と前記基準回
路基板の第1チエツク箇所との間に一定電圧Vを
印加する手段と、前記共通接続点の電圧を検出し
て前記被検査回路基板の第1及び第2チエツク箇
所間の回路の良否信号を出力する電圧検出手段と
を含み、前記第1及び第2チエツク箇所の選択を
順次切換えることにより回路基板の良否を検査す
るようにした回路基板検査装置であつて、前記電
圧検出手段は前記共通接続点の電圧が(V/2)
×(1±δ)(δは前記被検査回路基板の第1チエ
ツク箇所と第2チエツク箇所間のインピーダンス
の許容範囲に応じた値)の範囲内にあることを検
出して良信号を出力する回路を有することを特徴
とする回路基板検査装置。 2 前記電圧検出手段は(V/2)×(1±δ)な
る基準電圧を発生する基準電圧発生手段と、前記
基準電圧と前記共通接続点の電圧とを比較するコ
ンパレータとを含むことを特徴とする特許請求の
範囲第1項記載の装置。 3 前記基準電圧発生回路は前記基準電圧の±δ
なる値を可変する可変抵抗器を有することを特徴
とする特許請求の範囲第2項記載の装置。 4 前記基準電圧発生回路は複数の異なる値を有
する抵抗と、前記抵抗の1つを選択して前記基準
電圧の±δなる値を所望に選定する抵抗選択回路
とを有することを特徴とする特許請求の範囲第2
項記載の装置。
[Scope of Claims] 1. Corresponding to any corresponding first check point of each circuit network of a circuit board to be inspected and a reference circuit board having a circuit network to be a standard for this circuit board to be inspected. means for connecting the first check point of the circuit board to be inspected and the second check point of the reference circuit board at a common connection point; means for applying a constant voltage V between the second check point and the first check point of the reference circuit board; a voltage detecting means for outputting a pass/fail signal of the circuit, the circuit board testing device is configured to test the pass/fail of the circuit board by sequentially switching selections of the first and second check points, the circuit board testing device comprising: The detection means detects that the voltage at the common connection point is (V/2)
×(1±δ) (δ is a value according to the permissible range of impedance between the first and second check points of the circuit board to be inspected) and outputs a good signal. A circuit board inspection device characterized by having a circuit. 2. The voltage detection means includes a reference voltage generation means that generates a reference voltage of (V/2)×(1±δ), and a comparator that compares the reference voltage with the voltage at the common connection point. An apparatus according to claim 1. 3 The reference voltage generation circuit is configured to generate ±δ of the reference voltage.
3. The device according to claim 2, further comprising a variable resistor that changes the value of the resistor. 4. A patent characterized in that the reference voltage generation circuit has a plurality of resistors having different values, and a resistance selection circuit that selects one of the resistors to select a desired value of ±δ of the reference voltage. Claim 2
Apparatus described in section.
JP5147180A 1980-04-18 1980-04-18 Device for checking circuit substrate Granted JPS56148072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5147180A JPS56148072A (en) 1980-04-18 1980-04-18 Device for checking circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5147180A JPS56148072A (en) 1980-04-18 1980-04-18 Device for checking circuit substrate

Publications (2)

Publication Number Publication Date
JPS56148072A JPS56148072A (en) 1981-11-17
JPS6239708B2 true JPS6239708B2 (en) 1987-08-25

Family

ID=12887855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5147180A Granted JPS56148072A (en) 1980-04-18 1980-04-18 Device for checking circuit substrate

Country Status (1)

Country Link
JP (1) JPS56148072A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56746B2 (en) * 1972-02-14 1981-01-09

Also Published As

Publication number Publication date
JPS56148072A (en) 1981-11-17

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