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JPS6239825B2 - - Google Patents
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JPS6239825B2 - - Google Patents

Info

Publication number
JPS6239825B2
JPS6239825B2 JP56176799A JP17679981A JPS6239825B2 JP S6239825 B2 JPS6239825 B2 JP S6239825B2 JP 56176799 A JP56176799 A JP 56176799A JP 17679981 A JP17679981 A JP 17679981A JP S6239825 B2 JPS6239825 B2 JP S6239825B2
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor
heat dissipation
external lead
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56176799A
Other languages
Japanese (ja)
Other versions
JPS5878443A (en
Inventor
Takashi Myamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56176799A priority Critical patent/JPS5878443A/en
Publication of JPS5878443A publication Critical patent/JPS5878443A/en
Publication of JPS6239825B2 publication Critical patent/JPS6239825B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00Packaging processes not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Laser Beam Processing (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法にかかり、特に
高電力消費の半導体装置の製造方法の改良に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing a semiconductor device with high power consumption.

近年の半導体装置は、特に計算機等に使われる
ものは高速の演算スピードを要求されるようにな
り、半導体素子の高集積化、高消費電力化がなさ
れるようになつてきている。これに伴つて、1つ
の半導体素子が発する熱量も多大なものとなり、
これを搭載するケースも、放熱特性の良いものが
要求されるようになつてきた。ケースの放熱特性
を上昇させるためには2つのアプローチの仕方が
ある。1つは熱伝導率の高い材料を選択するこ
と、他の1つは放熱の容易な構造にすることであ
る。熱伝導率の高い材料として先づ金属が挙げら
れるが、金属は一般に熱膨張率も高く、他の材料
との整合性を考慮すると選択の範囲は狭まり、結
局高価なものとなつてしまう。また、ベリリア
(BeO)や炭化硅素(SiC)のように電気絶縁性
で熱伝導率が高く且つ熱膨張率の低い材料もある
が、今のところ高価であつたり、粉末に毒性があ
る等の問題があり、使用の範囲が限定される。一
方、放熱の容易な構造としてはヒート・パイプや
放熱フイン等がある。しかし、ヒート・パイプは
構造が複雑になり、末だ十分な信頼性を有するに
は至つてはいない。現在、最も容易で比較的高い
放熱特性が得られる構造はフイン付のケースであ
る。
2. Description of the Related Art In recent years, semiconductor devices, especially those used in computers and the like, are required to have high calculation speeds, and semiconductor elements are becoming more highly integrated and consume more power. Along with this, the amount of heat generated by one semiconductor element has also increased,
The cases in which these devices are installed are also required to have good heat dissipation characteristics. There are two approaches to increasing the heat dissipation characteristics of the case. One is to select a material with high thermal conductivity, and the other is to have a structure that facilitates heat dissipation. Metals are cited first as materials with high thermal conductivity, but metals generally also have a high coefficient of thermal expansion, and when compatibility with other materials is taken into consideration, the range of selection is narrowed, and they end up being expensive. In addition, there are materials such as beryllia (BeO) and silicon carbide (SiC) that are electrically insulating, have high thermal conductivity, and have a low coefficient of thermal expansion, but they are currently expensive and the powder is toxic. There are problems and the scope of use is limited. On the other hand, structures that allow easy heat dissipation include heat pipes and heat dissipation fins. However, heat pipes have complicated structures and have not yet achieved sufficient reliability. Currently, the structure that is easiest and provides relatively high heat dissipation characteristics is a case with fins.

これまでの放熱フイン付きのケースは、例えば
第1図のような形態が代表的である。即ち、セラ
ミツク基板1の下面に外部リードピン2が配列さ
れ、反対の面に放熱フイン3が取り付けられたも
のである。一般に放熱フインは、外部リードピン
の植立されている面とは反対側に取り付けられ
る。これは、半導体装置をプリント基板に実装し
た時に、送風によりフインから放熱し易くする為
である。しかし、従来のこの種の構造には放熱と
いう点で極めて不利な欠陥を有する。それは第2
図に断面図で示したように、半導体素子4から発
生した熱は、半導体素子が固着されているセラミ
ツク基板1に伝わり、それがフイン3に伝導され
て放熱されるという経路をとる為、伝導路が長く
なり熱抵抗が大きくなるという点である。従つ
て、放熱性を改善する為には、第3図のように、
半導体素子4を外部リードピン2が囲んだ面に固
着し、その固着面からセラミツク基板を挾んで直
接にフインに熱を逃がす必要がある。しかし、こ
のパツケージ構造を得る為には、半導体素子の封
止法を改善する必要がある。セラミツク・ケース
の従来からある封止法は、セラミツク製キヤツプ
をエポキシ系樹脂で接着したり、シリコーン系あ
るいはエポキシ系樹脂を流し込んだりする簡単な
ものから、セラミツク製キヤツプにガラス粉末を
塗布し融かして接着するフリツトシール、ハンダ
で金属板を固着するハンダシール、Au/Sn合金
で金属板を固着するAu/Snシール、そして最も
一般的に使われているシームウエルド等がある。
A typical example of conventional cases with heat dissipation fins is as shown in FIG. That is, external lead pins 2 are arranged on the lower surface of a ceramic substrate 1, and heat dissipation fins 3 are attached to the opposite surface. Generally, the heat dissipation fins are attached to the side opposite to the surface on which the external lead pins are planted. This is to facilitate heat dissipation from the fins by blowing air when the semiconductor device is mounted on a printed circuit board. However, this type of conventional structure has a drawback that is extremely disadvantageous in terms of heat dissipation. That's the second
As shown in the cross-sectional view in the figure, the heat generated from the semiconductor element 4 is transmitted to the ceramic substrate 1 to which the semiconductor element is fixed, and then is conducted to the fins 3 where the heat is dissipated. The problem is that the path becomes longer and the thermal resistance increases. Therefore, in order to improve heat dissipation, as shown in Figure 3,
It is necessary to fix the semiconductor element 4 to a surface surrounded by the external lead pins 2, and to sandwich the ceramic substrate from the fixed surface to release heat directly to the fins. However, in order to obtain this package structure, it is necessary to improve the sealing method of semiconductor devices. Conventional sealing methods for ceramic cases range from simple methods such as gluing a ceramic cap with epoxy resin or pouring silicone or epoxy resin, to applying glass powder to a ceramic cap and melting it. There are frit seals that bond metal plates together, solder seals that bond metal plates with solder, Au/Sn seals that bond metal plates with Au/Sn alloy, and the most commonly used seam weld.

樹脂を使つて封止する方法はいずれも耐湿性や
耐熱性に乏しく、高信頼度を要求される半導体装
置の封止法としては不適当である。フリツトシー
ル法は、比較的低融点のガラス粉末を用いて封止
するが、それでも400〜500℃に加熱しなければな
らず、この温度に特性変動をきたさない半導体素
子は限られ、特に最近の論理素子は高集積化とと
もに高温には弱く、一般的なシール法ではない。
ハンダシールは、比較的安価に容易にできるが、
融点が200℃前後と低く、また熱疲労し易いた
め、信頼性に欠ける欠点がある。Au/Snシール
は、300〜350℃の加熱で良好な封止が可能である
が、Auを使用している為、高価になり、また、
半導体素子をセラミツク基板にハンダで固着して
いる半導体装置には適用できない。封止の際に半
導体素子の温度が上がらず、信頼度も高く、低コ
ストでできるのがシームウエルド法である。これ
は第4図に示したように、半導体素子4の外周囲
に金属リング5をセラミツク基板1に密着して設
け、この上に金属キヤツプ6を重ね、一対のロー
ラー電極7,7′を押し当てながら電流を流す
と、リング5とキヤツプ6との接触面で発熱し、
両者を融かして接着するものである。発熱は局部
的であり半導体素子の温度は上昇しないので高温
に弱い素子や半導体素子をセラミツク基板にハン
ダで固着した半導体装置にも適用できる。また、
リングやキヤツプはFe/Ni合金などで作られ、
これの融けたものでシールされる為ハンダや
Au/Snの低融点ロウ材に比べて熱疲労が少な
く、信頼性も高い。
All methods of sealing using resin have poor moisture resistance and heat resistance, and are inappropriate as a method for sealing semiconductor devices that require high reliability. The frit seal method uses glass powder with a relatively low melting point for sealing, but it still has to be heated to 400 to 500 degrees Celsius, and there are only a limited number of semiconductor devices that do not change their characteristics at this temperature. This is not a common sealing method because the elements are highly integrated and vulnerable to high temperatures.
Solder seals are relatively cheap and easy to make, but
It has a low melting point of around 200°C and is susceptible to thermal fatigue, so it has the drawback of lacking reliability. Au/Sn seals can achieve good sealing by heating at 300 to 350℃, but since they use Au, they are expensive and
It cannot be applied to semiconductor devices in which semiconductor elements are fixed to ceramic substrates with solder. The seam welding method does not raise the temperature of the semiconductor element during sealing, is highly reliable, and can be done at low cost. As shown in FIG. 4, a metal ring 5 is provided around the outer periphery of the semiconductor element 4 in close contact with the ceramic substrate 1, a metal cap 6 is placed on top of the metal ring 5, and a pair of roller electrodes 7, 7' are pressed. When a current is applied while applying heat, heat is generated at the contact surface between the ring 5 and the cap 6,
Both are melted and bonded together. Since the heat generation is local and the temperature of the semiconductor element does not rise, it can also be applied to elements that are sensitive to high temperatures and semiconductor devices in which semiconductor elements are fixed to ceramic substrates with solder. Also,
The ring and cap are made of Fe/Ni alloy, etc.
Since it is sealed with the melted version of this, solder or
It has less thermal fatigue and higher reliability than low melting point brazing materials such as Au/Sn.

しかし、シームウエルドの欠点は、金属ローラ
ーを回転できる広いスペースが必要である点であ
り、第3図のように、外部リードピンに囲まれた
領域でシームウエルドすることは困難である。
However, the disadvantage of seam welding is that it requires a large space in which the metal roller can rotate, and it is difficult to seam weld in an area surrounded by external lead pins, as shown in FIG.

本発明は、上記のように半導体素子の封止を外
部リードピンに囲まれた状態で行なう場合に、改
良した方法で封止することにより、従来の問題を
解消し、高信頼性且つ低熱抵抗のパツケージを実
現するためになされたもので、セラミツク基板上
の半導体素子を囲む位置に金属リングを設け、半
導体素子を覆い且つ金属リングに重なる大きさの
金属キヤツプを重ね、しかる後に両者の重なる部
位にレーザービームを照射して封止することを特
徴とするものである。
The present invention solves the conventional problems by using an improved method when sealing a semiconductor element surrounded by external lead pins as described above, and achieves high reliability and low thermal resistance. This was done to realize a package. A metal ring is provided on a ceramic substrate at a position surrounding the semiconductor element, and a metal cap of a size that covers the semiconductor element and overlaps the metal ring is placed on top of the other. Then, the area where the two overlap is It is characterized by sealing by irradiation with a laser beam.

レーザービームは指向性が良く隔れた所から照
射しても広がりが殆んどないため、微細加工に適
し、特に機械的な加工では治工具類が屈かない領
域の加工でも離れた所から容易に行なえる特徴を
有する。本発明は、レーザービームのこの特徴
を、半導体装置の低熱抵抗構造を有するパツケー
ジ、即ち、第3図のように、半導体素子を外部リ
ードピンが囲んだ面に固着した構造を有する半導
体装置の製造に利用したものである。
Laser beams have good directivity and hardly spread even when irradiated from a distance, so they are suitable for micro-machining, and in mechanical machining in particular, they can be easily processed from a distance even in areas where jigs and tools do not bend. It has the feature that it can be used to The present invention utilizes this feature of a laser beam to manufacture a package having a low thermal resistance structure of a semiconductor device, that is, a semiconductor device having a structure in which a semiconductor element is fixed to a surface surrounded by external lead pins as shown in FIG. It was used.

以下に、本発明の実施例を図面を使つて詳細に
説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

半導体装置をTAB(Tape Automated
Bonding)法により組み立てる場合に本発明を適
用した一例を第5図に示す。TAB法は第5図a
のように、絶縁性フイルム8の中央部に貫通孔9
を開け、この貫通孔上にリード10を支持枠11
に支えられて突出させる。一方、半導体素子4の
電極は突起状に形成し、リード4の先端は、この
突起電極の位置に合致するように揃えてある。リ
ードと突起電極とは、両者を位置合わせして重ね
た後、ほぼ半導体素子と大きさの等しい治具によ
り熱と圧力を加えることにより、全リードを同時
に接続することができる。以上のようにして接続
した状態を示したものが第5図aである。リード
4の末端にはパツド12が設けられており、ここ
に電極端子を押し当てることにより半導体素子を
動作させ、所定の性能を発揮するか否かチエツク
することができる。チエツクの結果、正常な半導
体素子は、第5図bのように、支持枠11を残し
て絶縁フイルムから切り離され、例えば第5図c
に示したようなPIP(PIug―in―Packageプラグ
インパツケージ)13に組み込まれる。半導体素
子4は、PlPの中央に開けられた凹部14の底に
固着(=マウント)される。半導体素子には第5
図bのようにリード10が接続されているので、
半導体素子をピンセツト等で把んで凹部14の底
と擦り合わすことができず、通常のAu/Siマウ
ントや、Au/Snマウントはむずかしい。TAB法
によつて組み立てる場合、マウントは半導体素子
の裏面にAu等を蒸着し、PlPの凹部14の底には
AuやSn等をメタライズしておき、ハンダで行な
うのが最もよい。銀ペースト等でマウントするこ
とも勿論可能であるが、熱抵抗が高くなるので消
費電力の高い半導体素子の場合は不利である。以
上のようにして半導体素子をマウントした後、リ
ード10の末端を、PIPの外部端子15に接続す
る。両者は、例えば、リード10と外部端子15
をAuやSnでめつきしておき、熱と圧力を加えれ
ば、全リードを同時に接続することができる。外
部端子15はそれぞれ外部リードピンに導通され
ている。c図では、繁雑を避けるために、手前の
外部リードピンは省略して描いてある。半導体素
子4及びそれに接続されたリード10を収納した
凹部(=キヤビテイ)16の外周には金属リング
5が設けられ、ここに第3図のように金属キヤツ
プ6を重ね、レーザービームを照射して両金属を
溶かして溶接する。金属リングにコバールを、金
属キヤツプに厚さ2〜3μmのNiめつきした100
μm厚のコバール板を用いた場合、溶接に必要な
出力は、準連続Nd:YAGレーザーで100〜
200W、速度は15mm/秒である。このようにして
シールした半導体装置は、外部リードピンの植立
された面とは反対の面にAu等でメタライズして
おけば、塔載する半導体素子の消費電力や耐熱性
によつて、必要に応じて第3図のように放熱フイ
ン3を設けることが可能である。半導体素子の最
高ジヤンクシヨン温度Tj(max)が125℃、使用
外気温度Taが70℃、消費電力Pが5Wとすると、
要求される熱抵抗RΘは、 RΘ=Tj−Ta/P=125−70/5=11℃/W 以下となり、第2図のような従来の構造では到底
実現できず、第3図の形態が必要となり、従つて
シームウエルド法による気密シールはできなくな
る。しかもTAB法では、前記のようにマウント
はハンダを用いるのが一般的であるので、封入は
フリツト・シールやAn/Snシールのように温度
を上げることができない。本発明によれば、上記
の困難を解消し、低熱抵抗且つ高気密性を有する
信頼度の高い半導体装置を作ることができる。
Semiconductor equipment is TAB (Tape Automated)
FIG. 5 shows an example in which the present invention is applied when assembling by the bonding method. The TAB method is shown in Figure 5a.
A through hole 9 is formed in the center of the insulating film 8 as shown in FIG.
is opened, and the lead 10 is placed on the support frame 11 over this through hole.
It is supported by and made to protrude. On the other hand, the electrodes of the semiconductor element 4 are formed in the shape of a protrusion, and the tips of the leads 4 are aligned to match the positions of the protruding electrodes. All the leads can be connected at the same time by aligning and overlapping the leads and the protruding electrodes, and then applying heat and pressure using a jig that is approximately the same size as the semiconductor element. FIG. 5a shows the state in which the devices are connected as described above. A pad 12 is provided at the end of the lead 4, and by pressing an electrode terminal thereon, it is possible to operate the semiconductor element and check whether or not it exhibits a predetermined performance. As a result of the check, a normal semiconductor element is separated from the insulating film leaving the support frame 11 as shown in FIG. 5b, and for example, as shown in FIG.
It is incorporated into PIP (PIug-in-Package) 13 as shown in . The semiconductor element 4 is fixed (=mounted) at the bottom of a recess 14 formed in the center of PlP. The semiconductor element has a fifth
Since the lead 10 is connected as shown in Figure b,
It is difficult to grip the semiconductor element with tweezers or the like and rub it against the bottom of the recess 14, making it difficult to use a normal Au/Si mount or Au/Sn mount. When assembled by the TAB method, the mount is made by vapor-depositing Au etc. on the back surface of the semiconductor element, and the bottom of the recess 14 of the PlP is
It is best to metalize Au, Sn, etc. and then solder. It is of course possible to mount with silver paste or the like, but this increases the thermal resistance, which is disadvantageous in the case of semiconductor elements with high power consumption. After mounting the semiconductor element as described above, the ends of the leads 10 are connected to the external terminals 15 of the PIP. Both include, for example, the lead 10 and the external terminal 15.
By plating with Au or Sn and applying heat and pressure, all leads can be connected at the same time. The external terminals 15 are each electrically connected to an external lead pin. In Figure c, the external lead pins in the front are omitted to avoid clutter. A metal ring 5 is provided around the outer periphery of a recess (=cavity) 16 that accommodates the semiconductor element 4 and the leads 10 connected thereto, and a metal cap 6 is placed over this as shown in FIG. 3, and a laser beam is irradiated onto the metal ring 5. Both metals are melted and welded. 100 with Kovar on the metal ring and Ni plating with a thickness of 2 to 3 μm on the metal cap.
When using a μm-thick Kovar plate, the output required for welding is 100 ~
200W, speed 15mm/sec. If the semiconductor device sealed in this way is metallized with Au or the like on the side opposite to the side on which the external lead pins are planted, it will be possible to Accordingly, it is possible to provide heat dissipation fins 3 as shown in FIG. Assuming that the maximum junction temperature Tj (max) of the semiconductor element is 125℃, the outside air temperature Ta is 70℃, and the power consumption P is 5W.
The required thermal resistance RΘ is RΘ=Tj-Ta/P=125-70/5=11℃/W or less, which is impossible to achieve with the conventional structure shown in Figure 2, and the configuration shown in Figure 3 is Therefore, an airtight seal using the seam weld method cannot be achieved. Moreover, in the TAB method, as mentioned above, solder is generally used for the mount, so the temperature cannot be raised for encapsulation as with frit seals or An/Sn seals. According to the present invention, the above-mentioned difficulties can be solved and a highly reliable semiconductor device having low thermal resistance and high airtightness can be manufactured.

本発明の実施は上記の例に限られない。例え
ば、第6図のようなDIP(DuAl―in―line
Package)にも適用することができる。通常の
DIPは、外部リードピン2の向きとは反対側の面
(背面)に半導体素子が塔載され、主にシームウ
エルド法によつて封入されるが、第6図のよう
に、外部リードピンの向いた面(腹面)に半導体
素子を塔載し、熱放散性を上げる為に背面に放熱
フインや放熱スタツド(図示せず)を設ける場合
はシームウエルドは困難である。本例に於いても
レーザービームによる封止により低熱抵抗パツケ
ージが実現できる。
Implementation of the invention is not limited to the above example. For example, as shown in Figure 6, DIP (DuAl-in-line)
Package) can also be applied. normal
In a DIP, a semiconductor element is mounted on the side (back side) opposite to the direction of the external lead pins 2, and is encapsulated mainly by the seam welding method. Seam welding is difficult when semiconductor elements are mounted on the front surface (bottom surface) and heat dissipation fins or heat dissipation studs (not shown) are provided on the back surface to improve heat dissipation. In this example as well, a low thermal resistance package can be realized by sealing with a laser beam.

また第7図のように多層のセラミツク基板1の
腹面に半導体素子を複数個載置し、個々の半導体
素子を箱形のキヤツプ6で封入する場合でも本発
明の適用が可能である。本例の場合、セラミツク
基板の背面には放熱フイン3を取り付け、基板全
体を冷却できるようになつている。外部リードピ
ンは、基板1の側面に取り付けられ、プリント板
等に実装できるようになつている。
The present invention can also be applied to a case where a plurality of semiconductor elements are mounted on the bottom surface of a multilayer ceramic substrate 1 and each semiconductor element is enclosed in a box-shaped cap 6 as shown in FIG. In this example, a heat dissipation fin 3 is attached to the back surface of the ceramic substrate, so that the entire substrate can be cooled. The external lead pins are attached to the side surface of the board 1 so that they can be mounted on a printed board or the like.

以上、詳細に説明したように、本発明によれ
ば、消費電力の高い半導体素子や最大許容ジヤン
クシヨン温度の低い半導体素子等、低熱抵抗セラ
ミツク・ケースに組み立てられる必要のある半導
体素子を、外部リードピンに囲まれた面、即ち、
半導体装置としてプリント基板等に実装する際
に、プリント基板等と向かい合う面に塔載し封入
することができるので、この面とは反対の面には
放熱フインや放熱スタツド等のヒート・シンクを
取り付けることができ、高性能で且つ信頼性の高
い半導体装置を作ることができる。
As described in detail above, according to the present invention, semiconductor devices that need to be assembled in a low thermal resistance ceramic case, such as semiconductor devices with high power consumption or semiconductor devices with a low maximum allowable junction temperature, can be attached to external lead pins. The enclosed surface, i.e.
When mounted as a semiconductor device on a printed circuit board, etc., it can be mounted and sealed on the surface facing the printed circuit board, etc., so a heat sink such as a heat dissipation fin or a heat dissipation stud can be attached to the surface opposite to this surface. Therefore, a high performance and highly reliable semiconductor device can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の半導体装置の斜視
図および断面図、第3図は本発明に関わる半導体
装置の断面図、第4図はシームウエルド法を説明
する断面図、第5図は本発明をPIPに適用した場
合を説明する斜視図、第6図は本発明をDIPに適
用した場合の斜視図、第7図は本発明をハイブリ
ツド基板に適用した場合の斜視図である。 なお図中、1……セラミツク基板、2……外部
リードピン、3……放熱フイン、4……半導体素
子、5……金属リング、6……金属キヤツプ、
7,7′……ローラー電極、8……絶縁性フイル
ム、9……貫通孔、10……リード、11……支
持枠、12……パツド、13……PIP、14……
凹部、15……外部端子、16……キヤビテイで
ある。
1 and 2 are a perspective view and a sectional view of a conventional semiconductor device, FIG. 3 is a sectional view of a semiconductor device according to the present invention, FIG. 4 is a sectional view explaining the seam weld method, and FIG. 5 is a sectional view of a conventional semiconductor device. FIG. 6 is a perspective view illustrating a case where the present invention is applied to a PIP, FIG. 6 is a perspective view when the present invention is applied to a DIP, and FIG. 7 is a perspective view when the present invention is applied to a hybrid board. In the figure, 1... Ceramic substrate, 2... External lead pin, 3... Heat dissipation fin, 4... Semiconductor element, 5... Metal ring, 6... Metal cap,
7, 7'... Roller electrode, 8... Insulating film, 9... Through hole, 10... Lead, 11... Support frame, 12... Pad, 13... PIP, 14...
Recessed portion, 15... external terminal, 16... cavity.

Claims (1)

【特許請求の範囲】[Claims] 1 外部リードピンを配列したセラミツク基板の
前記外部リードピンが導出された側の面上に半導
体素子を搭載し、前記半導体素子の外周に前記セ
ラミツク基板に密着して金属リングを設け、前記
半導体素子を覆い且つ前記金属リングに重なる大
きさの金属キヤツプを重ね、前記金属リングと前
記金属キヤツプと重なる部分にレーザー・ビーム
を照射することにより両者を接合し、前記半導体
素子が搭載された面とは反対の面の前記セラミツ
ク基板上に放熱部材を取り付けることを特徴とす
る半導体装置の製造方法。
1. A semiconductor element is mounted on the side from which the external lead pins are led out of a ceramic substrate on which external lead pins are arranged, a metal ring is provided around the outer periphery of the semiconductor element in close contact with the ceramic substrate, and the semiconductor element is covered. In addition, a metal cap of a size that overlaps the metal ring is stacked, and a laser beam is irradiated to the overlapped portion of the metal ring and the metal cap to bond them together, and a surface opposite to the surface on which the semiconductor element is mounted is bonded. A method of manufacturing a semiconductor device, comprising: attaching a heat dissipating member on the ceramic substrate.
JP56176799A 1981-11-04 1981-11-04 Manufacture of semiconductor device Granted JPS5878443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56176799A JPS5878443A (en) 1981-11-04 1981-11-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56176799A JPS5878443A (en) 1981-11-04 1981-11-04 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5878443A JPS5878443A (en) 1983-05-12
JPS6239825B2 true JPS6239825B2 (en) 1987-08-25

Family

ID=16020039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56176799A Granted JPS5878443A (en) 1981-11-04 1981-11-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5878443A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6081843A (en) * 1983-10-12 1985-05-09 Fujitsu Ltd Microwave box construction

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51114874A (en) * 1975-04-02 1976-10-08 Hitachi Ltd Semiconductor device formation method
JPS577835A (en) * 1980-06-19 1982-01-16 Hitachi Cable Ltd Manufacture of base material for optical fiber

Also Published As

Publication number Publication date
JPS5878443A (en) 1983-05-12

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