JPS6239834B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to field effect transistors.

In general, compound semiconductors are often used in ultra-high frequency devices due to their physical characteristics. Recently, among them, GaAs, a - group binary compound semiconductor
The development of field-effect transistors (FETs) using FETs is remarkable, and they are moving from the prototype stage to mass production. However, there is a need to obtain ultra-high frequency devices with higher performance and higher reliability at a higher yield. One such request is
There is a possibility of increasing the breakdown voltage between the source and the drain (hereinafter referred to as drain breakdown voltage).

Conventionally, as a manufacturing method for field effect transistors,
The self-alignment method described below is used.

FIGS. 1a to 1e are cross-sectional views showing main manufacturing steps for explaining a conventional method for manufacturing a field effect transistor.

First, as shown in Figure 1a, semi-insulating GaAs
A buffer layer 12 is formed on a substrate 11 to form a wafer 10, and a mesa 14 is formed on the buffer layer 12. A GaAs active layer 13 is formed on the mesa 14. Next, an Al layer 15 is applied to the entire surface of the wafer 10.
Formed to a thickness of 4500 Å.

Next, as shown in FIG. 1B, the entire surface is covered with a photoresist 15, and the photoresist at the ohmic forming portion is removed by photolithography.

Next, as shown in FIG. 1c, using this photoresist 16 as a mask, phosphoric acid is applied to the Al layer 1.
6 and adjust it to the desired gate length.

Next, as shown in FIG. 1d, an AuGe/Pt layer 17, which is an ohmic contact metal, is formed by vapor deposition while leaving the photoresist 16 on.

Next, as shown in FIG. 1e, the AuGe/Pt layer 17 deposited on the photoresist is immersed in methyl ethyl ketone and removed together with the photoresist.
Next, an alloying process is performed in H ₂ to establish ohmic contact and use the AuGe/Pt layer 17 as source and drain electrodes. The heat treatment temperature is 420°C.

In the FET structure made by the above method, when a voltage is applied between the source and drain, the metal electrode 1
There was a drawback that the electric field was concentrated at the edge portion of No. 7 (portion a in FIG. 1e), and the drain breakdown voltage was lowered.

The present invention provides a field effect transistor which eliminates the above drawbacks and prevents a decrease in drain breakdown voltage.

The field effect transistor of the present invention includes a buffer layer having a first mesa portion formed on a semi-insulating semiconductor substrate, a trench dug around the first mesa portion, and a buffer layer formed on a semi-insulating semiconductor substrate. an active layer formed on the first mesa part and having a second mesa part; a gate electrode formed on the upper surface of the second mesa part and in contact with the second mesa part; The source electrode and the drain electrode are formed to extend from the side surface of the second mesa portion through the side surface of the first mesa portion of the buffer layer until reaching the groove, and are in ohmic contact with each other.

According to the present invention, since the ohmic electrode is formed by being dug into the semiconductor substrate, the above-mentioned problem of electric field concentration at the edge of the ohmic electrode is solved, and the drain breakdown voltage is high and the reliability is high. A field-effect transistor with good performance can be produced.

The present invention will be explained by examples.

FIGS. 2a to 2g are sectional views showing main manufacturing steps for explaining an embodiment of the present invention.

First, as shown in FIG. 2a, a GaAs buffer layer 22 is formed on a semi-insulating GaAs substrate 21 to form a wafer 20, and a mesa 24 is formed on the buffer layer 22. A GaAs active layer 23 is formed on the mesa 24.

Next, as shown in FIG. 2b, an Al layer 25 is formed on the entire surface of the wafer 20 to a thickness of about 4500 Å.

Next, as shown in FIG. 2c, the entire surface is coated with a photoresist 26, and the photoresist at the ohmic forming portion is removed by photolithography. At this time, a photoresist is formed so that the mesa 24 and the wafer in its vicinity are exposed in the next etching. Using this photoresist 26 as a mask, the Al layer 25 is etched by a plasma etching method so as to be exactly aligned with the mask.

Next, as shown in FIG. 2d, the GaAs buffer layer 22 and active layer 23 are etched using an etching solution of phosphoric acid, hydrogen peroxide, and pure water using the same pattern of photoresist and Al as masks. A mesa portion is formed in the active layer 23, and a groove 28 is also formed. The depth of the groove 28 is 500 Å.

Next, as shown in FIG. 2e, using the photoresist 26 as a mask, phosphoric acid is applied to the Al layer 2.
Side-etch 5' and adjust to the desired gate length.

Next, as shown in FIG. 2f, an AuGe/Pt layer 27, which is an ohmic contact metal, is formed by vapor deposition while leaving the photoresist on. The thickness is AuGe: 1350 Å, Pt: 360 Å.

Next, as shown in FIG. 2g, the AuGe/Pt layer 27 deposited on the photoresist is soaked in methyl ethyl ketone and removed together with the photoresist, and alloyed in H ₂ to form an ohmic contact. Take. The heat treatment temperature is 420°C.

According to the above method, the groove 28 is dug into the GaAs layer 22 to form an ohmic contact.
It is possible to avoid electric field concentration and increase drain breakdown voltage.

FIG. 3 is a drain voltage-drain current characteristic diagram of a field effect transistor manufactured according to an embodiment of the present invention.

The horizontal axis represents the drain voltage V _DS and the vertical axis represents the drain current I _DS . A solid line 31 represents the characteristics of a transistor manufactured according to the invention. For comparison, the characteristics of a conventional transistor are shown by a broken line 32. As is clear from the figure, the drain breakdown voltage of the transistor according to the present invention is higher by about 2V.

As described in detail above, according to the present invention, a field effect transistor having a high drain breakdown voltage and high reliability can be obtained, so that the present invention is highly effective.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views of main manufacturing steps for explaining a conventional method of manufacturing a field effect transistor, and FIGS. 2A to 2G are main manufacturing steps for explaining an embodiment of the present invention. FIG. 3 is a drain voltage-drain current characteristic diagram of a field effect transistor manufactured according to an embodiment of the present invention. 10, 20... Wafer, 11, 21... Semi-insulating GaAs substrate, 12, 22... GaAs buffer layer, 13, 23... GaAs operating layer, 14, 24...
...Mesa, 15,25...Al layer, 16,26...
Photoresist, 17, 27...AuGe/Pt layer,
28...Groove.

Claims (1)

[Claims] 1. A buffer layer having a first mesa portion formed on a semi-insulating semiconductor substrate, a trench formed by being dug around the first mesa portion, and a buffer layer formed on the first mesa portion. an active layer having a second mesa portion; a gate electrode formed on the upper surface of the second mesa portion and in contact with the second mesa portion; A field effect transistor comprising source and drain electrodes that are formed to extend through the side surface of the first mesa portion of the buffer layer until reaching the groove and are in ohmic contact with each other.