JP2558766B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a short gate length and a two-step recess structure for improving drain breakdown voltage.

2. Description of the Related Art Conventionally, in order to obtain a short gate length, an electron beam exposure apparatus has been used to realize a gate length of 0.3 μm or less. The two-stage recess is hardly used because its control is difficult, and has a structure in which the source / drain is lengthened.

Problems to be Solved by the Invention In the related art, since an EB exposure device or the like is used, throughput is poor and mass productivity is poor. Further, since the source-drain is not contracted, it is difficult to reduce the source resistance, and the characteristics cannot be improved. Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device having a short gate and excellent characteristics.

Means for Solving the Problems In order to suppress the conventional problems, the present invention provides a semiconductor substrate in which at least two layers of an upper layer to be an ohmic layer and a lower layer to be a channel layer are formed on one main surface of a semiconductor. Used 2
In manufacturing a field effect transistor having a stepped recess structure, a step of performing mesa etching for element isolation on one main surface of a substrate, a step of forming a first insulating film on the surface of the substrate, and a field effect transistor Forming ohmic electrodes in the source / drain regions of the same, depositing a second insulating film on the entire surface, removing the second insulating film on the inside of the ohmic electrode pattern, and field effect transistor. Etching the insulating film on the gate part to form a gate part window in contact with the first insulating film and the ohmic layer, and exposing the exposed substrate surface of the gate part window to the first ohmic layer. A first etching step of recess etching, leaving a portion left behind, and forming a third insulating film having the same property as the first insulating film or the second insulating film on the side wall of the gate window. A short gate length by a method of manufacturing a semiconductor device, including a second etching step of again etching the exposed substrate surface of the gate portion window having the sidewall film, and a step of forming a gate electrode in the gate window portion. The two-step recess structure is realized. The two-step recess structure improves the breakdown voltage of the source / drain, shortens the distance between the source / drain, and improves the device characteristics.

Action With the sidewall formation technology and the two-step recess structure, it is possible to realize a high withstand voltage and high transconductance field effect transistor having a gate length of 0.3 μm or less.

Example An example of the present invention will be described below.

FIG. 1 is a diagram showing one embodiment of the present invention using a GaAs FET as an example.

As shown in FIG.
An N layer 2 having a carrier concentration of 4 × 10 ¹⁷ cm ⁻³ is formed in the layer and an N + layer 2 having a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ is formed in the second layer. The substrate 3 is subjected to mesa etching 4 by a normal photoetching process. Next, the first insulating film SiN film 5 is deposited on the entire surface by 4000 Å and AuGe / Ni / Au (1500/50
The ohmic electrode 6 of 0 / 1000Å) is formed. Subsequently, a second insulating film 7SiN film having the same property as that of the first insulating film is deposited by 2000Å, and the second insulating film on the inner side of the ohmic electrode is removed by etching to form the ohmic window 8. A gate window opening 9 of 0.5 to 0.6 .mu.m is formed by an ordinary general-purpose photolithography apparatus, and the first recess etching is performed to form an etching portion 10. At this time, a part of the N + layer 1 which is an ohmic layer remains under the etched portion 10. Further, a film having a deposition rate of about 100 Å / min and a film quality similar to those of the first and second insulating films is formed on the side wall 11 of the gate window. After that, the second recess etching is performed to form the etching portion 12 and adjust it to a desired current value, and then the gate electrode 13 made of Ti / Pt / Au / Au plating is formed to complete the FET.

The first recess etching amount is preferably 3 times or more the second recess etching amount, and the first recess etching is performed until an ungate current value that is about twice the final target ungate current is obtained. Is desirable. When the gate electrode 13 is formed by a plating process, the gate resistance can be reduced. The deposition rate of the insulating film 5 or 6 used on the side wall is preferably about 100Å / min.

Figure 2 shows the gate width in the first and second recess etching.
It is a figure which shows an example of source-drain withstand voltage and transconductance in 70 micrometers.

From this figure, it can be seen that when the desired current value is 25 mA, the withstand voltage and transconductance are better when the current value in the first recess is 50 mA.

FIG. 3 is a diagram showing the relationship between the gate resistance of the gate portion and the minimum noise figure when the gate width is 140 βm.

From Fig. 3 FET formed by normal lift-off method
It can be seen that it is 1 dB lower than NF.

EFFECTS OF THE INVENTION By the method for manufacturing a semiconductor device of the present invention, the sidewall formation technology and the two-step recess structure are combined to achieve excellent mass productivity.
A high withstand voltage and high transconductance field effect transistor with a gate length of 3 μm or less can be realized, and more desirably, the gate resistance can be reduced by using an Au plating process, and a field effect transistor with excellent characteristics even at high frequencies can be realized. did it.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of an FET according to an embodiment of the present invention, FIG. 2 is a view showing the relationship between the transconductance and the breakdown voltage of the recess current of the present invention, and FIG. It is a figure which shows the relationship with a noise figure. 10 …… First recess etch, 12 …… Second recess etch, 11 …… Sidewall SiN film, 13 …… Gate electrode.

Claims (1)

(57) [Claims] 1. A method of manufacturing a field effect transistor having a two-step recess structure, which uses a semiconductor substrate in which at least two layers of an upper layer to be an ohmic layer and a lower layer to be a channel layer are formed on one main surface of a semiconductor. A step of performing mesa etching for element isolation on one main surface of the substrate, a step of forming a first insulating film on the surface of the substrate, and a step of forming ohmic electrodes in the source / drain regions of the field effect transistor, Depositing a second insulating film on the entire surface, removing the second insulating film on the inside of the ohmic electrode pattern, etching the insulating film on the gate portion of the field effect transistor, and
A step of forming a gate portion window in contact with the insulating film and the ohmic layer, a first etching step of recess etching the exposed substrate surface of the gate portion window, leaving a part of the first ohmic layer, Forming a third insulating film having the same property as the first insulating film or the second insulating film on the sidewall of the gate window, and etching the exposed substrate surface of the gate window having the sidewall film again A method of manufacturing a semiconductor device, comprising: a second etching step; and a step of forming a gate electrode in the gate window portion.