JPS6239951B2 - - Google Patents
Info
- Publication number
- JPS6239951B2 JPS6239951B2 JP12629481A JP12629481A JPS6239951B2 JP S6239951 B2 JPS6239951 B2 JP S6239951B2 JP 12629481 A JP12629481 A JP 12629481A JP 12629481 A JP12629481 A JP 12629481A JP S6239951 B2 JPS6239951 B2 JP S6239951B2
- Authority
- JP
- Japan
- Prior art keywords
- motor
- pulses
- circuit
- checking
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000013078 crystal Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04D—APPARATUS OR TOOLS SPECIALLY DESIGNED FOR MAKING OR MAINTAINING CLOCKS OR WATCHES
- G04D7/00—Measuring, counting, calibrating, testing or regulating apparatus
- G04D7/002—Electrical measuring and testing apparatus
- G04D7/003—Electrical measuring and testing apparatus for electric or electronic clocks
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electromechanical Clocks (AREA)
Description
【発明の詳細な説明】 本発明は時計用集積回路に関するものである。[Detailed description of the invention] The present invention relates to an integrated circuit for a watch.
従来、時計用集積回路のチエツクを行なう場合
にはモータ駆動パルスが所定の周期で発生するか
否かを測定している。一般には２秒周期の２系統
のパルスを１秒ずつ位相をずらして発生させ、１
秒周期でモータを駆動している。そのため周期測
定に時間がかかり、大量の集積回路をチエツクす
る場合に不都合であつた。 Conventionally, when checking an integrated circuit for a watch, it is determined whether or not motor drive pulses are generated at a predetermined period. Generally, two systems of pulses with a period of 2 seconds are generated with a phase shift of 1 second each, and 1
The motor is driven every second. Therefore, it takes time to measure the period, which is inconvenient when checking a large number of integrated circuits.
そこで本発明は短時間でチエツクが行なえる時
計用集積回路を提供するものである。 Therefore, the present invention provides a timepiece integrated circuit that can be checked in a short time.
以下本発明の一実施例を図面に基づいて説明す
る。Ｑは水晶振動子、C1，C2はコンデンサで、
インバータV1とによつて水晶発振器を構成して
いる。Ａは集積回路で、分周器Ｄ、駆動パルスの
発生回路DR、チエツク用パルスの発生回路PG、
ゲート回路G1，G2およびインバータV1〜V3から
なる。Ｌはモータの駆動コイルで、出力端子P1，
P2間に接続してある。 An embodiment of the present invention will be described below based on the drawings. Q is a crystal oscillator, C 1 and C 2 are capacitors,
A crystal oscillator is constituted by the inverter V1 . A is an integrated circuit that includes a frequency divider D, a drive pulse generation circuit DR, a check pulse generation circuit PG,
It consists of gate circuits G1 , G2 and inverters V1 to V3 . L is the drive coil of the motor, and the output terminals P 1 ,
It is connected between P2 .
以上の構成において、発生回路DRの端子r1，
r2からはそれぞれ第２図Ａ，Ｂのごとく２秒周期
の駆動パルスが発生する。発生回路PGからは第
２図Ｃのごとく上記駆動パルスより短い周期で狭
幅のチエツク用パルスが生じる。これらのパルス
によつて出力端子P1，P2にはそれぞれ第２図Ｄ，
Ｅのごとくパルスが生じる。各端子P1，P2から生
じるチエツク用パルスは同相であるためモータに
は影響が及ぼされず、駆動パルスによつてのみモ
ータが駆動される。 In the above configuration, the terminals r 1 ,
From r2 , drive pulses with a period of 2 seconds are generated, as shown in FIGS. 2A and 2B. As shown in FIG. 2C, the generating circuit PG generates a check pulse having a shorter period and a narrower width than the driving pulse. These pulses cause the output terminals P 1 and P 2 to output signals D and D in Figure 2, respectively.
A pulse is generated as shown in E. Since the check pulses generated from each terminal P 1 and P 2 are in phase, the motor is not affected, and the motor is driven only by the drive pulses.
そして分周器が正常に機能しているかどうかの
確認および出力周期の確認を行なう場合には、端
子P1，P2からのチエツクパルスを用いればよく、
チエツクに要する時間を短縮することができる。 When checking whether the frequency divider is functioning properly and checking the output cycle, check pulses from terminals P 1 and P 2 can be used.
The time required for checking can be shortened.
したがつて、特に大量の集積回路をチエツクす
る場合などに大きな効果を奏する。 Therefore, it is particularly effective when checking a large number of integrated circuits.
第１図は本発明の一実施例を示した論理回路
図、第２図は動作説明のためのタイムチヤートで
ある。
Ａ……集積回路、DR……駆動パルスの発生回
路、PG……チエツク用パルスの発生回路、G1，
G2……ゲート回路、Ｌ……コイル。
FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation. A...Integrated circuit, DR...Drive pulse generation circuit, PG...Check pulse generation circuit, G1 ,
G 2 ...Gate circuit, L...Coil.
Claims (1)
タ駆動パルスとこのモータ駆動パルスより短い周
期で２系統の互いに同相のチエツク用パルスを上
記各出力端子から生じることを特徴とする時計用
集積回路。1. A timepiece integrated device having two output terminals for driving a motor, and generating two systems of check pulses having the same phase with each other at a cycle shorter than the motor driving pulse from each of the output terminals. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12629481A JPS5827083A (en) | 1981-08-11 | 1981-08-11 | Integrated circuit for time piece |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12629481A JPS5827083A (en) | 1981-08-11 | 1981-08-11 | Integrated circuit for time piece |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5827083A JPS5827083A (en) | 1983-02-17 |
| JPS6239951B2 true JPS6239951B2 (en) | 1987-08-26 |
Family
ID=14931639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12629481A Granted JPS5827083A (en) | 1981-08-11 | 1981-08-11 | Integrated circuit for time piece |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827083A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011013120A (en) * | 2009-07-02 | 2011-01-20 | Seiko Instruments Inc | Integrated circuit for electronic clock, and electronic clock |
-
1981
- 1981-08-11 JP JP12629481A patent/JPS5827083A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5827083A (en) | 1983-02-17 |
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