JPH0158697B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse signal generation circuit, and particularly to a pulse signal generation circuit that is built into an LSI or the like and is capable of test operation.

Generally, an LSI includes a reference oscillator, a first frequency division stage,
It includes a second frequency division stage, a timing generation circuit, etc., the frequency of the clock signal generated by the reference oscillator is divided by the first frequency division stage, and the frequency of the divided signal is further divided by the second frequency division stage, Some devices receive the pulse signal obtained at the second frequency division stage and generate subsequent appropriate timing pulses in a timing generation circuit based on this pulse signal. Further, the reference oscillator is externally attached. In these LSIs, the first frequency division stage is not essential to obtain the timing signal, but the reference oscillator uses a relatively high frequency one (for example, several MHz) that is commercially available at low cost. It is often used to lower the reference oscillation frequency to a manageable frequency. When performing various tests on this type of LSI, there is a problem in that the test takes a long time if a signal at the reference oscillation frequency is input from the first frequency dividing stage in all tests.

Therefore, in conventional LSIs, in addition to the input terminal of the first frequency division stage, a test terminal that can input a direct clock signal from the outside to the second frequency division stage is provided to confirm the normal operation of the first frequency division stage. After that, a clock signal was applied to the test terminal and directly inputted to the second frequency division stage, thereby shortening the test time.

However, test terminals are unnecessary during the original operation of the circuit, and providing this terminal specifically increases the size of the package and increases costs. The disadvantage was that it was restricted by

The purpose of this invention is to eliminate the above-mentioned conventional drawbacks,
Test terminals can be reduced or omitted, making it more compact.
It is an object of the present invention to provide a pulse signal generation circuit that is low in cost and can accommodate more circuits in an LSI.

In order to achieve the above object, the pulse signal generating circuit of the present invention switches the input terminal 1 and the output terminal of the first frequency dividing circuit 2, and provides a pulse signal generating circuit connected to the input terminal of the second frequency dividing circuit 4. 1 switching circuit 3, and the first switching circuit 3;
The output terminal of the frequency dividing circuit 2 and the output terminal of the second frequency dividing circuit 4 are switched and connected to the monitor terminal 6.
a switching circuit 5, a delay circuit 8 which receives a clock signal input to the input terminal 1 and whose output rises a predetermined time after the rise of the clock signal, and receives the output of the delay circuit 8 as an input;
It is characterized by a flip-flop 9 which is triggered by the falling edge of the clock signal and uses its output as a switching signal for the first and second switching circuits 3 and 5, and during normal operation, the input terminal 1 is The flip-flop 9 of the delay circuit 8 identifies the frequency of the clock signal input to the delay circuit 8 and operates the first and second switching circuits 3 and 5. are connected in series, and the output end of the first frequency dividing circuit 2 is connected to the monitor terminal 6. On the other hand, during test operation, the frequency of the test clock signal input to the input terminal 1 is identified by the flip-flop 9 of the delay circuit 8, and the first and second switching circuits 3 and 5 are operated, so that the input terminal 1 is The second frequency dividing circuit 4 is connected to the input terminal thereof, and the monitor terminal 6 is connected to the output terminal of the second frequency dividing circuit 4.
Therefore, the second frequency dividing circuit 4 is stepped at a higher speed than during its original operation.

Hereinafter, the present invention will be explained in more detail with reference to Examples.

FIG. 1 is a block diagram of a pulse signal generation circuit showing one embodiment of the present invention. All of the circuits shown here are housed within an LSI chip.

In FIG. 1, 1 is an input terminal, and a reference oscillator (not shown) is connected to this input terminal 1. The reference oscillator itself may be built into the LSI chip or externally attached, but even if it is an external one, input terminal 1 is not inherently necessary as a resonator connection terminal. be.

The input terminal 1 is connected to the input terminal of the first frequency division stage (frequency division circuit), the output terminal of the first frequency division stage 2 is connected to the terminal A of the switching circuit 3, and the input terminal 1 is connected to the input terminal of the first frequency division stage (frequency division circuit). It is also connected to terminal B of No.3. Further, the common terminal C of the switching circuit 3 is connected to the input terminal of the second frequency dividing stage 4, and the output terminal of the second frequency dividing stage 4 is connected to the terminal B of the switching circuit 5. The output of the first frequency division stage 2 is also connected to the terminal A of the switching circuit 5. A common terminal C of the switching circuit 5 is connected to a monitor terminal 6.

The pulse signal output from the second frequency division stage 4 is applied to the timing generation circuit 7, and the timing generation circuit 7 generates various timing signals based on this pulse signal.

Reference numeral 8 denotes a delay circuit, which receives a clock signal input to the input terminal 1, and after the rise of the clock signal, the output rises after a TD time on condition that the clock signal is high. The output of the delay circuit 8 is connected to the signal input terminal D of the flip-flop 9, and the input terminal 1 is connected to the trigger input terminal of the flip-flop 9. The flip-flop 9 is configured to be triggered by the falling edge of the clock signal applied to the input terminal 1. Also, the output terminal Q of this flip-flop 9
The switching circuits 3 and 5 are switched in conjunction with each other by the signal derived from the signal. That is, when the output terminal Q of the flip-flop 9 is high, the switching circuits 3 and 5
The common terminal C of is connected to the terminal A, and the output terminal Q
is low, the common terminal C of the switching circuits 3 and 5 is connected to the terminal B.

FIG. 2 shows an example of a specific circuit of the switching circuit 3(5). In the figure, A, B, C, and Q correspond to the terminals A, B, and C of the switching circuit 3 and the output terminal Q of the flip-flop 9, respectively, and a high signal is derived to the output terminal Q of the flip-flop 9. Then, the signal at the terminal A, that is, the output of the first frequency dividing stage 2, is inputted to the terminal C, that is, the second frequency dividing stage 4, via the NAND gate NG1 and the NAND gate NG3. On the other hand, when a low signal is derived from the output terminal Q of the flip-flop 9, this low signal is output to the inverter.
Since the high signal is inverted at IN and applied to one end of the input of NAND gate NG2, the signal at terminal B, that is, the signal applied to input terminal 1, passes through NAND gate NG2 and NAND gate NG3 to terminal C, that is, the second frequency division stage. 4 is now entered.

Next, the operation of the above embodiment circuit will be explained.

When testing the original operation of the circuit and the operation of the first frequency dividing stage 2, a clock signal with a relatively low frequency is input to the input terminal 1, as shown in FIG. In this case, the delay time of delay circuit 8 is
Since the pulse width W of the clock signal CP is large compared to TD, even if the TD time has elapsed since the clock signal CP rises, the clock signal CP is still at a high level, and therefore the output of the delay circuit 8 is teeth,
It rises to high level with a delay of T time from the rise of the clock signal CP (see FFD in Figure 3). Therefore, when the flip-flop 9 is triggered by the fall of the clock signal CP, the output terminal Q of the flip-flop 9 also becomes high due to the high output of the delay circuit 8 (see FFQ in FIG. 3). After that, the clock signal CP
Since the same operation continues each time ? is input to the input terminal 1, the output terminal Q of the flip-flop 9 remains high, and therefore the switching circuits 3 and 5 are connected to the terminal A side. It remains as it is. Therefore, the clock signal CP input to input terminal 1
is frequency-divided by the first frequency division stage 2 and the second frequency division stage 4. In this case, the operation of the first frequency dividing stage 2 may be confirmed by the operation after the timing generation circuit 7, and since the output of the first frequency dividing stage 2 is directly obtained from the monitor terminal 6, this It may be confirmed by

When testing each circuit after the second frequency dividing stage 4, a clock signal CP having a relatively high frequency is input to the input terminal as shown in FIG. Since the pulse width W of this clock signal CP is smaller than the delay time TD of the delay circuit 8, even if the flip-flop 9 is triggered from the time when the clock signal CP rises to the next fall, the clock signal
Since the TD time has not yet elapsed since the rise of CP, the output of the delay circuit 8 remains low (see FFD in Figure 4), and therefore the output terminal Q of the flip-flop 9 also does not go high (Figure 4). FFQ
). Thereafter, as long as the same clock signal CP is input to the input terminal 1, the same operation continues, so the output terminal Q of the flip-flop 9 remains low, and therefore the switching circuits 3 and 5
is connected to the terminal B side. Therefore, input terminal 1
The clock signal CP inputted to the clock signal CP is applied to the second frequency division stage 4, skipping the first frequency division stage. Then, the circuits after the second frequency division stage 4 are tested. In this case, since the clock signal CP is directly applied to the second frequency division stage 4, various tests of the original circuits after the second frequency division stage 4 can be performed in a shortened manner.

According to the pulse signal generating circuit of the present invention, the frequency of the clock signal applied to the input terminal is identified within the circuit, and the frequency is divided including the first frequency dividing stage, or the frequency is divided including the first frequency dividing stage. This allows the user to select whether to skip the frequency and perform the test by dividing the frequency, which allows the test to be performed in a shortened time, and because there is no need to provide any special terminals for the test, the LSI can be made smaller and lower in cost. In addition, if the package size is the same as the conventional one, more circuits can be accommodated. Further, by changing the frequency of the clock signal input to the input terminal, the second switching circuit is operated, and both the output of the first frequency dividing circuit and the output of the second frequency dividing circuit are monitored at the monitor terminal. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a pulse signal generation circuit showing one embodiment of the present invention, FIG. 2 is a diagram showing a specific logic circuit example of a switching circuit of the pulse signal generation circuit, and FIG. 3 is a block diagram of a pulse signal generation circuit according to an embodiment of the invention. A time chart for explaining the operation of the generator circuit during normal operation and when testing the first frequency division stage. Figure 4 shows the test of the circuits after the second frequency division stage of the same pulse signal generation circuit. This is a time chart for explaining the operation when performing the following. 1: input terminal, 2: first frequency division stage, 3: switching circuit, 4: second frequency division stage, 7: timing generation circuit, 8: delay circuit, 9: flip-flop.

Claims (1)

[Claims] 1. An input terminal 1, a first frequency divider circuit 2 whose input side is connected to the input terminal 1, and a second frequency divider circuit 2 which receives the output of the first frequency divider circuit 2 and divides its frequency. a frequency dividing circuit 4, the pulse signal generating circuit obtains a required timing pulse based on a pulse signal output from the second frequency dividing circuit 4, the input terminal 1 and the first frequency dividing circuit; a first switching circuit 3 which switches the output terminal of the second frequency dividing circuit 2 and connects it to the input terminal of the second frequency dividing circuit 4; and an output terminal of the first frequency dividing circuit 2 and the second frequency dividing circuit 4; a second switching circuit 5 which switches the output end of the circuit and connects it to the monitor terminal 6; and a delay circuit which receives the clock signal input to the input terminal 1 and whose output rises a predetermined time after the rise of the clock signal. 8, and a flip-flop 9 which receives the output of the delay circuit 8 at its input, is triggered by the fall of the clock signal, and uses its output as a switching signal for the first and second switching circuits 3 and 5. A pulse signal generation circuit characterized by: