JPS6240799B2 - - Google Patents

Description

Detailed Description of the Invention Technical Field of the Invention The present invention is directed to reducing the circuit area of a selector in a semiconductor memory device having a self-correcting circuit that automatically corrects bit errors occurring in a memory using an error correction code. This invention relates to a semiconductor memory device that can be scaled up.

Background of the Technology As a semiconductor memory device with a built-in circuit that automatically corrects bit errors that occur in semiconductor memory, horizontal and vertical parity check codes are applied to multiple memory cells connected to a single word line. We have previously proposed a semiconductor memory device that self-corrects bit errors by
issue). FIGS. 1A and 1B are diagrams explaining the principle of this, and the horizontal parity bit for 16 data bits arranged on a 4×4 matrix is shown as a, and the vertical parity bit is shown as b. If the data bits and parity bits a and b are moved as shown by the broken lines in Figure 1a, the two-dimensional matrix will be
It can be converted into a one-dimensional matrix as shown in Figure b. Therefore, among the 24 bits in the one-dimensional matrix in Figure 1b, the error in any one bit among the upper 16 bits is compared with the parity bits in the lower 8 bits for each group shown by the solid line in Figure 1b. By doing this, the position of the error bit can be detected. Therefore, any 1 of the upper 16 bits
Even if a fixed defect or a non-fixed defect occurs in a bit, the position of the defective bit can be detected, and accordingly, error correction can be easily performed.

FIG. 2 shows the configuration of a self-correcting memory using the principles shown in FIGS. 1a and 1b. Fig. 2 shows a self-correcting memory when the data bit width is 1 bit, in which 1 is a memory cell section consisting of memory cells 4, 2 is a vertical parity cell section consisting of horizontal parity cells 5, and 3 is a memory cell section consisting of horizontal parity cells 5.
7-1 to 7-2m, 9, 13 are selectors for selecting one bit from K pieces of bit line information; 8 is a (K x 2 m) piece of bit line information. A selector for selecting K bits from line information, 12 a selector for selecting 1 bit from 2m bit line information, 20 and 21 horizontal and vertical parity check circuits, 24 a word line, and 31 a 2-bit selector. The input AND gate 32 is a two-input EOR gate. K indicates the number of vertical bit line groups, and 2m indicates the number of horizontal bit line groups. In this configuration,
It is formed of (K×2m) data bit lines and (K+2m) parity bit lines. (K+
Since the 2m) data bit lines form horizontal parity bit information in units of K bits, they are grouped in units of K bits to form 2m groups of data bit lines. Furthermore, (K×2m) data bit lines form vertical parity bit information in units of 2m bits, so they are grouped in units of 2m bits to form K groups of data bit lines. Then, corresponding to 2m groups of horizontal data bit lines for forming horizontal parity bit information, 2m horizontal parity bit lines and K groups of vertical data bit lines for forming vertical parity bit information. K vertical parity bit lines are provided to receive test information for each data bit line group.

In this configuration, the data bit information group to which the desired data bit information for performing horizontal and vertical parity checks belongs is stored in the selectors 8, 7-
1 to 7-2m and supplied to horizontal and vertical parity check circuits 20 and 21.
Further, horizontal and vertical parity bit information regarding desired data bit information is also sent to the selectors 12 and 13.
and are supplied to horizontal and vertical parity check circuits 20 and 21, respectively. Then, if an error is detected in the desired data bit information,
The output of the gate 31 becomes "1", and the data bit information is inverted, ie, corrected, and outputted at the gate 32.

The layout around the selector and multiplexer in this configuration is shown in FIG. 3a. 1 is a memory cell section,
2 is a horizontal parity cell section, 3 is a vertical parity cell section, 8 is a selector for selecting horizontal data bit line information, 10 is a selector for selecting a group of vertical data bit line information, 11 is a multiplexer, 12, 13
1 is a selector for selecting horizontal or vertical parity bit line information, 20 and 21 are horizontal and vertical parity check circuits, 30 is a 2-input AND gate to which bit line information and selection signals are input, 31 is a 2-input AND gate, and 32 is a 2-input AND gate. It is a 2-input EOR gate. FIG. 3b shows a specific circuit example of the two-input AND gate 30. b is a bit line, and s is a selection signal line. In this layout, there are (K×2 m) data bit lines, selectors for selecting horizontal and vertical data bit line information, and a total of (K+2 m) output lines.

Conventional technology and problems In the layout using the conventional circuit configuration,
The circuit area of selectors 8 and 10 is (K×2m)P _B・
(K+2m) P _S ; (P _B : Bit line pitch, P _S :
selector output line pitch). Since this selector occupies a large circuit area within the memory, there is a problem in reducing the circuit area.

OBJECTS OF THE INVENTION In order to solve the conventional drawbacks, the present invention divides a plurality of memory cells storing information forming the same error correction code into a plurality of groups, and provides an output line for obtaining desired information corresponding to each group. Alternatively, by sharing the output line and the selector, the circuit area of the selector is reduced, and will be explained in detail below with reference to the drawings.

Embodiment of the Invention FIG. 4 shows an embodiment of the invention. 1a is a first block of the memory cell section, 1b is a second block of the memory cell section, 2 is a horizontal parity cell section, 3 is a vertical parity cell section, 8 is a selector for selecting a horizontal data bit line information group, and 10 is a vertical data bit. 11 is a multiplexer; 12 and 13 are selectors for selecting horizontal and vertical parity bit line information; 20 and 21 are horizontal and vertical parity check circuits; 30 is for inputting bit line information and selection signals; AND gate, 3
1 is a 2-input AND gate, and 32 is a 2-input EOR gate. In this embodiment, the memory cell section is divided into two parts. The configuration is such that (K×m) data bit lines are output for each divided block. The vertical data bit line information group is [K
K groups are formed in units of 2m bits from among the data bit line information of ×2m), but in this embodiment, each divided block contains K m bits of one group of the vertical data bit line information group. Allocate the amount to each group. With this configuration, the number of output lines of the selector 10 for selecting vertical data bit line information from each block is only m. That is, as is clear from a comparison of the selectors 10 and 8 in FIG. 3, in the selector 8 that selects the horizontal data bit line information group, the two-input AND gate for selecting the circle mark, that is, the intersection point, is as follows: On the other hand, in the selector 10 for selecting the vertical data bit line information group, the circle mark, that is, the AND gate mentioned above, is almost evenly distributed over the entire range shown by 8. K pieces are arranged in groups. Therefore, of the entire range of the vertical data bit line information group selection selector 10, the upper right and lower left areas require exclusive area on the layout, although they are useless parts.
As described above, the present invention utilizes the selector 1 for vertical data bit line information group selection in order to effectively utilize this feature.
0 into two blocks (as a premise for realizing this, the memory cell part of the one-dimensional matrix must also be divided into two blocks), and the arrangement of the AND gates included in the lower block is changed to the upper block. The layout has been devised so that the gates are arranged below the AND gate array matrix in the block, that is, on the extension in the column direction. In this way, the lower right part of the vertical data bit line information group selection selector 10 in FIG. 3 is located below the left upper part, so that the vertical data bit line information group selection selector 10 in FIG. As is clear from the comparison, it is possible to omit the upper right and lower left parts of the vertical data bit line information group selection selector 10 in FIG. The width that previously required the width of 100 m is reduced to m, while the height remains unchanged at K×m×2. Therefore, selectors 8 and 10 in this embodiment
The total circuit area is (K×2m) P _B × (K+m)
P _S , and it becomes possible to reduce the circuit area to (K+m)/(K+2m) times the circuit area of selectors 8 and 10 having the configuration shown in FIG.

As explained above, the present invention provides a selector for selecting vertical data bit line information in a semiconductor memory device having a self-correction circuit for self-correcting bit errors occurring in the memory using an error correction code. The pattern layout is divided into two blocks, and the pattern layout is arranged so that the AND gates included in the lower block are arranged below the AND gate array matrix in the upper block, that is, on the extension in the column direction. Because it is a natural thing,
It is possible to realize a reduction in the area occupied by the selector, which has a great effect on realizing a large-scale circuit.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the sailor vertical parity check code, Figure 2 is a configuration diagram of a self-correcting memory using the principle of Figure 1, and Figures 3a and b are specific layouts of the configuration of Figure 2. , FIG. 4 shows an embodiment of the present invention. 1...Memory cell part, 1a...First part of the memory cell part
Block, 1b...Second block of memory cell section,
2...Horizontal parity cell section, 3...Vertical parity cell section, 4...Memory cell, 5...Horizontal parity cell, 6
...Vertical parity cell, 7-1 to 7-2m, 8,
9, 10, 10a, 10b, 12, 13...Selector, 11...Multiplexer, 20, 21...Horizontal and vertical parity check circuit, 24...Word line, 30...2-input AND with input of bit line information and selection signal Gate, 31...2 input AND gate,
32...2 input EOR gate.

Claims (1)

[Claims] 1. A plurality of memory cells that store information, a plurality of test cells that store information for detecting bit errors occurring within the memory cells, and a plurality of test cells that store information from among the information of the plurality of memory cells. A selector selects 2m bits and K bits of memory cell information necessary for bit error correction from among (K x 2m) pieces of memory cell information forming the same error correction code, and a selector selects 1 bit from K pieces of check cell information. In a semiconductor memory device that has a selector that selects bit errors and a self-correction circuit that automatically corrects bit errors based on each selected memory cell information and check cell information, one word line has (K×2m) bit errors. The memory cell part of a one-dimensional matrix consisting of connected information storage memory cells is divided into two parts: m on the top and m on the bottom.
Divide into blocks, (K x 2m) memory cell information is sequentially grouped into K pieces to form a vertical data bit line group, and the vertical data bit line group is 2m in total.
In order to select a specific vertical data bit line group from among the vertical data bit line groups provided, a matrix of 2m rows and K columns is constructed, [(1,1), (1,2)..., (1,K)],
[(2, K+1), (2, K+2), ..., (2,
2K)],…, [(2m, K×(2m−1)+1), (2m,
K×(2m−1)+2)…,(2m,K×2m)]
Each group is sequentially shifted in the row direction, and as a whole,
A selector for selecting a vertical data bit line information group consisting of a two-input AND gate for selection arranged only at matrix intersections near diagonal lines is divided into two blocks corresponding to the memory cell portion, and the vertical data The arrangement of the AND gate in the lower block of the bit line information group selection selector is as follows:
A semiconductor memory device characterized in that the area occupied by the selector for selecting the vertical data bit line information group is reduced by disposing the selector in the column direction below the AND gate array matrix in the upper block.