JPS6242310B2 - - Google Patents
Info
- Publication number
- JPS6242310B2 JPS6242310B2 JP17563882A JP17563882A JPS6242310B2 JP S6242310 B2 JPS6242310 B2 JP S6242310B2 JP 17563882 A JP17563882 A JP 17563882A JP 17563882 A JP17563882 A JP 17563882A JP S6242310 B2 JPS6242310 B2 JP S6242310B2
- Authority
- JP
- Japan
- Prior art keywords
- request signal
- request
- signal
- processing
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はインタフエース、例えば計算機システ
ムにおける入出力装置（以下Ｉ／Ｏと称す）と中
央処理装置（以下CPUと称す）との間のインタ
フエースにおいて、要求信号を出した装置がその
要求信号を取り消した場合に、要求を処理する装
置がその取消されたことを速かに知ることができ
るようにしたものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an interface, for example, an interface between an input/output device (hereinafter referred to as I/O) and a central processing unit (hereinafter referred to as CPU) in a computer system. In the present invention, when the device that issued the request signal cancels the request signal, the device processing the request can quickly know that the request signal has been cancelled.
以下Ｉ／Ｏからの割込み要求をCPUで受付け
る場合を例にして説明する。
The following will explain the case where the CPU accepts an interrupt request from I/O as an example.
Ｉ／Ｏからの割込み要求に対し、CPUは他割
込み要求との優先度のチエツク等を行なつて受付
け可能な場合には受付け信号を応答する。しか
し、その間にＩ／Ｏが要求を取消した場合、
CPUは直ちにはその取消されたことが判らず、
Ｉ／Ｏからの次の応答が来ないことを時間監視等
で検知する等して何らかの異常が有つたことを知
り、CPUからＩ／Ｏに状態センスを行なう等の
必要があつた。 In response to an interrupt request from an I/O, the CPU checks the priority with respect to other interrupt requests, and responds with an acceptance signal if it can be accepted. However, if the I/O cancels the request in the meantime,
The CPU does not immediately know that it has been canceled,
It became known that some kind of abnormality had occurred by detecting, for example, by time monitoring that the next response did not come from the I/O, and it became necessary to perform a status sensing from the CPU to the I/O.
本発明の目的は、要求信号の取消されたことを
速かに、かつ簡単な回路で知ることを可能にする
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to enable quick and simple circuitry to determine that a request signal has been canceled.
本発明は要求信号をコピーするフリツプ・フロ
ツプ（以下単にFFと称する）と、要求信号の立
上りでセツトされるFFとを設け、両FFの論理状
態を見ることによつて要求信号が取消されたこと
を知るようにしたことを特徴とする。
The present invention includes a flip-flop (hereinafter simply referred to as FF) that copies the request signal and an FF that is set at the rising edge of the request signal, and the request signal is canceled by checking the logic state of both FFs. It is characterized by being made aware of things.
第１図は本発明の一実施例回路図、第２図はそ
のタイムチヤートである。図中１はＩ／Ｏ装置
（処理要求装置）、２は制御装置（例えばＩ／Ｏ制
御装置又はチヤネル装置）、３はCPU（要求処理
装置）、FF１〜３はフリツプ・フロツプ、RVは
レシーバ、DVはドライバ、IVはインバータであ
る。２１は立上がり検出回路、２２はリセツト制
御回路である。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart thereof. In the figure, 1 is an I/O device (processing request device), 2 is a control device (for example, an I/O control device or channel device), 3 is a CPU (request processing device), FFs 1 to 3 are flip-flops, and RV is a receiver. , DV is the driver, and IV is the inverter. 21 is a rising detection circuit, and 22 is a reset control circuit.
通常の動作は、先ずＩ／O1から割込み要求信
号iRQが出ると、装置２で第１のFF１にバツフ
アされ（iRQB）さらにコピー用FF２にラツチさ
れてiRQCとなつてCPU３に伝達される。一方、
iRQBの立上がりが回路２１で検出され、FF３が
セツトされてiRQUとしてCPU３に伝達される。
（第２図の区間）
CPU３では割込みを受付けられるか否かを調
べ、もし受付け可能ならば許可信号iRQANSを発
する。iRQANSは装置２を介してＩ／O1にiRQA
として伝達される。これによりＩ／Ｏは割込み要
求に関するシーケンスを開始し（図示せず）、
iRQを落とす。iRQが落ちることによりiRQB，
iRQCも落ちるが、iRQUはセツト状態に保持さ
れる。（第２図の区間）
ここでCPU３はiRQANSを出すに際して、
iRQCとiRQUとがともにセツト状態にあること
を見て、iRQが取消されていないことを認識す
る。もしこの時点でiRQCが落ちていてiRQUが
立つていれば、iRQが取消されたものと認識す
る。この場合にはiRQANSを出さずにリセツト信
号RSTを出してFF３をリセツトする。 In normal operation, first, when an interrupt request signal iRQ is issued from the I/O 1, it is buffered (iRQB) to the first FF1 in the device 2, latched to the copy FF2, and transmitted to the CPU 3 as iRQC. on the other hand,
The rise of iRQB is detected by the circuit 21, FF3 is set, and the signal is transmitted to the CPU 3 as iRQU.
(Section shown in Fig. 2) The CPU 3 checks whether or not it can accept an interrupt, and if it can accept it, issues a permission signal iRQANS. iRQANS connects iRQA to I/O1 via device 2.
It is transmitted as This causes the I/O to initiate a sequence regarding the interrupt request (not shown).
Drop iRQ. iRQB due to iRQ falling,
iRQC also falls, but iRQU remains set. (Section in Figure 2) Here, when CPU3 issues iRQANS,
It recognizes that iRQ has not been canceled by seeing that both iRQC and iRQU are in the set state. If iRQC is down and iRQU is up at this point, it is recognized that iRQ has been cancelled. In this case, without issuing iRQANS, the reset signal RST is issued to reset FF3.
さらに割込処理が終了したときには、CPU３
はリセツト信号RSTを発し、リセツト制御回路
２２を介してFF３をリセツトする。iRQUが落ち
たことによりiRQANSを落とし、従つてiRQAが
落ちる。（第２図の区間）
尚、第２図のCLKは制御装置２のクロツクで
ある。 Furthermore, when the interrupt processing is finished, CPU3
issues a reset signal RST and resets FF3 via the reset control circuit 22. iRQU drops, which causes iRQANS to drop, and therefore iRQA to drop. (Section in FIG. 2) Note that CLK in FIG. 2 is the clock of the control device 2.
以上の如く本発明によれば要求信号iRQをコピ
ーした信号iRQCと要求信号の立上がりでセツト
される信号iRQUとの２つの信号を見ることによ
り、要求信号の取消されたことを速かに判断で
き、複雑な手順や待時間が不要になる。
As described above, according to the present invention, by looking at two signals: the signal iRQC, which is a copy of the request signal iRQ, and the signal iRQU, which is set at the rising edge of the request signal, it is possible to quickly determine that the request signal has been canceled. , eliminating the need for complicated procedures and waiting times.
第１図は本発明の一実施例回路図、第２図はそ
のタイムチヤートである。
図中、iRQは処理要求信号、FF２は要求信号
をコピーするFF、FF３は要求信号の立上がりで
セツトされるFFである。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart thereof. In the figure, iRQ is a processing request signal, FF2 is an FF that copies the request signal, and FF3 is an FF that is set at the rising edge of the request signal.
Claims (1)
理装置が応答信号を返送して処理を実行し、かつ
処理要求装置が一旦発した要求信号を取消すこと
を許すシステムにおいて、該処理要求装置からの
要求信号をコピーする第１のフリツプ・フロツプ
と、該要求信号の立上りを検出回路で検出し要求
信号がセツトされ、要求処理装置によりリセツト
される第２のフリツプ・フロツプを設け、要求処
理装置は該応答信号の返送に際して、該第１、第
２のフリツプ・フロツプの状態によつて該要求信
号が取消されたか否かを判断するようにしたこと
を特徴とするインタフエースの要求信号制御方
式。1. In a system in which a request processing device executes processing by returning a response signal in response to a request signal from a processing requesting device, and also allows the processing requesting device to cancel a request signal once issued, A first flip-flop for copying a request signal, and a second flip-flop for detecting the rising edge of the request signal by a detection circuit, setting the request signal, and resetting the request signal by the request processing device. 1. A request signal control method for an interface, characterized in that, when returning the response signal, it is determined whether the request signal has been canceled or not based on the states of the first and second flip-flops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17563882A JPS5965330A (en) | 1982-10-06 | 1982-10-06 | Request signal control system of interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17563882A JPS5965330A (en) | 1982-10-06 | 1982-10-06 | Request signal control system of interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5965330A JPS5965330A (en) | 1984-04-13 |
| JPS6242310B2 true JPS6242310B2 (en) | 1987-09-08 |
Family
ID=15999581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17563882A Granted JPS5965330A (en) | 1982-10-06 | 1982-10-06 | Request signal control system of interface |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5965330A (en) |
-
1982
- 1982-10-06 JP JP17563882A patent/JPS5965330A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5965330A (en) | 1984-04-13 |
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