JPH0789327B2 - Information processing system - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information processing system, and more particularly to an interrupt processing system from an information processing apparatus to a fault processing processor.

2. Description of the Related Art Conventionally, in an information processing system, a failure processing processor is provided corresponding to the information processing apparatus, and the information processing apparatus and the failure processing processor have a one-to-one relationship. Therefore, the processing for the interrupt from the information processing apparatus is performed only by the failure processing processor corresponding to the information processing apparatus.

In an information processing system including a plurality of information processing apparatuses, when a failure due to a failure of the information processing apparatus is reported as an interrupt to a failure processing processor, the failure processing is performed by the failure processing processor and the information processing apparatus The system can be operated continuously by disconnecting it from the system.

In such a conventional information processing system, since the information processing device and the failure processing processor have a one-to-one relationship, when the failure processing processor is stopped due to a failure or the like, the information processing device corresponding to the failure processing processor is Even if a failure occurs, it will not be possible to receive a failure report from the information processing device, and failure processing for the failure of the information processing device will have to wait until the recovery of the failure processing processor, and even adversely affect the operation of the system. It has the disadvantage of being

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional ones, and even if a failure processing processor fails, it is possible to perform failure processing for a failure report from an information processing device corresponding to the failure processing processor. The purpose is to provide an information processing system that can be performed.

Configuration of the Invention An information processing system according to the present invention is an information processing system including a plurality of information processing devices and a plurality of fault processing processors provided corresponding to the plurality of information processing devices, respectively. A failure means for sending a failure detection signal from the corresponding information processing apparatus to the own apparatus and another apparatus, failure processing means for performing failure processing in response to the failure detection signal, and failure processing means for the other apparatus. A plurality of fault handling means for discriminating the state, and a discriminating means for discriminating whether or not the fault handling in response to the fault detection signal sent from the sending means of the other device can be executed in the own device; According to the identification means, the processor has the respective processors, and the failure detection signal is sent from the sending means of the other device, and the failure processing in response to the failure detection signal cannot be executed in the other device. When it is determined that the failure processing in response to the failure detection signal is executable by the own apparatus, the failure processing in response to the failure detection signal is executed by the failure processing unit of the own apparatus. It is characterized in that it is performed by.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, fault processors 1 and 2 are interrupt accepting units 11 and 12 that accept a fault detection signal (hereinafter referred to as an interrupt) reported as an interrupt from a corresponding information processing device (not shown), and an interrupt accepting unit 11 , 21, and processor units 12 and 22 for processing the interrupts accepted.

The interrupt acceptance units 11 and 21 are the internal processor interface 1
11,121 is connected to the processor section 12,22 of its own device,
The interprocessor interfaces 112 and 122 are connected to the processor units 22 and 12 of other devices. Further, the processor units 12 and 22 are connected to each other by the processor state interface 101.

FIG. 2 is a flow chart showing the operation of the embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS. 1 and 2.

First, when both the processor units 12 and 22 of the failure processing processors 1 and 2 can perform interrupt processing, the failure processing processor 2
When an interrupt from the information processing device corresponding to the fault processing processor 2 is input to the interrupt accepting unit 21 of, the interrupt accepting unit 21 accepts the interrupt and registers the cause of the interrupt, and the processor units 22 and 12 Issues an interrupt request to the processor via the in-processor interface 121 and the inter-processor interface 122.

The processor unit 22 judges whether or not this interrupt request is a request from the interrupt acceptance unit 21 of its own device (step in FIG. 2).
31) If it is determined that the request is from the interrupt accepting unit 21 of its own device, the interrupt request is accepted and interrupt processing is activated (step 36 in FIG. 2).

On the other hand, the processor unit 12 of the fault processing processor 1 determines that this interrupt request is not the request from the interrupt acceptance unit 11 of its own device (step 31 in FIG. 2), and the processor unit 22 of the other device via the processor status interface 101. The state of is read (step 32 in FIG. 2).

By this reading, if it is determined that the state of the processor unit 22 of the other device can handle the interrupt (step 3 in FIG. 2).
3) In the processor unit 12, the interrupt processing for the interrupt request from the interrupt acceptance unit 21 of the failure processing processor 2 is not performed.

Next, when the processor unit 22 of the fault processing processor 2 is in a state where interrupt processing cannot be performed due to a failure or the like, the interrupt receiving unit 21 of the fault processing processor 2 is notified from the information processing apparatus corresponding to the fault processing processor 2. When the interrupt is input, the interrupt accepting unit 21 accepts the interrupt and registers the cause of the interrupt, and sends an interrupt request to the processor units 22 and 12 via the in-processor interface 121 and the interprocessor interface 122. Issue.

At this time, the processor unit 22 cannot accept the interrupt request because it is in a state in which the interrupt process cannot be performed.

On the other hand, the processor unit 12 of the fault processing processor 1 determines that this interrupt request is not the request from the interrupt acceptance unit 11 of its own device (step 31 in FIG. 2), and the processor unit 22 of the other device via the processor status interface 101. The state of is read (step 32 in FIG. 2).

Based on this reading, the processor unit 12 determines whether the processor unit 22 of the other device is in the interrupt-capable state (step 33 in FIG. 2). If it is determined that the processor unit 22 is in the interrupt-incapable state, the processor The unit 12 takes out the interrupt factor registered in the interrupt receiving unit 21 of the fault processing processor 2 and obtains detailed information of this interrupt request (step 34 in FIG. 2).

Further, the processor unit 12 discriminates, from among the interrupt factors taken out from the interrupt receiving unit 21, those which can be executed instead of the interrupt processing and those which cannot be executed (step 35 in FIG. 2).

When it is identified that the interrupt processing can be executed instead, the interrupt factor from the interrupt receiving unit 21 is accepted, the interrupt request is accepted, and the interrupt processing is activated (step 36 in FIG. 2).

When it is identified that the interrupt process cannot be executed instead, the interrupt factor of the interrupt accepting unit 21 is registered as it is, and the interrupt process for the interrupt request from the interrupt accepting unit 21 is not performed in the processor unit 12.

By registering the interrupt factor in the interrupt accepting unit 21 as it is, when the processor unit 22 which has been in the interrupt-disabled state becomes the interrupt-enabled state, the processor unit 22 accepts the interrupt. Interrupt processing can be executed.

Here, if something that can be executed instead of interrupt processing and something that cannot be executed occur at the same time, the processor unit
In 12, the interrupt process is executed which can be executed in the alternative, but the interrupt factor which cannot be executed in the alternative is registered in the interrupt accepting unit 21 as it is.

When an interrupt from the information processing device corresponding to the fault processing processor 1 is input to the interrupt accepting unit 11, if the processor unit 12 of the fault processing processor 1 is in a state where interrupt processing cannot be performed, the above-described processing operation is performed. In the same manner as above, the interrupt processing, which can be executed by the processor unit 22 of the failure processing processor 2 instead, is executed.

In this way, when an interrupt from the information processing device corresponding to the fault processing processor 2 is input to the interrupt accepting unit 21, the interrupt accepting unit 21 notifies the processor unit 22 of its own device and the processor unit 12 of another device. When an interrupt request is issued and the processor unit 22 of the own device is in a state in which interrupt processing is not possible, the processor unit 12 of the other device performs interrupt processing so that the failure processing processor 2
Even if the failure occurs, the failure processing for the failure report from the information processing apparatus corresponding to the failure processing processor 2 can be quickly performed by the processor unit 12 of the other apparatus, and the configuration change processing of the information processing system can be quickly performed. be able to.

EFFECTS OF THE INVENTION As described above, according to the present invention, a failure detection signal from an information processing apparatus corresponding to another apparatus is sent from the other apparatus to the own apparatus, and the failure processing is executed in response to the failure detection signal. When it is determined that the failure processing is not possible in the apparatus, the failure processing in response to the failure detection signal is executed by the apparatus itself, so that even if the failure processing processor fails, the information processing corresponding to the failure processing processor is performed. There is an effect that it is possible to execute a failure process for a failure report from the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the embodiment of the present invention. Explanation of symbols of main parts 1,2 …… Fault handling processor 11,21 …… Interrupt acceptance unit 12,22 …… Processor unit 101 …… Processor status interface 111,121 …… Internal processor interface 112,122 …… Interprocessor interface

Claims (1)

[Claims] 1. An information processing system including a plurality of information processing devices, and a plurality of fault processing processors provided corresponding to the plurality of information processing devices, respectively. Sending means for sending the fault detection signal to the own device and another device, fault handling means for performing fault handling in response to the fault detection signal, and identification means for identifying the state of the fault handling means of the other device And each of the plurality of fault processing processors has a discriminating means for discriminating whether or not the fault processing in response to the fault detection signal sent from the sending means of the other device can be executed in the own device, The determination is made when the fault detection signal is transmitted from the transmission unit of the other device, and the identification unit determines that the fault processing in response to the fault detection signal cannot be executed in the other device. When the step determines that the failure processing in response to the failure detection signal can be executed in the own device, the failure processing in response to the failure detection signal is executed by the failure processing means of the own apparatus. Information processing system.