JPS6242413B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates primarily to a pulse generation circuit for driving a stepping motor.

Generally, the torque-to-revolutions characteristic of a stepping motor is as shown in FIG. In FIG. 1, the vertical axis represents torque and the horizontal axis represents rotational speed. In the figure, indicates an area where instantaneous driving and instantaneous stopping can be performed, that is, a pull-in area, and indicates an area other than that, that is, a pull-out area. Instantaneous drive and instantaneous stopping are not possible in the pullout area. In order to maximize the characteristics of such a stepping motor, it is necessary to use it up to the pull-out region. Therefore, when the stepping motor is driven and stopped, acceleration and deceleration control must be performed so that the speed-time characteristic is as shown in FIG. 2A.

In FIG. 2a, the vertical axis represents speed and the horizontal axis represents time. In the figure, 1 indicates a triangular characteristic, and 2 indicates a trapezoidal characteristic. The arrows shown in the figure indicate the passage of time. That is, when driving, it is operated at a low speed, and then the speed is increased to the pull-out region.
When the stepping motor is stopped, the characteristics of the stepping motor can be maximized by controlling the motor to slow down again. However, even if such characteristics are provided, problems still remain.

FIG. 2b is a diagram showing the acceleration curve of the characteristic diagram shown in a. The broken line in the figure indicates the triangular characteristic acceleration curve shown in FIG. Also shown in the figure are the positions of these change points corresponding to change points A, B, C, D, and G in figure a. Generally, the load torque characteristics of a stepping motor decrease as the speed increases, as shown in the load torque curve in FIG. Therefore, compared to points A and B in Figure 2b, C,
At point D, the magnitude of acceleration is the same, but the output torque is smaller at point D, so vibration is more likely to occur.
In some cases, it may cause loss of synchronicity.

In order to eliminate such drawbacks, see a in Figure 4.
Acceleration/deceleration control may be performed to obtain the characteristics shown in FIG. That is, new change points E and F are provided between points A and C and between points D and B, respectively, to slow down the change in acceleration. b in the same figure shows the acceleration curve of the characteristic diagram shown in a. As can be seen from b, the amount of change in acceleration is smaller than that shown in FIG. Therefore, the torque required for operation is small, and vibrations, step-outs, etc. do not occur.

However, it is not easy to obtain a pulse generating circuit having the characteristics as shown in FIG. 2 or 4, and the characteristics shown in FIG. 2 or 4 can only be obtained approximately. On the other hand, with the recent development of microcomputer technology, it has become possible to program the characteristics shown in FIG. 4 into memory. With such a programming method, it is certainly possible to obtain a pulse generating circuit with characteristics as shown in FIG. However, there are problems such as the upper limit speed of the generated pulses being restricted due to the slow machine cycle of the microcomputer, the need for a large amount of memory for programming, and the inability to easily change the characteristics.

The present invention has been made in view of these points, and has realized a pulse generating circuit having characteristics as shown in FIG. 4 with a simple configuration. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 5 is an electrical connection diagram showing one embodiment of the present invention. In the figure, 1 is an up-down counter, 2 is a first latch circuit, 3 is a full adder, and 4 is an up-down counter.
is a second latch circuit, 5 is a clock frequency switching circuit, 6 and 7 are down counters, 8 is a 1/2 frequency divider,
9 to 15 are various gates.

The up-down switching signal and CLOCK1 are input to the up-down counter 1. CLOCK1 is a switch SW, which selects either frequency f ₀ or f ₀ /2. The output of the up-down counter 1 enters the first latch circuit 2. A strobe signal is inputted to the first latch circuit 2 from the gate 11, and data applied from the up-down counter 1 is latched by this strobe signal.

The output of the first latch circuit 2 enters the full adder 3. The full adder 3 receives the output of the latch circuit 2, and the output thereof is input to the second latch circuit 4. The output of the full adder 3 and CLOCK2 are input to the second latch circuit 4. The output of full adder 3 is latched by CLOCK2. The latched output of the second latch circuit 4 is fed back to the input section of the full adder 3 as it is. Since the full adder 3 receives the outputs of the first and second latch circuits, it generates a carry signal every time its contents exceed the rated value. That is, full adder 3
A circuit including the second latch circuit 4 and the second latch circuit 4 constitutes a pulse oscillation circuit that receives the output of the first latch circuit 2 and outputs a carry signal.

The carry signal from the full adder 3 is input to the down counters 6 and 7 and the 1/2 frequency divider 8 via the gate 9. The output V ₀ of this 1/2 frequency divider 8 becomes the output of the pulse generation circuit shown in FIG. On the other hand, the number of generated pulses can be set in the down counters 6 and 7. The number of generated pulses is the number of pulses that can be generated by the pulse generation circuit shown in the figure. For example, in the case of an NC machine, positioning is performed by operating a stepping motor by this number of generated pulses. Further, for example, if the number of generated pulses is 50, the down counters 6 and 7 are both set to 50. The zero detection signal of the down counter 6 is input to the down counter 7 via an inverter 14 and a gate 15, and is also input to the up/down counter 1, where it is used as an up/down switching signal. Furthermore, it is also input to itself via the gate 13. On the other hand, the zero detection signal of the down counter 7 is input to the gate 9 and controls the passage of the carry signal of the full adder 3 which is also input to the gate 9. The output of gate 9 is 1/2 as mentioned above.
In addition to the frequency divider 8, the down counter 7 also has a gate 15.
I am entering it through.

The output of the Nth bit (N is an integer greater than 1) of the up-down counter 1 is input to the gate 11 via the inverter 10 and also to the gate 12. The other input of gate 11 has
CLOCK3 is input, and its output is the first
is applied to the latch circuit 2 as a strobe signal for the latch circuit 2. The other input of the gate 12 is applied with the output of an arbitrary bit of the up-down counter, for example, the (N-1)th bit. The output of this gate 12 is the frequency changeover switch.
It has come to control SW. Figure 6 is the 5th
This is a time chart showing the relationship of signals in each part of the figure. The names shown at the left end of FIG. 6 are the names of the signals. The operation of the circuit shown in FIG. 5 will be explained with reference to FIG.

First, an outline of the operation of the present invention will be explained using FIG. 6. At the start, CLOCK1 with frequency f ₀ is added to up-down counter 1, and when the output value of counter 1 reaches a certain value [for example, the (N-1)th bit is "1"], switch SW is changed and the counter Add the frequency f ₀ /2 to 1. Therefore, the input CLOCK1 of the up-down counter 1 changes as shown in a of FIG.

The up-down counter 1 is
Since CLOCK1 is initially counted up, its output increases as time passes. and,
After a certain point, the count changes to a down count, so the output value gradually decreases and finally reaches "0". That is, the output of the up-down counter 1 changes as if the number of pulses of CLOCK1 in a of FIG. 6 was integrated.

The first latch 2 outputs the output as soon as the output of the up-down counter 1 is introduced until the Nth bit of the up-down counter 1 becomes "1" [point C in b in FIG. 6]. Then, the Nth bit is “1”
Then, since the output of up-down counter 1 at that time is held, the output _D0 of latch 2 is the 6th one.
It changes as shown in b in the figure. That is, the first latch 2
The output D ₀ of is similar to diagram a in FIG. In addition, due to space limitations, Figure 6 shows F and F in Figure 4.
The illustration of part B is omitted.

Full adder 3 has a certain capacity and adds the output signals of latches 2 and 4. When the addition result exceeds the capacity, one carry signal is output to the gate 9, and the outputs of latches 2 and 4 are added again, and a carry signal (pulse signal) is output each time the addition result exceeds the capacity. On the other hand, latch 2 added to full adder 3
The output signal D ₀ of is a signal that changes as shown in b in FIG. The carry signal changes as shown in c in FIG. That is, the carry signal initially starts with a low frequency of occurrence, but at A of b in FIG.
The frequency of occurrence becomes higher depending on the slope between -E. Since the slope becomes gentle between E and C in b of FIG. 6, the increasing tendency of the occurrence frequency of the carry signal also changes gradually. And C-D in b of Fig. 6
In between, since the slope is O, the frequency of occurrence of carry signals stops increasing and occurs at a constant period. After passing D in FIG. 6B, the slope becomes negative, so the frequency of occurrence of the carry signal gradually decreases. In this way, the carry signal of the full adder 3 changes as shown in c in FIG.

This carry signal is passed through gate 9 and 1/2 frequency divider 8.
Therefore, the circuit of FIG. 5 according to the present invention outputs a pulse signal V ₀ which is obtained by thinning the signal shown in c of FIG. 6 to 1/2.

If the stepping motor is driven with this pulse signal V ₀ , the characteristics shown by a in FIG. 4 will be obtained.

That is, the stepping motor rotates by a fixed angle step each time one pulse shown in FIG. Therefore, as the frequency of pulse generation in FIG. 6c increases, the rotational speed of the stepping motor increases. Here, in the period A-E of FIG. 6b,
Although the frequency of occurrence of the pulse shown in FIG. 6c is lower than the frequency of occurrence between E and C and between C and D in FIG. 6B, the rate of increase in the frequency of occurrence is the highest. That is, during the period A-E of FIG. 6b, the rotational speed of the stepping motor is low, but the rate of increase in the rotational speed is the highest.

Then, in the E-C period of FIG. 6b, the 6th
The pulse generation frequency shown in FIG. c is higher than the generation frequency between A and E, but the rate of increase is lower. Therefore, the sixth
Although the rotational speed of the stepping motor is higher in the period E-C in FIG. 2B than in the period A-E, the rate of increase in the rotational speed is lower.

Then, in the CD period of FIG. 6b, the 6th
The frequency of pulse occurrence shown in FIG. c is higher than the frequency of occurrence during the EC period, but the frequency of occurrence remains constant. Therefore, during the period CD in FIG. 6b, the rotational speed of the stepping motor is at its highest speed, but the rotational speed is a constant value.

Thereafter, the stepping motor rotates in accordance with the pulse generation frequency shown in FIG. 6c by the same operation after D in FIG. 6b.

Therefore, the change in speed of the stepping motor can be expressed as a time course as shown in FIG. 4.

The operation will be explained in detail below.

At the start, all elements are reset. Further, the number of generated pulses is set in the down counters 6 and 7. The up-down counter 1 receives an up-down switching signal from the down counter 6 and is in an addition (also called up-count) mode. In the reset state, all the outputs of the up-down counter 1 are 0, and the output of the gate 12 that receives these outputs is also 0 and CLOCK 1.
is set on the f ₀ side.

At the same time as the start, CLOCK1 becomes the up-down counter 1, and CLOCK2 becomes the second latch circuit 4.
Then, CLOCK3 is input to gate 11.

Here, the timing relationship between CLOCK1, CLOCK2, and CLOCK3 will be described. CLOCK1 and CLOCK
3 is a synchronous relationship (for example, the signal applied from switch SW to up-down counter 1 is f _i
Then, CLOCK3 and f _i are the same signal).

Note that CLOCK1 is set to f ₀ by the frequency switching circuit 5.
If it becomes f ₀ /2, CLOCK3 will also change accordingly.
Switches from f ₀ to f ₀ /2.

On the other hand, CLOCK2 is a signal unrelated to the phase of CLOCK1, and even if CLOCK1 changes from f ₀ to f ₀ /2 by the frequency switching circuit 5, the frequency of CLOCK2 is unaffected and remains constant.

In this state, up-down counter 1 is
Since CLOCK1 of frequency f ₀ shown in FIG. 6A is added, the contents of up-down counter 1 increase with the passage of time.

0 to (N-1) of this up-down counter 1
The output of the bit is applied to the first latch circuit 2. At this point, the output of the Nth bit of up-down counter 1 is "0", so
This "0" signal is inverted by the inverter 10 and is applied to the gate 11 as a "1" signal.
Therefore, since the gate 11 is in an open state, the latch timing is determined by the CLOCK3 timing. Here, CLOCK3 is as mentioned above,
Since the signal is synchronized with CLOCK1, the change in the output value _D0 of the first latch 2 is synchronized with the change in the output of the up-down counter 1. Therefore, the output D ₀ of the first latch circuit 2 changes as if the number of pulses a in FIG. 6 is integrated, and becomes as shown in b in FIG. 6. Note that A, E, C, and D labeled in Figure 6b correspond to the same symbols in Figure 4, and
The symbols (N-1) and N in FIG. b indicate the contents of the up-down counter 1.

The output D ₀ of the latch circuit 2 enters the full adder 3,
The output of the full adder 3 is fed back to the full adder 3 itself via the second latch circuit 4.

Therefore, the full adder 3 adds the respective outputs of the first and second latch circuits 2 and 4. Since CLOCK2 has the same or higher frequency than CLOCK3, a change in the output _D0 of latch circuit 2 immediately becomes a change in the output of latch circuit 4. The full adder 3 has a certain capacity and outputs one carry signal every time this capacity is exceeded.This full adder 3 and the second latch circuit 4 constitute a pulse oscillation circuit. There is. Since the output D ₀ of the first latch circuit 2 changes as shown in FIG. 6b, the carry signal output from the full adder 3 becomes as shown in FIG. 6c. Here, c in FIG. 6 will be explained. Initially, the output D ₀ of the latch circuit 2 applied to the full adder 3 is a small value as shown in b in FIG. 6 (therefore, the output value of the latch circuit 4 is also small), so the capacity of the full adder 3 is It takes time to fill up. Therefore, the carry signal occurs at a low frequency at the start, as shown in FIG. 6c. However, the sixth
Since the slope between A and E in b of the figure is steep, the frequency of occurrence of carry signals increases rapidly.

Furthermore, the operation in which the carry output of the full adder 3 is as described above [as shown in FIG. 6c] will be explained using FIG. Figure 8 is a further enlargement of the time axis of Figure 6, and depicts the relationship between the output D ₀ of the first latch circuit 2 and the carry output of the full adder 3 using CLOCKs 1 to 3. This is a diagram. As mentioned above, CLOCKs 1 and 3 are synchronized signals, and these two CLOCKs are shown in a and b of FIG. 8. Therefore, the output _D0 of the first latch circuit 2 into which the output of the up-down counter 1 is introduced changes stepwise as shown in FIG. 8C. Although the output D ₀ of the latch circuit 2 is a digital value, it is shown in a stepwise manner in FIG. 8 to make it conceptually easier to understand. In addition, in FIG. 6b, it is drawn in a reduced scale, so it has a smooth slope. The numerical value attached to this stepwise waveform is the content of the latch circuit 2 (the count number of the up-down counter 1).

Figure 8d shows CLOCK2, usually CLOCK1
It is a higher frequency. In Figure 8d, CLOCK
The case where the frequency is 10 times that of 1 is depicted.

Now, the contents of full adder 3 and its output D
_A (outputs applied to latch circuit 4) are both “0”, and output of latch circuit 2 input to full adder 3
Suppose that D ₀ =Y (constant). Since D ₀ =Y, the output D _A of the full adder 3 becomes Y. This D _A
=Y value is added to latch circuit 4 and CLOCK2
When is applied once, the value of "Y" is added to the full adder 3 via the latch circuit 4. Therefore, the full adder 3 adds D ₀ =Y and "Y" fed back from the latch circuit 4, and applies D _A =2Y to the latch circuit 4. Then, when the next CLOCK2 is applied one time, this value of "2Y" is fed back to the full adder 3 via the latch circuit 4. Therefore, the full adder 3 adds D ₀ =Y and "2Y" fed back from the latch circuit 4, and adds D _A =3Y to the latch circuit 4. In this way, the contents of full adder 3 change to “Y” every time CLOCK2 is applied once.
It operates in such a way that it increases by increments. That is, CLOCK2
If n shots are added, it will increase by n·Y. Furthermore, even when the output D ₀ of the first latch 2 changes to "Y", the content of the full adder 3 increases by this "Y", so it changes to D ₀ =Y, and in this state,
If CLOCK2 is applied n times, the content of full adder 3 increases by (n+1)Y.

In Figure 8 d, the frequency of CLOCK2 is
This shows an example of 10 times the value of 10. If it is assumed that one carry output is issued each time the content of the full adder 3 becomes "64", the result will be as shown in FIG. 8e.
That is, the carry output terminal of full adder 3 is normally at high level, but when its content becomes "64", it momentarily falls to low level and then becomes high again.
I'm starting to get back to level. Such an operation can be easily realized by incorporating a monostable multivibrator (not shown) in the full adder 3. That is, the period during which the carry output terminal is at low level can be determined by the time constant of this built-in monostable multivibrator.

The operation shown in FIG. 8e will be explained using specific numerical values. The numerical values written between c and d in FIG. 8 are the contents of the full adder 3. The initial value of the full adder is 0. When the output D ₀ of latch 2 becomes 1, the content of full adder 3 (hereinafter simply referred to as "content") becomes 1. Next, each time CLOCK2 occurs, the "content" increases by 1, and when the 10th CLOCK2 occurs, the "content" becomes 11. Then, when the output D ₀ of latch 2 becomes 2, the "content" becomes (11+2=13). Subsequently, each time CLOCK2 occurs, the “content” increases by 2, and when D ₀ = 2, the 10th shot
When CLOCK2 occurs, the "content" becomes 33. Next, when D ₀ =3, the "content" becomes (33+3=36). When the 10th CLOCK2 occurs in the state of D ₀ =3, the "content" becomes (64+2). Therefore, 64
, the full adder 3 outputs the first carry pulse, and the "content" becomes the overflowed remaining 2, and a new addition is started with 2 as the initial value. Next, when D ₀ =4, the "content" becomes (2+4=6). Below, CLOCK2
Each time ``content'' occurs, the ``content'' increases by 4. Next, D ₀ = 5, and in the state of D ₀ = 5, the third shot
When CLOCK2 occurs, the "content" becomes (64+2) and the second pulse is output. Thereafter, similar operations result in a waveform as shown in FIG. 8e.

Figure 8 f shows that the frequency of CLOCK2 is CLOCK1
This shows an example of 5 times the value of 1. If we assume that the full adder 3 outputs one carry output each time the content of the full adder 3 becomes "64" as described above, the result will be as shown in Figure 8g. Become.

The operation shown in FIG. 8g will be explained using specific numerical values. The numerical values written between e and f in FIG. 8 are the contents of the full adder 3. The initial value of the full adder is 0. When the output D ₀ of latch 2 becomes 1, the "content" becomes 1. Next, each time CLOCK2 occurs, the “content” increases by 1, and when D ₀ = 1, the 5th shot
When CLOCK2 occurs, the "content" becomes 6. Next, when the state of D ₀ =2 occurs and the fifth CLOCK2 occurs, the "content" becomes 18. Next, when the fifth CLOCK2 occurs after D ₀ =3, the "content" becomes 36. Next, when the fifth CLOCK2 occurs after D ₀ = 4, the “content” is
It will be 60. Next, when D ₀ = 5, the “content” is (64
+1), and the first carry pulse is output. Full adder 3 starts adding again from the remaining 1 that overflowed, and when the fifth CLOCK2 occurs in the state of D ₀ = 6, the “content”
becomes 62. Next, when D ₀ =7, the "content" becomes (64+5), and the second carry pulse is output. Following the same operation, the 8th
The waveform will be as shown in Figure g.

As explained above, the output D ₀ of the latch circuit 2 =
In state 1, even if CLOCK2 is applied 10 times,
The contents of full adder 3 only increase by “10” and then
Even if the state shifts to D ₀ =2 and CLOCK2 is subsequently applied 10 times, the content of the full adder 3 increases by only "10+20" from the initial state. In this way, when the value of D ₀ is small, the full adder 3 does not become full easily even if a large number of CLOCK2 signals are applied.

On the other hand, in a state where D ₀ = 8, for example, the contents of the full adder 3 increase by "8" each time CLOCK2 is applied once, so if CLOCK2 is applied 8 times, it increases by "64" and becomes full. , one carry output occurs.

In this manner, as the output D ₀ of the latch circuit 2 increases, the frequency of occurrence of the carry signal output from the full adder 3 rapidly increases. Therefore, it changes as shown in FIG. 6c.

The contents of up-down counter 1 are as follows:
Since CLOCK1 is added, it increases in proportion to time. The area from A to E in FIG. 4a is the area in which the up-down counter 1 increases until the (N-1)th bit becomes ``1''.

When the (N-1)th bit of the up-down counter 1 becomes "1", the output of the gate 12 becomes "1", and the frequency changeover switch SW is set to f ₀ /2.
[See a and b in Figure 6].

At this time, the integer N is selected so that the speed of the motor is 1/2 of the maximum speed N ₀ , that is, N ₀ /2. After the frequency of CLOCK 1 switches from f ₀ to f ₀ /2, up-down counter 1 now adds up at a rate twice as slow as before. Therefore, the output D ₀ of latch 2 also has a gentle slope as shown by E-C in FIG. 6b. This state corresponds to the region E to C shown in FIG. 4a. As the addition progresses, "1" is set at the Nth bit. This point is shown in Figures 4a and 6.
This is point C shown in Figure b.

When "1" is set at the Nth bit, this "1" signal is inverted by the inverter 10 and "0" is applied to the gate 11, so that the gate 11 is closed. Therefore, the strobe signal is no longer input to the first latch circuit 2, and the output _D0 of the first latch circuit 2 remains constant even though the input data to the latch circuit 2 is constantly changing. This state is a flat region starting from point C shown in FIGS. 4a and 6b. Therefore, the frequency of occurrence of the carry output of the pulse oscillation circuit composed of the full adder 3 and the second latch circuit 4 remains constant regardless of the passage of time [see FIG. 6c]. Although the frequency of occurrence of carry output is constant, the contents of up-down counter 1 continue to increase gradually.

However, the contents of up-down counter 1 continue to increase infinitely, and the Nth bit becomes "1" again.
It can be set in advance so that it never becomes "0". That is, the pulse generating circuit according to the present invention is used in a stepping motor used for driving an NC machine, a robot arm, a recording pen of a plotter, and the like. Since the moving distance of the movable parts of these devices (the number of pulses output from the pulse generating circuit of the present invention) has a limit, the contents of the up-down counter 1 will not increase infinitely. Since the maximum moving distance is also known in advance at the design stage, the Nth bit becomes “1” again →
It can be set so that it never becomes "0".

While this up-down counter 1 continues to add CLOCK 1, it counts the number of pulses of the carry signal of the full adder 3 of the down counter 6, and the content finally becomes "0". The operation of the down counters 6 and 7 will now be explained with reference to FIG. d to g in FIG. 6 show the contents of the down counters 6 and 7 and the state of the zero detection signal.

At the start of pulse generation, the zero detection signals of the down counters 6 and 7 are both "high" as shown in FIG. 6e and g, so the gates 9 and 13 to which these zero detection signals are applied are The gate will be open. On the other hand, since the zero detection signal whose polarity is inverted by the inverter 14 is applied to the gate 15, the gate is closed.

Therefore, at the start, the carry signal output from the full adder 3 passes through the gates 9 and 13 and is added to the down counter 6. On the other hand, since the gate 15 of the down counter 7 is closed, this carry signal is not input. That is, the down counters 6 and 7 constitute means for counting carry signals, and the gates 13, 14, and 15 constitute means for operating the down counter 7 after operating the down counter 6.

In this way, at the start, the down counter 6 counts the number of pulses of the carry signal as shown in FIG. 6c, as shown in FIG. 6d. FIG. 6 shows a case where, for example, 50 is set as an initial value in the down counter 6. down counter 6
, its contents are lowered each time a pulse of the carry signal is added, and finally its contents become "0".

When this content becomes “0”, the down counter 6
changes the level of the zero detection signal from "high" to "low" [see Figure 6e].

The following change occurs due to the zero detection signal of the down counter 6 becoming "low".

The up-down counter 1 is inverted from the previous addition mode to the subtraction mode.

The gate 13 is closed because "low" is applied, and the gate 15 is opened because "high" is applied via the inverter 14.
Incidentally, since the state of the zero detection signal of the down counter 7 has not changed, the gate 9 remains open. As a result of the above, a carry signal is now added to the down counter 7, and its contents begin to decrease [see f in FIG. 6].

The up-down counter 1 continues to decrement and returns to N.
The bit returns to 0. This point is D shown in Figure 4a.
It is a point. When the Nth bit returns to 0, the gate 11 opens again and a strobe signal is applied to the first latch circuit 2. Therefore, as the content of the up-down counter 1 decreases, the frequency of the output pulse also gradually decreases. As more time passes, the (N-1)th bit of the up-down counter also becomes 0.
become. The state up to this point corresponds to areas D to F shown in FIG. 4a. The point in time when the (N-1)th bit becomes 0 is point F in FIG. 4a.

When the (N-1)th bit becomes 0, the output of gate 12 becomes 0, and the frequency of CLOCK1 becomes 0.
Switching from f ₀ /2 to f ₀ , the rate of decrease increases. As the down counter 1 continues to subtract, and when the contents of the down counter 7 reach 0 and a zero detection signal is output, the gate 9 closes and the circuit stops outputting pulses. That is, down counter 7 introduces a carry output through open gates 9 and 15, and its content is decreased each time a carry output occurs. When there is a 50th carry output after the down counter 7 starts counting, the zero detection signal of the down counter 7 becomes "low". Therefore, regardless of the state (high, low) of the carry output terminal of the full adder 3, the output of the gate 9 is fixed to "low". That is, the gate 9 is closed and the carry output is no longer applied to the 1/2 frequency divider 8. The state up to this point is shown in Figure 4a.
This is the area from F to B. In this way,
The circuit shown in FIG. 5 is a pulse generating circuit capable of generating pulses having characteristics as shown in FIG. 4a.

As can be seen from the above explanation, this pulse generation circuit generates twice the set number of pulses, so the 1/2 frequency divider 8 converts it to the original number of pulses. The output V ₀ of the 1/2 frequency divider 8 becomes the output of this circuit.

In Figure 5, the frequency of CLOCK1 is f ₀ , f ₀ /2
Although the value is selected to be 2 times, it is not necessary to limit it to 2 times, and any value may be used. Further, although the frequency switching by the switch SW is set to two points, it is not necessary to limit the frequency to two points, and any number of frequencies may be provided, and these may be sequentially switched.

Also, add it to updown counter 1
By changing the value of frequency f ₀ of CLOCK1,
The frequency of occurrence of the carry signal of the full adder 3 can be adjusted. That is, the frequency of the output V ₀ of the pulse generating circuit shown in FIG. 5 can be varied. The reason for this will be omitted since it is clear from the above explanation of the operation.

Also, if you add another bit, for example, the (N-k)th bit, in place of the (N-1)th bit signal applied to the gate 12, the corner positions of points E and F in Fig. 4 can be changed. .

Further, although the above description has been made assuming that the frequency value of CLOCK2 is constant, the frequency of the output signal _V0 of the pulse generation circuit shown in FIG. 5 can also be changed by changing CLOCK2. In this case, a characteristic as shown in FIG. 7 [time-velocity characteristic corresponding to a in FIG. 4] can be obtained. The reason why the characteristics as shown in FIG. 7 can be obtained will be explained below. FIG. 8f shows the case where the frequency of CLOCK2 mentioned above, that is, the frequency of FIG. 8d is changed to 1/2. If you reduce the frequency of CLOCK2 to 1/2,
Since the number of times the signal from the latch circuit 4 is fed back to the full adder 3 is reduced by half, the frequency of occurrence of carry output from the full adder 3 becomes as shown in FIG. 8g. That is,
Since the frequency of CLOCK2 has become 1/2, Figure 8g
The frequency of occurrence of the carry output shown in Figure 8e is 1/
Reduced to 2. This rate of decrease is uniform throughout the entire area from point A to point B shown in Figure 4, so
By changing the frequency of CLOCK2, the 7th
The characteristics shown in the figure can be obtained. Such an operation will be quantitatively explained below. The full adder 3 is generally a circuit with a capacity of ²ⁿ , and the pulse oscillation circuit composed of the full adder 3 and the second latch circuit 4 is a so-called DDA (digital differential analyzer).
...This circuit is called a counting type differential analyzer).
Assuming that the frequency of the output of this DDA, that is, the carry signal, is f _D , the frequency of CLOCK2 is f _C2 , and the output of the first latch circuit is D ₀ , the following equation holds.

f _D = (D ₀ /2 ⁿ )・f _C2 Therefore, by changing the value of the frequency f _C2 of CLOCK2, the frequency f _D of the carry signal can be changed as a whole, so as shown in Fig. 7. The characteristics shown can be obtained.

That is, when the output of the up-down counter 1 is fixed, the frequency of the output _V0 of the pulse generating circuit shown in FIG. 5 can be changed by changing the frequency of CLOCK2.

As explained above in detail, according to the present invention, it is possible to realize a pulse generation circuit with a simple configuration that can maximize the characteristics of a stepping motor and that does not cause vibration or step-out during high-speed rotation. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the characteristics of a stepping motor, FIG. 2 is a diagram showing the driving characteristics of the stepping motor, and FIG. 3 is a diagram showing the torque characteristics of the stepping motor. FIG. 4 is a diagram showing the driving characteristics of the stepping motor according to the present invention, FIG. 5 is an electrical connection diagram showing an embodiment of the present invention, and FIGS.
The figure is the time chart of the signals of each part in Figure 5, and Figure 7 is the time chart when changing the frequency of CLOCK2.
FIG. 3 is a diagram showing speed characteristics. 1... Up-down counter, 2, 4... Latch circuit, 3... Full adder, 5... Frequency switching circuit, 6, 7... Down counter, 8... 1/2 frequency divider, 9 to 15 ……Gate.

Claims (1)

[Claims] 1. An up-down counter that can count by switching between two modes, addition and subtraction, by introducing a first clock and a zero detection signal, and an arbitrary bit of this up-down counter. a switching circuit that switches the frequency of the first clock in synchronization with a change in the state of the arbitrary bit; and a switching circuit that switches the frequency of the first clock in synchronization with the change in the state of the arbitrary bit; 1 latch circuit, the Nth bit which is the next most significant bit of the up-down counter output, and a third clock,
Introducing a strobe signal generation circuit 11 that controls the generation of a strobe signal based on the "high" or "low" state of this Nth bit and applies this strobe signal to the first latch circuit, and the output of the first latch circuit. a second latch circuit that introduces the output of the full adder and a second clock, and feeds back the output of the second latch circuit to the full adder; A pulse oscillation circuit whose output is the carry signal of the full adder, a gate 9 which receives the carry signal of this pulse oscillation circuit, and first and second gates which count the output of the pulse oscillation circuit via the gate 9. counters 6 and 7, and the first
a second counter is operated after operating a second counter, and when the first counter reaches a set number of pulses, a zero detection signal is applied to the up-down counter to switch the mode;
a counting means for applying a zero detection signal to the gate 9 to stop the output of the pulse oscillation circuit when the counter reaches a set number of pulses;