JPH081679B2 - Data output type incremental encoder - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an incremental encoder used in robots.

[0002]

2. Description of the Related Art A conventional incremental encoder detects a two-phase pulse signal and an origin signal with rotation,
These signals were sent to the host controller.

[0003]

In recent years, high precision and high speed transmission characteristics have been demanded, but the conventional incremental encoder has technical limitations and cannot meet these demands.

An object of the present invention is to provide a data output type incremental encoder which can meet the requirements of high accuracy and high speed of transmission characteristics.

[0005]

A data output type incremental encoder of the present invention inputs pulse signals of a first phase and a second phase and differentiates the rising and falling edges thereof to generate a quadrupled signal. A differentiation circuit that outputs the quadruple multiplied signal from the first output terminal or the second output terminal according to the phase relationship between the first-phase pulse signal and the second-phase pulse signal; The 4 × signal output from the second output terminal is input from the 1st and 2nd input terminals respectively, and when the 4 × signal is input from the 1st input terminal, the 4 × signal is up-counted. However, when the quadruple-multiplied signal is input from the second input terminal, the count values of the first and second counters that count down the quadruple-multiplied signal and the count values of the first and second counters are parallel / Serial to serial number , A second P / S converter, a serial data output circuit that sequentially outputs serial outputs of the first and second P / S converters, and a serial data output circuit provided between the differentiating circuit and the first counter, A second gate of the quadruple signal is provided between the first gate circuit for permitting / inhibiting the output of the quadruple signal to the first counter by the first mode signal, the differentiating circuit, and the second counter. Second input to the counter
A second gate circuit for permitting / inhibiting by the mode signal and a mode signal generating circuit for generating the first and second mode signals by the origin signal.

[0006]

[Operation] Depending on the combination of the first and second mode signals, there are three combinations of starting / stopping the first and second counters. (1) When the power of the incremental encoder is turned on, only the first counter is started and the second signal is detected when the origin signal is detected.
Start the counter of.

In this case, the value of the first counter is the position loop data LOOP, and the value of the second counter is the position data POS from the origin. By sending both data at a certain time point after the second counter is activated to the host controller, the position loop data LOO
P, position data POS, origin deviation (= LOOP
-POS) is known. (2) When the incremental encoder power is turned on, only the first counter is started, and the first signal is detected when the home signal is detected.
The second counter is started while the second counter is stopped.

In this case, the first counter is stopped when the first counter is stopped.
The counter value of indicates the origin deviation. Then, the value P of the second counter after starting the second counter is set to this value.
The position loop data LOOP is obtained by adding the OS. Therefore, by sending the value of the first counter when the first counter is stopped and the value of the second counter to the host controller, the position loop data LOO
The deviation of P, the position data POS, and the origin can be known. (3) When the incremental encoder power is turned on, both counters are started, and when the origin signal is detected, only the second counter is stopped.

In this case, the value of the first counter indicates the position loop data LOOP, and the value of the second counter when the second counter is stopped indicates the deviation of the origin. The value obtained by subtracting the value of the second counter from the value of the first counter becomes the position data POS of the origin. Therefore, by sending the value of the first counter and the value of the second counter at the time of stop to the host controller, the position loop data LOOP and the position data POS can be obtained.
And you can see the deviation of the origin.

As described above, the incremental encoder of the present invention creates the position data and sends it to the host controller, so that it is possible to meet the demand for the transmission characteristics of high accuracy and high speed.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a circuit which constitutes an incremental encoder according to an embodiment of the present invention and which differentiates the two-phase signals PA and PB, counts the differentiated signals by two counters and sends them to a host controller. 2 is a diagram showing the timing of transmitting the count value in FIG.

This circuit comprises a differentiating circuit 1, a counter 2,
3, P / S converters 4, 5, and OR circuits 6, 7, 8, 8
And AND circuits 10 and 11 and an OR circuit 12.

The differentiating circuit 1 receives the two-phase pulse signals PA and PB having a 90 ° phase difference, differentiates the rising and falling edges thereof to generate a quadruple signal, and the phase of the pulse signal PA leads from PB. If so, the pulse signal P is output from the output terminal O _1.
If A is ahead of PB in phase, a quadruple signal is output from the output terminal O ₂ . The counter 2 inputs a 4 × signal from the input terminal U or D via the OR circuits 6 and 7, and upcounts when the 4 × signal is input from the input terminal U, and when it is input from the input terminal D. Count down. The counter 3 inputs the quadruple signal from the input terminal U or D via the OR circuits 8 and 9, and performs the same counter operation as the counter 2. The P / S converters 4 and 5 perform parallel / serial conversion on the count values of the counters 2 and 3, respectively. One of the input terminals of the OR gates 6 and 7 is connected to the mode signal AMODE, the other input terminal is connected to the output terminals O ₁ and O ₂ of the differentiating circuit 1, and the output terminals are connected to the input terminals U and D of the counter 2, respectively. Has been done. One of the input terminals of the OR gates 8 and 9 receives the mode signal BMODE,
The other input terminal is the output terminal O _{1 of} the differentiating circuit ₁ ,
It is connected to O ₂ and its output terminals are connected to the input terminals U and D of the counter 3, respectively. AND circuit 10 is P / S
The output data (serial data) DATAA of the converter 4 and the control signal SENDA are input, and when the control signal SENDA is "1", the output data DATAA of the P / S converter 4 is output. The AND circuit 11 outputs the output data (serial data) DATAB of the P / S converter 5 and the control signal SENDB.
When the control signal SENDB is "1", the output data DATAB of the P / S converter 5 is output. OR circuit 1
2 outputs the data output from the AND circuit 10 or 11 as data DATA to a host controller (not shown). Here, the control signals SENDA and SENDB are
As shown in the figure, first, the control signal SENDA becomes "1" and the data DATAA is output from the OR circuit 12, and then the control signal SENDB becomes "1" and the data DAT.
AB is output from the OR circuit 12.

FIG. 3 shows a chip select signal CS, which generates a differential signal PC 'of the origin signal PC and becomes mode signals AMODE, BMODE.

[Outside 1] Block diagram of the mode signal generation circuit for generating
Differential signal P of phase pulse signals PA, PB and origin signal PC
It is a figure which shows the phase relationship of C '.

In the circuit shown in FIG. 3, the AND circuit 13 that ANDs the two-phase pulse signal PB and the origin signal PC, the two-phase signal PA, the output Q ₁ , the output of the AND circuit 13, and the output Q ₃ are respectively D _1. , D ₂ , D ₃ , and D ₄ inputs to the D flip-flop 14 (LS273) and the D flip-flop 1
Inverters 15 and 16 for inverting the Q ₁ output and the Q ₄ output, respectively, and a NAND circuit 1 for inputting the output of the inverter 15 and the Q ₃ output and Q ₂ output of the D flip-flop 14.
7, a NAND circuit 18 that receives the Q ₃ output of the D flip-flop 14 and the outputs of the inverters 15 and 16, a NAND circuit 19 that inputs and outputs the output of the NAND circuit 17 or 18, and an output of the NAND circuit 19. PC '(differential signal of origin signal) J input (K input is connected to the power supply)
And the chip select signal CS,

[Outside 2] JK type flip-flop 20 (LS109) that outputs
As shown in FIG. 4, the forward rotation direction (C
In W), the differential signal PC 'after rising of the origin signal PC is output from the NAND circuit 18, and in the reverse rotation direction (CCW), the differential signal PC' after falling of the two-phase signal PA is output from the NAND circuit 17, and the JK flip-flop is used. 20 is set, the chip select signal CS,

[Outside 3] Are "1" and "0", respectively. These chip select signals CS,

[Outside 4] As will be described later, the mode signals AMODE, BMOD
It is input as E to the OR circuits 6 and 7 and 8 and 9 shown in FIG. 1, respectively.

In FIG. 1, the two-phase pulse signals PA, P
The illustration of the differential portion for detecting B and the origin signal PC is omitted.

Next, the operation of this embodiment will be described.

FIG. 5 shows three cases in which the count values of the counters 2 and 3 change with time. (1) When only the counter 2 is activated when the incremental encoder is powered on, and the counter 3 is activated when the differential signal PC 'is output (Fig. 5 (1)), in this case, first, the mode signal AMODE is set to OV, and the mode The signal BMODE is the chip select signal CS. When the power is turned on, the counter 2 is activated to start the counting operation. Counter 3 is not activated. When the differential signal PC 'is output, a chip select signal is output as a mode signal BMODE.

[Outside 5] Is input, the counter 3 is activated and the counting operation is started. The counter 2 continues the counting operation. in this case,
The value of the counter 2 indicates the position loop data LOOP, and the value of the counter 3 indicates the position data POS from the origin. These data are parallel / serial converted by the P / S converters 4 and 5, respectively, and then ANDed. It is sent from the OR circuit 12 to the host controller via the circuits 10 and 11. The host controller can recognize the position loop data LOOP, the position data POS, and the deviation of the origin (= LOOP-POS) from the transmitted data. (2) When only the counter 3 is started when the power of the incremental encoder is turned on, and the counter 3 is stopped when the differential signal PC 'is output and the counter 2 is started (Fig. 5 (2)).

In this case, first, the mode signal AMODE is the chip select signal CS and the mode signal BMODE is the

[Outside 6] And When the power is turned on, the counter 3 is activated to start the counting operation. Counter 2 is not activated. When the differential signal PC 'is output, the mode signal AMO
DE is the chip select signal

[Outside 7] , The mode signal BMODE becomes the chip select signal CS, the counter 3 is stopped, and the counter 2 is activated to start the counting operation. In this case, the value when the counter 3 is stopped indicates the deviation of the origin, and the value of the counter 2 indicates the position data POS from the origin, and these data are sent to the host controller in the same manner as in (1). The upper controller can know the position data POS from the origin, the deviation of the origin, and the position loop data (= value when the counter 3 is stopped + position data POS) from the transmitted data. (3) When the power of the incremental encoder is turned on, both counters 2 and 3 are started and the differential signal P
When only counter 3 is stopped when C'is output (Fig. 5 (3)).

In this case, first, the mode signals AMODE, B
Chip select signal for both MODE

[Outside 8] And When the power is turned on, the counters 2 and 3 are both activated to start the counting operation. When the differential signal PC 'is output, only the mode signal BMODE switches to the chip select signal CS and the counter 3 stops. The counter 2 continues the counting operation. In this case, the value of the counter 2 indicates the position loop data LOOP, the value of the counter 3 at the time of the stop indicates the deviation of the origin, and these data are sent to the host controller in the same manner as in the case of (1). The host controller can recognize the position loop data LOOP, the deviation of the origin, and the position data from the origin (= LOOP-deviation of the origin) from the transmitted data.

[0022]

As described above, the present invention has an effect that it is possible to meet the demand for high precision and high speed of transmission characteristics by creating position data by the incremental encoder and sending it to the host controller.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an incremental encoder according to an embodiment of the present invention.

2 is a timing diagram of data output of the block diagram of FIG. 1. FIG.

FIG. 3 is a block diagram of a mode signal generation circuit forming an incremental encoder according to an embodiment of the present invention.

FIG. 4 is a timing diagram of the block diagram of FIG.

FIG. 5 is a diagram showing changes in count values of counters 2 and 3 depending on a combination of mode signals AMODE and BMODE.

[Explanation of symbols]

 1 Differentiation circuit 2,3 Counter 4,5 P / S converter 6,7,8,9 OR circuit 10,11 AND circuit 12,13 OR circuit 14 D-type flip-flop 15,16 Inverter 17,18,19 NAND circuit 20 JK type flip-flops

Claims (4)

[Claims] 1. An incremental encoder for detecting a pulse signal of a first phase and a second phase and one origin signal with rotation and inputting a pulse signal of the first phase and a second phase, and rising thereof. And a falling edge are differentiated to generate a quadruple-multiplied signal, and the quadruple-multiplied signal is output from the first output terminal or the second output terminal in accordance with the phase relationship between the first-phase pulse signal and the second-phase pulse signal. A differentiating circuit for outputting and a quadruple multiplied signal outputted from the first and second output terminals of the differentiating circuit are inputted respectively from the first and second input terminals, and the quadruple multiplied signal is inputted from the first input terminal. First and second counters that up-count the 4-multiplied signal when input, and down-count the 4-multiplied signal when the 4-multiplied signal is input from the second input terminal, respectively. First, second
The first and second P / S converters for parallel / serial conversion of the count value of the counter, and the serial data output circuit for sequentially outputting the serial outputs of the first and second P / S converters, A first gate circuit provided between the differentiating circuit and the first counter for permitting / inhibiting the input of the quadruple multiplied signal to the first counter by a first mode signal; the differentiating circuit and the second gate circuit. A second gate circuit provided between the counters for permitting / inhibiting the input of the 4 × signal to the second counter by the second mode signal, and the first and second mode signals by the origin signal. A data output type incremental encoder having a mode signal generation circuit for generating the generated mode signal. 2. The incremental according to claim 1, wherein the first and second mode signals continue the operation of one counter during the counting operation and activate the other counter which is stopping the counting operation. Encoder. 3. The incremental according to claim 1, wherein the first and second mode signals stop the operation of one counter during the counting operation and activate the other counter during which the counting operation is stopped. Encoder. 4. The incremental according to claim 1, wherein the first and second mode signals both continue the operation of one of the two counters during the counting operation and stop the operation of the other counter. Encoder.