JPS6243195B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an improved scroll-up scheme for display devices.

A display device for a terminal of an electronic computer includes a display means having a display screen in which unit display blocks for displaying input data are arranged in multiple rows in a matrix, and each unit for temporarily storing a code signal representing the data. A storage means having a plurality of unit storage blocks each corresponding to a display block is essential. However, in this type of display device, the screen is displayed to the fullest,
Furthermore, when there are no more lines to be displayed, an operation called scroll-up is performed in which each line is moved up one line at a time and new data is displayed on the empty bottom line.

However, with the conventional scroll-up method,
As the displayed data is scrolled up, the code signal stored in the storage means is
Since the memory correction was performed on the unit memory block group of the corresponding upper row so as to advance the display data by one row, it took a long time to edit the display data. Therefore, it was not very good in terms of operability.

In view of the above, the present invention provides a new scroll-up method that eliminates the need for memory modification operations on the storage means and allows display data to be edited in a short time. Briefly stated, the scroll-up method of the display device of the present invention comprises a display section consisting of a gas discharge display panel with a memory function and a display screen in which unit display blocks are arranged in multiple rows in a matrix, and a character code representing input data. a storage unit having a plurality of unit storage blocks corresponding to the unit display blocks for storing signals; and a head address pointer that always indicates the address of the unit storage block corresponding to the first unit display block in the top row of the display screen. and a microprocessor-configured display control section comprising space data supply means for applying a code signal representing a space to each block of the unit storage block group corresponding to the unit display block group for one line, and After writing the input data to be displayed to the unit display block group belonging to the lowest row of the display, write the input data to the head address pointer to perform a scroll-up operation to advance the displayed data one row at a time. an operation of adding address contents for one line; and an operation of driving the space data supply means to apply the space code signal to a group of unit storage blocks corresponding to a group of unit display blocks in the top row to store it; Based on the address correction of the head address pointer, the data corresponding to the storage code signal of the unit storage block group is first written to the lowest row of the display screen, and then the character code signal is written from the lowest row. This method is characterized in that writing operations are added in order from one higher row to the highest row.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a system diagram of a display device for displaying characters to explain the scroll-up method of the present invention. This device is mainly composed of a data input section 1, a display control section 2, a display drive section 3, and a display section 4. The display unit 4 uses a conventionally well-known gas discharge display panel for matrix address display with a memory function (hereinafter referred to as matrix PDP), and the display screen of the PDP is 80 mm as shown in the figure.
(column) x 24 (row) = 1920 character display block AD ₁
~AD ₁₉₂₀ , and 1920 cursor display blocks _CD1 ~ _CD1920 adjacent to the lower sides of these display blocks. Also, the unit character display block is 5×
It has a 7-dot picture element configuration, and the unit cursor display block has a linear 5-dot picture element configuration.

The display drive section 3 has control functions for writing and erasing characters, writing cursors, erasing lines, and erasing the entire screen, and displays each of the selected characters and cursor according to the selected function mode. a plurality of address drivers for applying write or erase signals to the blocks;
and a character pattern generator for applying a character pattern signal to be written to the driver.

On the other hand, the data input section 1 has a keyboard 11 and a connection terminal 12 for an external computer. The display control section 2 uses a microprocessor, and sends a function mode selection signal, a display block address signal, a character code signal, etc. to the drive section 3 according to the character data from the data input section 1. By supplying this signal, display operations can be performed on the matrix PDP 4. in particular,
A central processing unit (hereinafter referred to as CPU) 21, a program memory 22, a frame memory 23, and a work area memory connected to it via a 16-bit address bus AB, an 8-bit data bus DB, and a control bus CB. 24, stack memory 25, interface 2 for data input section
6, 27, interface 28 for display drive unit,
29 and space data supply means 30. The CPU 21, program memory 22
Since the interfaces 26 and 27 are well known in the art, their explanation will be omitted here. The frame memory 2
3, as shown in FIG. 2a, a plurality of storage areas MA ₁ to MA corresponding to character display block groups for each line on the display screen of the PDP 4 (hereinafter referred to as character display areas CA ₁ to CA ₂₄ ), respectively. ₂₄ , and these storage areas store unit character display block groups of each character display area according to their arrangement order.
Unit memory block groups MAD ₁ , MAD _{2 .} . . MAD ₈₀ associated with AD ₁ , AD _{2 .} . . AD ₈₀ are included, respectively. Character code signals are normally stored in these memory blocks in an 8-bit configuration.

The work area memory 24 is for temporarily storing work contents according to the program, and has a plurality of storage areas MB ₁ to MB _o of 8-bit configuration as shown in FIG. 2b. For example, address 0 and 1
The address storage areas MB ₁ to _{MB 2} contain code signals that specify the column and row addresses of the cursor display.
The memory areas MB ₃ and MB 4 at addresses _{4 and 3} contain code signals for specifying the column and row addresses of the scroll display, and the memory areas MB 5 and ₅ at addresses 4 and 5 contain code signals for specifying column and row addresses for scroll display.
MB ₆ stores 2 bytes of 16-bit address data that specifies the system address of the unit storage block MAD ₁ corresponding to the first unit character display block AD ₁ of the top row on the display screen. It is becoming more and more like this. Note that the storage areas MB ₅ and MB ₆ are hereinafter collectively referred to as address pointers. The address specification order for the cursor display is (1.1), (2..
1)......(80・24) is added sequentially, which means (80・24), that is, the unit cursor display block CD ₁₉₂₀ in the last column of the lowest row is specified, and then character data is added. When inputted, the program memory 22 and CPU 21 are set to start the scroll up operation. Further, this cursor address code signal is used as an address signal when writing and erasing characters to the selected unit character display block and erasing the selected row. On the other hand, the address specification order for scroll display is first set to (80/23) by the scroll up execution data from the CPU, and then (79/23), (78/23), etc. according to the subsequent input data. …
It is designed to be subtracted sequentially like (1.1). Therefore, during the scroll up operation, display data is reproduced starting from the lowest line before the line break (scroll up).

Further, the addressing order of the head address pointer is initially set to the value of the address on the system indicating the first unit storage block _{MAD 1 of} the highest storage area MA ₁ , and thereafter as the scroll up is executed, Address on the system showing MAD ₁₆₁ ...MAD ₁₈₄₁
The address is added one line at a time, like the address in . It should be noted that other storage areas of the work area memory 24 normally store various work contents in addition to the address work, but since these are not related to the essence of the present invention, their explanations are omitted.

The stack memory 25 is used to temporarily store data associated with interrupts or subroutine calls. The interface 28 is used to specify the unit character to be selected and the cursor display block or character display area on the screen of the PDP 4, and is used to input the 7-bit column address signal PAX and the 5-bit row address signal PAY. It is supplied to the address driver in the display drive section 3. Further, the interface 29 is
Function mode selection signal for display driver 3
It outputs OMS, a character code signal CCS, and a strobe signal STB to ensure data exchange, and also receives a busy signal BUSY from the drive section to indicate that it is in operation.

Therefore, the space data supply means 30
is for supplying a code signal representing a space to one storage area selected when scrolling up, and as shown in the detailed diagram of FIG. , a flip-flop circuit 304, a clock generator 305, and two multiplexers 306 and 307. The decoder 3
01 is a pulse signal from output terminals a and b in response to a scroll up command signal from the CPU 21 applied through a 16-bit address bus AB.
CS ₁ and CS ₂ are output sequentially. The latch circuit 30
2 is activated in response to the pulse signal _CS1 from the decoder, and temporarily stores the address contents (16-bit configuration) of the head address pointer at that time through the data bus DB of 8-bit configuration. In this case, the contents of the head address pointer are latched twice by the signal _CS1 . That is, the first access latches the upper 8 bits, and the second access latches the lower 8 bits.

The counter 303 is an octal counter, and when the pulse signal CS ₂ from the decoder 301 is input to the load terminal L, the latch circuit 302 outputs 16
When a bit memory output is loaded and a pulse signal is input to the enable terminal EN, the counting operation of the memory output is started, and when 80 pulse outputs from the clock generator 305 are input, a pulse signal RPS is output. I'm starting to do that. The flip-flop circuit 304 is of the R-S type, and when the pulse signal _CS2 of the decoder 301 is input to the set terminal S, an "H" level signal QS is output from the Q terminal.
is output to the enable terminal of the counter 303.
EN and multiplexers 306 and 307 described below
are applied to the selected terminals of respectively. This also means that the pulse output of the counter 303 is connected to the reset terminal R.
When RPS is received, the circuit is reset and the output of the Q terminal becomes "L" level.

Regarding the multiplexers 306 and 307, when receiving the "H" level signal QS, the multiplexer 306 takes out an 8-bit SP code signal (or NULL code signal) representing a space from the output terminal, and otherwise outputs an 8-bit SP code signal (or NULL code signal) from the CPU 21. extract the data signal. Further, 307 takes out the count output of the counter 303 when the "H" level signal QS is input, and when it is not input, the CPU 21
Takes out the address signal. The respective outputs of these multiplexers are supplied to the frame memory 23, and in particular, when supplying the SP code signal and the counter output, the unit in one selected storage area in the frame memory is a feature of the present invention. The above SP is sequentially applied to the memory block group.
A code signal storage operation will be performed.

In the above-described configuration, a normal character writing operation is performed according to the flowchart shown in FIG. That is, first, in step A shown in FIG.
The CPU 21 alternately and sequentially repeats data input confirmation checks on both the interfaces 26 and 27. At this time, if a command indicating character writing is received from the keyboard 11, the data is taken into the CPU 21 in the next step B. Next, in step C, the CPU 21 decodes what the data means, and in the next step D, determines whether it is character writing. When character writing is confirmed, the CPU 21 reads the contents of the column address of the cursor and determines whether the contents are (80). If NO,
In the next step F, first, the column and row address contents of the cursor in the storage areas MB ₁ and MB ₂ at addresses 0 and 1 of the work area memory 24, for example (2.23), are read into the CPU 21, and
The character data (code signal) is stored in a selected storage block of the frame memory 23, for example MAD ₁₇₆₂ . As a result, the address signals PAX and PAY based on the address contents of the cursor are supplied to the address driver of the display driving section 3, and the code signal is supplied to the character pattern generator, respectively. The cursor in any previously displayed cursor display block, e.g. CD _1762, is erased, and then the desired cursor in the character display block _e.g.
Characters consisting of ×7 dot picture elements are displayed. After that, the CPU 21 controls the work area memory 2.
Only the column address contents in PDP 4 are incremented by 1, and this address contents are read again into the CPU, and an address signal based on the contents is used to display the next cursor display block on the screen of the PDP 4, for example, CD _1763.
A cursor consisting of 5 dots is displayed. In this case, the display driver 3 is driven by a strobe signal.
This is performed according to the subroutine (out STB) shown in FIG. 4b using STB and the busy signal BUSY.
That is, first, it is checked whether or not the drive section is in operation, and if it is not in operation, a strobe signal is set. After the drive unit 3 is operated in this way, the working status is checked again in the next step, and if it is working, the strobe signal is reset and the process returns to the main program. From this point on, the display control section 2 enters the next data control mode, and the step A
Return to

On the other hand, if the content of the column address of the cursor is determined to be (80) in step E, then in the next step G, the CPU 21 reads the row address of the cursor and determines whether it is (24) or not. . In other words, it determines whether the cursor position corresponds to the display block CD ₁₉₂₀ in the last column of the lowest row. If it is NO, it performs the normal automatic line feed operation, and if it is YES, it performs the following process. Display data is scrolled up according to such operations.

That is, Fig. 5 shows the flowchart of the operation when the cursor is positioned at the display block CD ₁₉₂₀ in the last column of the lowest row and character data is input, that is, when automatic line feed occurs due to scroll up.
It consists of steps (A) to (d). Note that the address of the head address pointer is the highest storage area.
It is assumed that this is the address value on the system corresponding to the first storage block MAD ₁ in MA ₁ .

(A) The CPU 21 reads the address content of the cursor and outputs an address signal based on the content to the address driver in the display drive unit 3.

(B) The CPU 21 reads out the input and temporarily stored code signal of the character data from the corresponding storage block MAD ₁₉₂₀ of the frame memory 23, and outputs it to the character pattern generator of the display driving section 3 via the interface 29.

(C) Set the display control unit 2 to character writing function mode.

(D) Execute the subroutine (out STB) shown in FIG. 4b. As a result, the character display block AD ₁₉₂₀ on the PDP4 is
The desired letter "T" is displayed. This display mode is shown in FIGS. 1-1 and 1-2.

(E) In response to the scroll up command signal from the CPU 21, the decoder 301 first outputs a pulse signal CS ₁
As a result, the address contents of the head address pointer (address on the system of MAD ₁ ) to be cleared are stored in the latch circuit 302.

(F) Similarly, the decoder 301 outputs a pulse signal _CS2 in response to the scroll up command signal. As a result, the flip-flop circuit 304
is set and a “H” level signal is output from the Q terminal.
Output QS. On the other hand, the counter 303 receives these two outputs and starts a counting operation based on the contents stored in the latch circuit 302. At the same time, one multiplexer 306 periodically outputs the SP code signal and the other multiplexer 307 periodically outputs the counted output of the counter 303 to the storage area MA of the frame memory 23 according to the "H" level signal QS. ₁ to each memory block MAD ₁ to MAD ₈₀ . At this time, since the frame memory 23 is set to the write mode, the SP code signal is sequentially stored in each block of the storage block group.

When the counter 303 receives 80 clock pulses, it generates a pulse output RPS and applies it to the reset terminal R of the flip-flop circuit 304. As a result, the output state of the Q terminal becomes "L" level, and the pulse output RPS is applied to the reset terminal R of the flip-flop circuit 304.
6, 307 is returned to its original state so that the signal from the CPU 21 is supplied to the frame memory 23. Thus, the storage operation of the SP code signal in one selected storage area of the frame memory 23 is completed.

(G) Add 80 (decimal) to the address contents of the head address pointer in the work area memory 24.
As a result, this becomes the address on the system corresponding to memory block MAD ₈₁ , and the memory area MA ₂ on the second line becomes the character display area on the display screen.
Corresponding to CA ₁ , MA ₃ corresponds to CA ₂ , and MA ₄ corresponds to
CA ₃ ...MA ₁ will be associated with CA ₂₄ .

(H) The CPU 21 specifies that the address content of the head address pointer is the last address LFM (memory block) of the frame memory allocated within the CPU.
(address on the system corresponding to MAD ₁₈₄₁ ). If it is larger, proceed to step (I) and set the address contents to the first address IFM (address on the system corresponding to memory block MAD ₁ ), but in this embodiment, as described above, it is initially set to (memory block MAD 1).
Since the address on the system corresponding to MAD ₁ is set, proceed to the next step (J).

(J) Set the address content of the cursor in the work area memory 24 to (1.24) corresponding to the first column of the lowest row (display block CD ₁₈₄₁ ).

(k) The CPU 21 reads the contents of the cursor address and outputs an address signal based on the contents to the display driving section 3.

(L) Set the display control section 2 to the line erasing function mode.

(M) Execute the subroutine shown in FIG. 4b again. As a result, in connection with steps (k) and (L), all display data in the character display area CA ₂₄ of the lowest row on the display screen is erased. This display mode is shown in FIG. 6 2-1.

(N) Set the display control section 2 to the cursor writing function mode.

(O) Execute the subroutine again. As a result, the cursor display block on the display screen is changed in relation to steps (k) and (N).
A cursor will appear on CD ₁₈₄₁ . FIG. 6 3-1 shows this display mode.

(P) Addressing the storage area MA _{23 of the frame memory 23} to the start position;
Thereafter, an index register (not shown) in the CPU 21 is controlled so that the addresses are sequentially addressed as MA ₂₂ . . . MA ₁ .

(Q) Set the scroll column and row address contents in the storage areas MB ₃ and MB ₄ at addresses 2 and 3 of the work area memory 24 to (80·23).

(R) Set the display control section 2 to the line erasing function mode.

(S) Execute the subroutine shown in FIG. 4b again. As a result, the address signal based on the row address content of the scroll causes the display driving section 3 to erase all display data in the character display area CA ₂₃ on the 23rd line on the screen of the PDP 4. This display mode is shown in FIG. 6 4-1.

(T) The CPU 21 reads the scroll column address contents and outputs an address signal based on the contents to the address driver of the display drive section 3.

(U) The CPU 21 takes out the character code signal in the memory block MAD ₁₈₄₀ of the frame memory 23 and inputs it to the character pattern generator of the drive unit 3 via the interface 29.

(V) Set the display control section 2 to the character writing function mode.

(W) Execute the subroutine again. As a result, in relation to steps (T) and (U), the character display block on the screen of the PDP4 is
AD ₁₈₄₀ will display characters corresponding to the character code. In other words, the characters displayed in the character display block AD ₁₉₂₀ before the scroll up operation are displayed in the display block one line above.
It was recreated in AD ₁₈₄₀ . This display mode is shown in FIG. 6, 4-2.

(X) The CPU 21 reads the address contents of the scroll column and determines whether it is (1) or not.
If NO, proceed to the next steps (Y) and (Z); if YES, proceed to steps (A) to (D).

(Y) Decrement the address content of the scroll column in the work area memory 24 by -1.

(Z) Decreases the memory contents of the column of the index register by 1. And the step (T)
Steps (T) to (W) are then repeated until the determination result in step (V) becomes YES. In short, by this step, PDP4
In each character display block group on the 23rd line above
Display data will be reproduced in the order of AD ₁₈₃₉ , AD ₁₈₃₈ ...AD ₁₇₆₁ . This display mode is shown in Figure 64.
-3.

(b) Decrease the memory contents related to the row of the index register by 1.

(b) The CPU 24 reads the content of the scroll line address and determines whether it is (1) or not. NO.
If YES, proceed to the next steps (c) and (d); if YES, return to the character writing routine shown in FIG. 4a.

(c) Decrease the contents of the scroll line address in the work area memory 24 by 1. As a result, the content becomes (22).

(d) Set the scroll column address contents in the work area memory 24 to (80). Then, return to step (R), and then proceed to step (R).
-(d) are repeated until the judgment result in step (b) becomes YES. In short, by this step, display data is reproduced in the order of CA ₂₂ , CA ₂₁ . . . CA ₁ for each of the remaining lines on the display screen of the PDP 4. This display mode is shown in Figure 6.4.
-4.

Thereafter, the address contents of the head address pointer are sequentially added one line at a time for each scroll up command, and the above operation is repeated based on the corrected address contents. Thus,
A scroll-up operation of the displayed data will be accomplished.

As is clear from the above description, the present invention eliminates the memory correction operation for the storage means when scrolling up display data, and also provides space for one line of selected storage area that requires rewriting in the storage means. Since a data supply means is provided, there is an advantage that the display data can be edited in a very short time. Therefore,
Operability can be significantly improved. Also, since the display data is reproduced in the order from the data displayed in the bottom row to the display data in the top row,
There is an advantage that when the display is scrolled up due to data rewriting, the contents of the newly displayed data can be understood more quickly. Therefore, it would be extremely advantageous to apply the present invention to a display device for a terminal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a character display display device for explaining the present invention, FIG. 2 is a diagram showing an example configuration of the frame memory and work area memory in FIG. 1, and FIG. An example configuration diagram of the space data supply means in the figure, FIG.
FIG. 5 is a flowchart for explaining the character writing operation of the device shown in the figure; FIG. 5 is a flowchart for explaining the scroll-up operation of the present invention; FIG. It is a diagram. 1: Data input section, 2: Display control section, 3: Display drive section, 4: Matrix PDP, 11: Keyboard, 21: CPU, 22-25: Memory, 26-2
9: Interface, 30: Space data supply means, CA ₁ ...: Unit character display area, AD ₁ ...
...: Unit character display block, CA ₁ ...: Unit storage area, MAD ₁ ...: Unit storage block, CD ₁ ...
...: Unit cursor display block, 301: Decoder, 302: Latch circuit, 303: Counter, 3
04: flip-flop circuit, 305: clock generator, 306 and 307: multiplexer.

Claims (1)

[Claims] 1. A display section consisting of a gas discharge display panel with a memory function having a display screen in which unit display blocks are arranged in multiple rows in a matrix, and a unit memory corresponding to each of these unit display blocks to store character code signals representing input data. A storage unit having a plurality of blocks, a head address pointer that always indicates the address of the unit storage block corresponding to the first unit display block of the top row on the display screen, and a unit storage block corresponding to a group of unit display blocks for one line. a microprocessor-configured display control section comprising space data supply means for applying a code signal representing a space to each block in the group; After writing the required input data, change the displayed data to 1
In order to perform a scroll-up operation that moves forward one line at a time, the contents of the address are added by one line to the head address pointer, and the space data supply means is driven to correspond to the unit display block group of the topmost line. Based on the operation of applying and storing the space code signal to the unit storage block group and the address correction of the head address pointer, the data corresponding to the storage code signal of the unit storage block group is first converted into data corresponding to the space code signal. A scroll-up method for a display device characterized by writing a character code signal on the lowest line of a display screen, and then adding a character code signal in order from the lowest line to the highest line.