JPS63835B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention obtains data in a first storage device using the address portion of a write address to a second storage device, and transfers the data to a second storage device designated by the write address. This invention relates to a data writing method for writing to a storage device.

(2) Background of the Invention Conventionally, in a graphic processing device, the graphics are created using dot patterns, and the processing includes image data processing, fixed pattern processing, painting processing, and the like. The dot pattern creation method in these processes has been a relative address write control method, but this has the following drawbacks, and a method for improving these is desired.

(3) Prior art and problems In other words, the above method is capable of image data processing and fixed pattern processing, but if you want to paint the image memory with the same repeating pattern, you need to change the data processing from relative address processing to absolute address processing. It is necessary to move on to address processing, which has conventionally been done through editing of painting data. Therefore, the processing time becomes long, and as a result, the display speed inevitably decreases.

(4) Purpose of the Invention The present invention was devised in view of the drawbacks of the data processing method as described above, and its purpose is to write data from a first storage device to a second storage device at high speed. The purpose is to provide a method.

(5) Structure of the Invention The object is to retrieve data specified by a predetermined address part of a write address for data to be written to a second storage device from a first storage device, and This is accomplished by storing the data in the second storage device specified by the write address.

(6) Embodiments of the invention Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.

FIG. 1 shows an image processing apparatus implementing the present invention. Reference numeral 1 denotes an image memory (second storage device), which is a painting data memory (first storage device) that stores image data sent from a main processing unit (not shown) or painting data in advance.
2 under the control of the main processing unit, and stores dot patterns in matrix format. 3 is a control logic circuit connected to the above-mentioned main processing unit via an interface 4, and this control logic circuit 3 is controlled by the main processing unit to include a command status register 5, an address counter 6, a length counter 7, and a length register 8. , and controls the counting operations of counters 6 and 7. These counters are also configured so that their counting operations are controlled by a write control circuit 9, which will be described later. Further, under the control of the control logic circuit 3, the painting data in the painting data memory 2 or the data sent from the main processing unit is placed in the dot pattern data register 10. The memory contents of one line of the memory 2 are placed in the register 10.

Reference numeral 11 denotes a comparison circuit connected to the outputs of the length counter 7 and length register 8. These counter 7, register 8, and comparison circuit 11 are used to determine the end point determined by the length. Not too much.

A write control circuit 9 is connected to the command status register 5 and the comparison circuit 11 and performs write control.

A multiplexer 12 is selectively switched under the control of the write control circuit 9 and supplies an address from the address counter 6 or the display control circuit 13 to the addressing section of the image memory 1.

A multiplexer 14 selectively supplies the contents of the address counter 6 or length counter 7 to the multiplexer 16 in response to a signal on the relative-absolute switching signal line 15 from the command status register 5. Multiplexer 16 responds to the address value from multiplexer 14 to register 1
This is for supplying a desired bit (data portion) of 0 to the image memory 1. This bit is written to the storage location of the image memory 1 specified by the address from the address counter 6 under the control of a control signal on the control line 17 from the write control circuit 9.

A video signal generating circuit 18 converts the image data read out from the image memory 1 into a video signal under the control of the display control circuit 13 and supplies it to the cathode ray tube 19.

The present invention will be explained through a description of an image processing apparatus configured as described above. For convenience of explanation, the first storage device (painting data memory) 2 is 16×16
It is assumed that the second storage device (image memory) 1 has a plurality of 16×16 bit storage areas for storing bit painting data.

Now, a decision is made in the main processing unit that the image processing system should paint a part of the image memory 1 using the contents of the painting data memory 2 in an absolute address writing format. Assume that it is desired to paint a partial triangular area ABC of the image memory 1 with the contents (bit pattern) of the painting data memory 2 as shown in FIG. In this determination, the addresses of the three points (A), (B), and (C) of the triangle are determined, and the length L is determined from the difference between the points (A) and (B). The update value of is also determined, and the update value of the address pointer (initially the address of point (A)) and length L are also determined.

Thereafter, a command representing the determination of the write mode is sent from the main processing unit to the control logic circuit 3 via the interface 4. This command includes a command code indicating writing in absolute address writing format, a length, and the address of point A (address pointer). From the control logic circuit, an address pointer (address of point A) is set in the address counter 6, a length is set in the length register 8, and a command status register 5 is set.
If the command code is set and the status of the register 5 indicates that the write control circuit 9 is ready for writing, this will cause the write control circuit 9 to be activated and the relative-to-absolute switching signal 15 will cause the multiplexer 14 to be activated. is switched to the absolute address writing mode. That is, the address is set so that the addresses from the address indicated by the lower 4 bits of the address pointer set in the address counter 6 to the address ahead by the length counted by the length counter 7 are sent out one after another.

Correspondingly, the bit pattern for one row of the memory 2 to which the address indicated by the lower four bits of the address pointer entered in the address counter 6 belongs is read out from the memory 2, and the address of the dot pattern is stored in the dot pattern data register 10. and is set.

Thereafter, first, the address indicated by the lower four bits of the address pointer is output from the multiplexer 14, and the bits of the register 10 specified by the address are output from the multiplexer 16. This bit is the bit that should be written to point A in FIG.
is written to the storage location in the image memory 1 specified by the address pointer.

Such a write operation is continued while updating the values of the address counter 6 and length counter 7 one bit at a time until an address specified by the length counter 7, that is, an output signal is generated from the comparison circuit 11. Regarding this in Figure 2, the address pointer specifies (P ₁₁ ),
Each time 1 bit is stored, P ₁₂ and P ₁₃ in Figure 2
...The writing progresses to P ₁₆ . When the next address is updated by 1 bit, the lower 4 bits have been changed to an address specifying _P1 of the bit pattern being read into the register 10.
In this way, the bit pattern of the register 10 is written into the image memory 1. Again _P16
is reached, but the next operation is repeated in the same way. In the above example, the painting process for the bit pattern set in the register 10 is completed at a position advanced by a length from the address pointer, which is 24 (P ₁₁ . . . P ₃ ) in the above example.

In response, the control logic circuit sends the address pointer a new address pointer (in FIG. 2) updated by the update value determined as described above.
A (address indicating _one point) is set in the address counter 6, and at the same time, a new length is set in the length register 8, with the length updated by the update value determined as described above. In addition, one row of the memory 2 to which the address represented by the lower four bits of the new address pointer entered in the address counter 6 belongs is read out to the register 10.

After these settings are made, the same process as the painting process for the lowest row of triangle ABC in FIG. 2 described above is performed.

The painting process for each row is repeated as described above, and when the apex C of the triangle is reached, the painting process for the above-mentioned triangle ABC in the image memory 1 based on the contents of the painting data memory 2 is completed.

As described above, by performing the painting process using the present invention, there is no need for conventional data editing process during the painting process, so the painting process to the image memory can be completed in a short time. This increases the speed and contributes to improving the display speed.

In addition, the image display system is switched to the same type of relative address writing mode as before under the control of the main processing unit,
When it is desired to paint the image memory 1 with the contents of the painting data memory 2 under this operation mode, the difference from the above-mentioned absolute address write control mode is to specify switching to the relative address write control mode in the command status register 5. A command code is placed and a signal indicating this is sent via line 15 to multiplexer 14, which in turn applies the contents of length counter 7 to multiplexer 16, which in turn outputs the dot pattern set as described above. data register 1
The purpose is to select and output the bits specified by the lower 4 bits of the above content within one line of 0's.
Therefore, the only difference in hardware is the control system that causes this difference, and the other components are common to both the above-mentioned embodiments.

Further, image data processing and fixed pattern processing other than this can be processed in the above-mentioned hardware.

In the above embodiment, the address pointer (write address) set in the address counter
Although we have described an example in which the lower 4 bits of the write address are used, for example, the higher 4 bits next to the lower 4 bits of the write address are used to transfer each of the bit strings in the first storage device 2 to the second storage device 1. It may also be configured to write. Therefore, the term data portion in this specification means one bit or a bit string.

(7) Effects of the invention As is clear from the above explanation, the following effects can be obtained according to the present invention.

(1) Transfer the data of the first storage device specified by the address part of the write address for the second storage device to the second storage device specified by the write address.
It is possible to write to a storage location in a storage device.

(2) Since the writing in (1) does not require any data editing operation, the writing speed can be increased.

(3) Therefore, data can be used from the second storage device within a short time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining writing of data to a partial storage area of the image memory shown in FIG. In the figure, 1 is the second storage device (image memory), 2
is a first storage device, 3 is a control logic circuit, 5 is a command status register, 6 is an address counter,
7 is the length counter, 8 is the length register,
9 is a write control circuit, 10 is a dot pattern data register, 11 is a comparison circuit, 12, 14, 16
is a multiplexer.

Claims (1)

[Scope of Claims] 1. In a data writing method for writing data from a first storage device to a second storage device, a predetermined address among write addresses for data to be written to the second storage device Data specified by the address portion is retrieved from the first storage device, and the data is written to a storage location of the second storage device specified by the write address. Writing method. 2 The data written to the second storage device is generated from the lower address portion of the address pointer of the write address placed in the buffer from the first storage device, and is generated from the lower address portion of the row data to which the address belongs. It consists of data portions designated by addresses sequentially generated by incrementing the configuration bits from the address generated in the lower address portion, each of the data portions starting from the address pointer of the incremented write address. 2. The data write method according to claim 1, wherein data is written sequentially up to a write address that is larger by a length that specifies a range to be written. 3. The data writing method according to claim 2, wherein the address pointer and length are changed by a predetermined update value to perform the same processing on the data as described above. 4. The data writing method according to claim 1, 2, or 3, wherein the data portion is a bit.