JPS6243210B2 - - Google Patents

Description

[Detailed Description of the Invention] For example, when operating the push buttons on the operation panel of a measurement control system, if multiple buttons are pressed at the same time, multiple ON signals are input at the same time, disrupting the sequence. The present invention relates to an instantaneous digital input circuit system in which only one signal is turned on and all others are turned off.

Figure 1 is a block diagram of a conventional instantaneous input type digital input circuit system when input data is 16 bits. In the figure, S ₁ to _{S 16} are momentary switches, d ₁ to _{d 16} are differentiating circuits, 1, G ₁ to _{G 16} are OR circuits, M ₁ to _{M 16} are memories (RS-FF), D ₁ to D ₁₆ are open collector drivers (NAND circuits), 2 is a delay circuit, 3 is a read signal input terminal, and Vcc is It is a positive DC power source. Figure 2 is a time chart of the method shown in Figure 1, where A is the pulse signal when the momentary switch _S3 is turned on, B is the pulse signal from the differentiating circuit _d3 , and C is the pulse signal when the momentary switch _S8 is turned on. , D is the pulse signal from the differentiating circuit d ₈ , E is the output of Q of memory M ₃ , F is the output of memory M ₈
, G is the read signal, H is the memory reset signal, A is the momentary switch S ₃ is turned off and then S ₈ is turned on, B is the momentary switch S ₃ and S ₈ are turned on at the same time. Indicates the case of aging. First, the case shown in FIG. 2A will be explained. For example, as shown in A, when the momentary switch _S3 is turned on, the differentiating circuit _d3 switches to B at the fall of this pulse signal.
A pulse signal is generated as shown in the figure. Due to this pulse signal, the output of OR circuit _G3 becomes “0” and the memory
The Q output of M ₃ becomes 1 as shown in E. Further, "1" is inputted to OR circuits G ₁ to _{G 16} via OR circuit 1. Next, as an example, even if the momentary switch _S8 is turned on as shown in C, since 1 is added to the OR circuit _G8 from the output of the OR circuit 1, the memory _M8 is not set (Q is set to 1). (Here, the differential circuit d ₁
~ _d16 is provided to prevent the memory output from becoming 1 again even if the memory output is reset while the momentary switch is on. ) Next, data is output from the open collector drivers D ₁ to D ₁₆ by the read signal shown at G.
At this time, only the open collector driver _D3 is "1" and all others are "0". Also, the read signal is sent to the memories M ₁ to _{M 16} via the delay circuit 2 and reset after outputting the data (memories M ₁ to _{M 16}
Q output becomes "0"), and a new input signal can be input. However, as shown in the part (b) of Figure 2, when two or more input signals are turned on at the same time [differential circuit (d ₁ to _{d 16} ), OR circuit (G ₁ to _{G 16} , memory (M ₁ to M ₁₆ ) , during the transmission time of the OR circuit 1] In this explanation, when the momentary switches S ₃ and S ₈ are turned on at the same time, the memory M ₃ is turned on as shown in E and F.
When the output of Q of ~ _M8 becomes 1 and data is output from open collector drivers _D1 to _D16 , the output of open collector drivers _D3 to _D8 becomes 1,
In the case of a measurement control system, etc., where only one signal does not become 1, there is a drawback that the sequence is confused.

The object of the present invention is to provide an instantaneous input type digital input circuit system in which only one bit is always turned on at the output even if multiple bits are turned on at the same time among N bits of input data, in order to eliminate the above-mentioned drawbacks. It is provided by.

In order to achieve the above object, the present invention converts N bits of data input in parallel into serial data in a parallel-to-serial converter, detects which bits are turned on bit by bit, and detects which bits are turned on first. This is an instantaneous input type digital input circuit system that is characterized in that all serial data after detecting a bit that is OFF is transferred to a serial/parallel converter and output as parallel data.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of an instantaneous input type digital input circuit system when the input data is 16 bits in one embodiment of the present invention. In the figure, the same functions as in FIG. Parallel-to-serial conversion shift register, SR2 is a serial-to-parallel conversion shift register, FF1 is a delay type flip-flop, FF2 is a set-reset flip-flop, 4, 11, 12
5 and 8 are AND circuits, 5 and 8 are delay circuits, 6 is a clock control circuit, 7 is a pulse generator, 9 is a differential circuit, 10 is an OR circuit, and a to d each position for explanation. Also, Figure 4 is the time chart of Figure 3.
B is the pulse signal when momentary switches S ₃ and S ₈ are turned on at the same time (hereinafter referred to as S 3 and S ₈ ), C is the pulse signal when momentary switches S ₃ and S 8 are turned on at the same time
Q output signal of FF2, D is the signal at point d, E is a
The signal at point B goes to the set signal of SR1.
16 clock pulses, SR1 internal signal,
H is the output signal of SR1, R is the output signal of FF1, N is the internal signal of SR2, L is the read signal, and O is the signal at point C, that is, the reset signal. If the momentary switches S ₃ and S ₈ are turned on at the same time, the signals S ₃ and S ₈ will be generated as shown in A and B. This signal is input to the OR circuit 10 at the same time as it is input to the shift register SR1. The output of the OR circuit 10 is branched into two branches, one of which is input to a differentiating circuit 9 that detects the fall of the signal, and becomes a set signal for the shift register SR1 as shown in E. This set signal causes the input data to be shifted into the register as shown in the figure below.
Set within SR1. The other signal is delayed by the delay circuit 8 (for the time required for the input data to be stored in the shift register SR1), and the Q of the reset flip-flop FF2 is inverted as shown in FIG. [C shows only the output of Q] The reset flip-flop FF2 is connected to the shift register SR1,
SR2 is a circuit that controls the clock output for operating the delay type flip-flop FF1, sets the reset flip-flop FF2 to "0", and blocks input signals until the input signals are output from the drivers _D1 to _D16 . When the reset flip-flop FF2 operates, the clock control circuit 6 operates to generate 16 clock signals as shown in FIG.
This clock signal is used by shift registers SR1 and SR.
2. Serves as a clock for delay type flip-flop FF1. The shift register is controlled by this clock signal.
The input data stored in SR1 is serially output as shown in H. In this case, only S ₃ and S ₈ are on signals. When the delay type flip-flop FF1 first detects _S3 , the signal is inverted as shown in (R), and the AND circuit ₄ sets S4 and subsequent signals to "0" and transfers them to the shift register SR2. Therefore, the input data transferred to shift register SR2 is "1" only in _S3 , and all others are "0".
Of course, the data read by the read signal shown next to it is " ₁ " only for S3, and all others are "0". Also, the read signal passing through the AND circuit 11 is delayed by the delay circuit 5 as shown in Fig.
is reset and new input signals can be input. Note that the AND circuit 11 is prevented from being reset by the signal shown in D even if a read signal is received while the shift register SR1 is transferring data to the shift register SR2. Even if there are multiple ON bit signals at the same time among the N bits of data input as described above, the bit signal is always 1.
Only one bit signal can be turned on and output.

As explained in detail above, according to the present invention, even if a plurality of ON bit signals are input at the same time among input N bit data, only one bit signal can always be output as ON, and for example, in a measurement control system. This has the advantage that even if multiple buttons on the operation panel are pressed at the same time, there is no need to worry about confusing the sequence.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional instantaneous input type digital input circuit system when the input data is 16 bits. Figure 2 is a time chart for the system shown in Figure 1. A shows momentary switch _S3 turned on. B is the pulse signal from the differentiating circuit _d3 , C is the pulse signal when the momentary switch _S8 is turned on, D is the pulse signal from the differentiating circuit _d8 , E is the memory reset signal, F is the memory _M8
, G is a read signal, and H is a memory reset signal. FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a time chart for the embodiment of FIG. A and B are the pulse signals when the momentary switch is turned on, C is the output signal of the reset flip-flop Q, and D is d.
Signal at point, E is shift register set signal, F is clock pulse, G is internal signal of shift register, H is output signal of shift register, R is FF1
In the figure, numeral 1 indicates an output signal, numeral numeral indicates an internal signal of the shift register, ru indicates a read signal, and oc indicates a reset signal. In the figure, S ₁ to S ₁₆ are momentary switches, and d ₁ to
d ₁₆ and 9 are differential circuits, 1, G ₁ to _{G 16} and 10 are OR circuits, M ₁ to _{M 16} are memories, D ₁ to _{D 16} are open collector drivers, 2, 5 and 8 are delay circuits, and 3 is a Read signal input terminal, Vcc is a positive DC power supply, SR1 is a shift register for parallel-serial conversion, SR2 is a shift register for serial-parallel conversion, FF1 is a delay type flip-flop, FF2 is a set-reset flip-flop, 4,11 , 12 is an AND circuit, 6 is a clock control circuit, and 7 is a pulse generator.

Claims (1)

[Claims] 1 N-bit data that is input in parallel is converted into serial data in the parallel-to-serial converter, and the bits that are turned on are detected bit by bit, and the serial data after the first bit that is turned on is detected. An instantaneous input type digital input circuit system characterized by turning everything off, transferring it to the serial/parallel converter, and outputting it as parallel data.