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JPS6244813B2 - - Google Patents
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JPS6244813B2 - - Google Patents

Info

Publication number
JPS6244813B2
JPS6244813B2 JP56114666A JP11466681A JPS6244813B2 JP S6244813 B2 JPS6244813 B2 JP S6244813B2 JP 56114666 A JP56114666 A JP 56114666A JP 11466681 A JP11466681 A JP 11466681A JP S6244813 B2 JPS6244813 B2 JP S6244813B2
Authority
JP
Japan
Prior art keywords
film
semiconductor substrate
conductive film
insulating film
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56114666A
Other languages
Japanese (ja)
Other versions
JPS5816546A (en
Inventor
Takehiko Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56114666A priority Critical patent/JPS5816546A/en
Publication of JPS5816546A publication Critical patent/JPS5816546A/en
Publication of JPS6244813B2 publication Critical patent/JPS6244813B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48Insulating materials thereof

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置にかかり、特に半導体装置
におけるデバイスの相互配線用導電膜の構造に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a conductive film for interconnection of devices in a semiconductor device.

半導体装置はますます高集積化、高密度化が進
みそれに伴つて不純物拡散領域パターン、絶縁膜
への開孔パターン、導電膜のパターン等はますま
す微細化されるようになつている。これらパター
ンの微細化はそれに用いられる装置の加工精度に
よつて制限されるのが一般的である。しかしなが
ら導電膜のパターンの微細化は加工精度と同時
に、その導電膜に流すことのできる電流値によつ
ても制限を受けている。
Semiconductor devices are becoming increasingly highly integrated and densely packed, and as a result, impurity diffusion region patterns, opening patterns in insulating films, conductive film patterns, etc. are becoming increasingly finer. The miniaturization of these patterns is generally limited by the processing accuracy of the equipment used. However, the miniaturization of the conductive film pattern is limited not only by the processing accuracy but also by the current value that can be passed through the conductive film.

特に近年加工精度の向上が著しいので電流値に
よる制限の方が重要になつてきている。電流値に
対する制限は一般に導電膜の断面積に対する電流
密度で規定される。
In particular, as machining accuracy has improved significantly in recent years, restrictions based on current values have become more important. Limits on the current value are generally defined by the current density relative to the cross-sectional area of the conductive film.

導電膜にある一定電流密度以上の電流を流すと
はなはだしい場合には自己発熱のために導電膜自
身が溶断してしまうが、それに到らない場合にお
いても、電流が流れることによつて導電膜中をイ
オンが移動することにより断線する場合がある。
後者はエレクトロマイグレーシヨンによる断線と
呼ばれており、半導体装置の実使用状態での劣
化、故障の重要な要因の一つとなつている。
If a current exceeding a certain current density is passed through the conductive film, the conductive film itself will melt due to self-heating, but even if this does not occur, the current flowing through the conductive film will cause the conductive film to melt. Disconnection may occur due to the movement of ions.
The latter is called disconnection due to electromigration, and is one of the important causes of deterioration and failure of semiconductor devices during actual use.

導電体としてアルミニウム(Al)薄膜を使用
した場合のエレクトロマイグレーシヨンのメカニ
ズムを簡単に記述する。一般に金属薄膜に電流を
流すと金属原子は、電子導体の場合、電界による
力と電子の流れによる力という互いに方向の反対
の力を同時にうける。しかし金属原子は通常それ
をとり巻く電子により電気的にシールドされてい
るため、金属原子に対しては電界による力が弱ま
り電子による力が支配的となる。このため金属原
子は電子流の方向に流され、正の極の側に蓄積さ
れてヒロツクやホイスカーを生じる。一方、金属
原子の移動したあとの空格子点は、反対方向に流
され、負の極の側に蓄積されてボイドを形成し、
配線の断線を生ずる。
The electromigration mechanism when using an aluminum (Al) thin film as a conductor will be briefly described. Generally, when a current is passed through a metal thin film, the metal atoms, in the case of an electron conductor, are simultaneously subjected to forces caused by the electric field and force caused by the flow of electrons, both in opposite directions. However, since metal atoms are usually electrically shielded by the electrons surrounding them, the force of the electric field weakens against the metal atoms, and the force of the electrons becomes dominant. For this reason, metal atoms are swept in the direction of the electron flow and accumulate on the positive pole side, creating hills and whiskers. On the other hand, the vacancies after the metal atoms move are swept in the opposite direction and accumulate on the negative pole side, forming voids.
This will cause the wiring to become disconnected.

このようなエレクトロマイグレーシヨンを抑制
する方法として、 (1) Alの金属学的組織を改善する、 (2) Alの形状を改善する、 (3) Al膜にある種の金属を添加する、 (4) Al配線を誘電体で被膜する、 などがある。
Methods to suppress such electromigration include (1) improving the metallographic structure of Al, (2) improving the shape of Al, (3) adding certain metals to the Al film, ( 4) Coating Al wiring with dielectric material, etc.

(1)の方法は具体的にはAl膜を形成するとき
に、半導体基板の温度を上げるなどして、Al膜
の結晶粒径を大きくすることであるが、この方法
はAl膜の微細加工における加工精度をそこなう
恐れがあるので好ましくない。(2)の方法は半導体
装置のパターン設計に望ましくない制限を与え
る。また(4)の方法は誘電体で被覆するという余分
な工程を経る必要があるので望ましくない。そこ
で、現在最も望ましいと考えられるエレクトロマ
イグレーシヨン抑制法は(3)の方法、すなわちAl
膜にある種の金属を添加する方法である。添加す
る金属としては一般にマグネシウム(Mg)、ニツ
ケル(Ni)、クロム(Cr)などが有効である。し
かしながら、Al膜に上記金属を均一に添加する
ことは困難であるばかりでなく、異種金属が混合
した薄膜を均一にエツチングすることも困難であ
る。
Specifically, method (1) involves increasing the crystal grain size of the Al film by increasing the temperature of the semiconductor substrate when forming the Al film. This is not preferable because it may impair the machining accuracy. Method (2) imposes undesirable restrictions on pattern design of semiconductor devices. Further, method (4) is not desirable because it requires an extra step of coating with a dielectric material. Therefore, the most desirable electromigration suppression method at present is method (3), that is, Al
This method involves adding certain metals to the film. Magnesium (Mg), nickel (Ni), chromium (Cr), etc. are generally effective as metals to be added. However, it is not only difficult to uniformly add the above metals to the Al film, but also difficult to uniformly etch a thin film containing a mixture of different metals.

本発明の目的は上記従来の問題点を解消し、エ
レクトロマイグレーシヨンを抑制した導電体層の
構造を提供することにある。
An object of the present invention is to solve the above-mentioned conventional problems and provide a structure of a conductive layer in which electromigration is suppressed.

本発明は半導体基板と、選択的に設けられた複
数個の開孔部を有し該半導体基板を覆う絶縁膜
と、該開孔部を通じて半導体基板と電気的に接続
し、かつ該絶縁膜上に延在して選択的に設けられ
た導電膜を有する半導体装置において、該導伝膜
が結晶粒径と同じかもしくはそれ以下の膜厚ごと
に異種金属層を有する多層膜で、構成されている
ことを特徴としている。
The present invention includes a semiconductor substrate, an insulating film having a plurality of selectively provided openings and covering the semiconductor substrate, and an insulating film that is electrically connected to the semiconductor substrate through the openings, and that is electrically connected to the semiconductor substrate through the openings. In a semiconductor device having a conductive film selectively provided extending over a region, the conductive film is composed of a multilayer film having different metal layers each having a thickness equal to or less than a crystal grain size. It is characterized by the presence of

次に本発明をよりよく理解するために、従来技
術と比較しながら図面を用いて説明する。
Next, in order to better understand the present invention, the present invention will be explained using the drawings while comparing it with the prior art.

第1図は従来技術の構造を示す断面図である。
複数の回路素子(図中では省略)を含む半導体基
板11を覆い、選択的に設けられた開孔部を有す
る熱酸化膜12の上面に導電体層(金属配線層)
13,14が形成されている。導電体層13は微
細な結晶粒の集合としてモザイク模様で示した。
導電体層13から導電体層14へ、半導体基板を
通じて電流を流す場合には電子流は14から13
へと流れる。第1図の構造の場合には結晶粒界が
多数あり、粒界にそつて導電体構成原子が移動す
るため、コンタクト孔15均傍には原子が蓄積さ
れ、コンタクト孔16の近傍では原子が無くなり
断線を生じる。これを防ぐために比較的新らしい
従来技術ではすでに述べたように電子流による移
動速度の遅い銅(Cu)等を導電体層中に添加
し、結晶粒界に析出させることによりエレクトロ
マイグレーシヨンを抑制しているが、結晶粒界に
析出したCu等は、導電体と合金を形成し、エツ
チングによるパターン形成が困難である。
FIG. 1 is a sectional view showing the structure of the prior art.
A conductor layer (metal wiring layer) is formed on the upper surface of a thermal oxide film 12 that covers a semiconductor substrate 11 including a plurality of circuit elements (not shown) and has selectively provided openings.
13 and 14 are formed. The conductor layer 13 is shown in a mosaic pattern as a collection of fine crystal grains.
When a current is passed from the conductor layer 13 to the conductor layer 14 through the semiconductor substrate, the electron flow is 14 to 13.
flows to. In the case of the structure shown in FIG. 1, there are many grain boundaries, and the atoms constituting the conductor move along the grain boundaries, so atoms are accumulated near the contact hole 15, and atoms are accumulated near the contact hole 16. This causes wire breakage. To prevent this, relatively new conventional technology suppresses electromigration by adding copper (Cu), which has a slow movement speed due to electron flow, into the conductor layer and depositing it at the grain boundaries. However, Cu deposited at grain boundaries forms an alloy with the conductor, making it difficult to form a pattern by etching.

第2図は本発明の実施例である。 FIG. 2 shows an embodiment of the invention.

半導体基板21と、選択的に設けられた複数個
の開孔部を有し該半導体基板を覆う絶縁膜22と
該開孔部を通じて半導体基板と電気的に接続し、
かつ該絶縁膜上に延在して選択的に設けられた導
電膜を有する半導体装置において、該導電膜は結
晶粒径28以内の膜厚29で異種金属24を設け
て二層構造となつている。本発明の実施例におい
ては導電体層は膜厚方向に〓つた結晶粒界を有す
るために、粒界における導体原子のエレクトロマ
イグレーシヨン現象を極めて低く抑制できる。ま
た、導体間に設けられた異種金属は層状に形成さ
れるので、選択エツチングによるパターン形成に
おいても、それぞれに適したエツチヤントを用い
ることができるので、加工上の問題もない。導体
層間に設ける異種金属としては導体層がAlの場
合にはCu,NiおよびCr等のように原子半径がAl
と大きく異つているものが望ましい。
a semiconductor substrate 21; an insulating film 22 having a plurality of selectively provided openings and covering the semiconductor substrate; electrically connected to the semiconductor substrate through the openings;
In a semiconductor device having a conductive film extending and selectively provided on the insulating film, the conductive film has a two-layer structure with a dissimilar metal 24 having a crystal grain size of 28 or less and a film thickness of 29. There is. In the embodiments of the present invention, since the conductor layer has crystal grain boundaries extending in the film thickness direction, the electromigration phenomenon of conductor atoms at the grain boundaries can be suppressed to an extremely low level. Furthermore, since the dissimilar metals provided between the conductors are formed in layers, etchants suitable for each can be used in pattern formation by selective etching, so there are no processing problems. When the conductor layer is made of Al, the dissimilar metals provided between the conductor layers are those with an atomic radius of Al, such as Cu, Ni, and Cr.
It is desirable to have something that is significantly different from the above.

導体層の結晶粒の大きさは、蒸着又はスパツタ
リング等の方法で導体膜を被着させる場合、半導
体基板の下地温度によつて大きく変わる。通常の
蒸着装置の場合、基板温度200℃でAl膜をつける
と、その結晶粒は〓1μ程度となる。
The size of crystal grains in a conductor layer varies greatly depending on the underlying temperature of the semiconductor substrate when a conductor film is deposited by a method such as vapor deposition or sputtering. In the case of a normal evaporation device, when an Al film is deposited at a substrate temperature of 200°C, the crystal grains will be approximately 1μ.

従つてAl膜厚を1.5μmとすると、Alを0.75μ
mつけた時点で、例えばCuを0.03μm被着し、
その後残りのAlを0.75μm被着するのが望まし
い。
Therefore, if the Al film thickness is 1.5μm, the Al thickness is 0.75μm.
At the time when 0.03 μm of Cu is applied, for example,
After that, it is desirable to deposit the remaining Al to a thickness of 0.75 μm.

以上本発明について簡単な構造の実施例を用い
て説明したが、実施例における半導体基板内の素
子については、MOS型トランジスタ、バイポー
ラ型トランジスタ、FETトランジスタ、PN接合
ダイオード等の能動素子、及び抵抗、容量等の受
動素子及びこれらの組合せ素子等についてすべて
適用可能である。それ故、本発明の特許権は、特
許請求の範囲に示すすべての半導体装置に及ぶも
のである。
The present invention has been described above using an example with a simple structure, but the elements in the semiconductor substrate in the example include active elements such as a MOS transistor, a bipolar transistor, a FET transistor, a PN junction diode, and a resistor. It is applicable to all passive elements such as capacitors and combination elements thereof. Therefore, the patent rights of the present invention extend to all semiconductor devices shown in the claims.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術を示す断面図である。第2図
は本発明の実施例を示す断面図である。図中に示
した英数字はそれぞれ次のものを示す。 11,21……半導体基板、12,22……絶
縁膜、13,14,23,25……導電体層、1
5,16,26,27……絶縁膜の開孔部、28
……導電体層の結晶粒の大きさ、29……導電体
層の膜厚である。
FIG. 1 is a sectional view showing the prior art. FIG. 2 is a sectional view showing an embodiment of the present invention. The alphanumeric characters shown in the figure each indicate the following. 11, 21... Semiconductor substrate, 12, 22... Insulating film, 13, 14, 23, 25... Conductor layer, 1
5, 16, 26, 27...Opening part of insulating film, 28
. . . Size of crystal grains in the conductor layer, 29 . . . Thickness of the conductor layer.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板と、選択的に設けられた複数個の
開孔部を有し該半導体基板を覆う絶縁膜と、該開
孔部を通じて半導体基板と電気的に接続しかつ該
絶縁膜上に延在して選択的に設けられた導電膜と
を有する半導体装置において、前記導電膜の平均
結晶粒径以内の該導電膜の膜厚の部分ごとに異種
金属層を設けることを特徴とする半導体装置。
1. A semiconductor substrate, an insulating film having a plurality of selectively provided openings and covering the semiconductor substrate, and an insulating film electrically connected to the semiconductor substrate through the openings and extending over the insulating film. 1. A semiconductor device having a conductive film selectively provided as a conductive film, wherein a different metal layer is provided for each part of the conductive film having a thickness within an average crystal grain size of the conductive film.
JP56114666A 1981-07-22 1981-07-22 Semiconductor device Granted JPS5816546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56114666A JPS5816546A (en) 1981-07-22 1981-07-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56114666A JPS5816546A (en) 1981-07-22 1981-07-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5816546A JPS5816546A (en) 1983-01-31
JPS6244813B2 true JPS6244813B2 (en) 1987-09-22

Family

ID=14643541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56114666A Granted JPS5816546A (en) 1981-07-22 1981-07-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5816546A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6417052U (en) * 1987-07-21 1989-01-27
JPS6436740U (en) * 1987-08-29 1989-03-06

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0687464B2 (en) * 1986-12-17 1994-11-02 日本電装株式会社 Aluminum alloy wiring device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6417052U (en) * 1987-07-21 1989-01-27
JPS6436740U (en) * 1987-08-29 1989-03-06

Also Published As

Publication number Publication date
JPS5816546A (en) 1983-01-31

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