JPS6246985B2 - - Google Patents
Info
- Publication number
- JPS6246985B2 JPS6246985B2 JP54091558A JP9155879A JPS6246985B2 JP S6246985 B2 JPS6246985 B2 JP S6246985B2 JP 54091558 A JP54091558 A JP 54091558A JP 9155879 A JP9155879 A JP 9155879A JP S6246985 B2 JPS6246985 B2 JP S6246985B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistance
- contact
- semiconductor
- resistor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/40—Resistors
- H10D1/43—Resistors having PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
この発明は半導体集積回路装置における半導体
抵抗に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor resistor in a semiconductor integrated circuit device.
半導体基板上に半導体抵抗を形成する場合、半
導体抵抗を実現する半導体拡散層や多結晶半導体
層とこれとオーミツクコンタクト（抵抗接触）す
る導体端子のコンタクト穴加工用のマスクのずれ
が問題となる。特に最近、Ａ／Ｄ、Ｄ／Ａ変換器
等がIC（集積回路）化されるに従い、それに使
用される電圧分割用抵抗は高精度が要求されるよ
うになつた。例えば(1)第１図に示すように半導体
基板１の横長拡散層２を抵抗としてこれを分割す
るために表面絶縁膜３に等間隔にコンタクト孔４
をあけてAl（アルミニウム）等の配線５を形成
するか、(2)第２図に示すように抵抗となる横長拡
散層（又は横長多結晶半導体層）６より等間隔に
拡散層７ａ，７ｂ…を引き出して電圧を分割し、
電流供給端子としてAl配線９を横長抵抗６の両
端部のコンタクト孔８ａ，８ｂのみに設ける等の
構造が従来から採用されている。これらの問題点
として(1)の構造ではコンタクト部の精度が高くと
れない、(2)の構造では引出し線により分割された
分割抵抗比Ｒi，Ｒi…は高精度にとれるが、両端
の電流供給端子のコンタクト部は拡散層との間で
細長拡散層の長手方向での位置合せずれ△ｌによ
り、両端部に近い分割抵抗の比に誤差（±△Ｒ）
を生じる。 When forming a semiconductor resistor on a semiconductor substrate, there is a problem of misalignment between the semiconductor diffusion layer or polycrystalline semiconductor layer that realizes the semiconductor resistor and the mask for contact hole processing of the conductor terminal that makes ohmic contact with this layer. . Particularly recently, as A/D, D/A converters, etc. have been integrated into ICs (integrated circuits), the voltage dividing resistors used therein are required to have high accuracy. For example, (1) as shown in FIG. 1, contact holes 4 are formed at equal intervals in the surface insulating film 3 in order to divide the horizontally long diffusion layer 2 of the semiconductor substrate 1 into a resistor.
(2) As shown in FIG. 2, form wirings 5 made of Al (aluminum) or the like, or (2) form diffusion layers 7a and 7b at equal intervals from the horizontally long diffusion layer (or horizontally long polycrystalline semiconductor layer) 6 that will serve as a resistor, as shown in FIG. ...and divide the voltage,
Conventionally, a structure has been adopted in which Al wiring 9 is provided as a current supply terminal only in contact holes 8a and 8b at both ends of horizontally long resistor 6. These problems include that the structure (1) cannot provide high accuracy in the contact part, and the structure (2) allows for high accuracy in the divided resistance ratios R i , R i ... divided by the lead wires, but The contact part of the current supply terminal has an error (±△R) in the ratio of the dividing resistors near both ends due to the misalignment △l in the longitudinal direction of the elongated diffusion layer between the contact part and the diffusion layer.
occurs.
本発明はこれら従来技術の問題点を取除くため
になされたものである。したがつてこの発明の目
的は、半導体抵抗による分割抵抗のコンタクト位
置ずれによる誤差を少なくし、高精度の抵抗を得
ることにある。 The present invention has been made to eliminate these problems of the prior art. Therefore, an object of the present invention is to reduce errors caused by contact positional deviation of a divided resistor using semiconductor resistors, and to obtain a highly accurate resistor.
上記目的を達成するため本発明においては、端
子側の抵抗装置の一部をループ状の並列抵抗に形
成してこのループの途中にコンタクト部を設ける
か、あるいは、端子側の抵抗をＴ字状に形成し、
２個所にコンタクト部を設けて相互に短絡するこ
とにより少なくとも半導体抵抗の長手方向に対す
るコンタクト穴用マスクのずれによる分割抵抗比
の誤差をなくすことを特徴とする。 In order to achieve the above object, in the present invention, a part of the resistance device on the terminal side is formed into a loop-shaped parallel resistance device and a contact part is provided in the middle of this loop, or alternatively, the resistance device on the terminal side is formed into a T-shaped resistance device. formed into
The present invention is characterized in that by providing contact portions at two locations and short-circuiting them, errors in the dividing resistance ratio caused by misalignment of the contact hole mask at least in the longitudinal direction of the semiconductor resistor can be eliminated.
以下実施例にそつて本発明を詳述する。 The present invention will be described in detail below with reference to Examples.
第３図に示すようにＸ方向に横長状の半導体抵
抗１０、例えば半導体拡散層又は不純物ドープ多
結晶半導体層が形成され、これよりＹ方向に等間
隔で分割された引出し線１１ａ，１１ｂ…が設け
てある半導体分割抵抗装置において、コンタクト
のずれが問題となる両端部（図面では一端部のみ
を記載）をその軸線に対称な２方向に延ばしてル
ープ状の末端を接続させたループ状抵抗（並列抵
抗R1，R2）１２とし、ループ状抵抗の末端側の部
分１３の中央にコンタクト部１４を設けてAl配
線を接続するものである。 As shown in FIG. 3, a horizontally elongated semiconductor resistor 10, such as a semiconductor diffusion layer or an impurity-doped polycrystalline semiconductor layer, is formed in the X direction, and lead lines 11a, 11b, . . . are divided at equal intervals in the Y direction. In the semiconductor divided resistor device that is provided, both ends (only one end is shown in the drawing) where contact misalignment is a problem are extended in two directions symmetrical to the axis and the loop-shaped ends are connected. Parallel resistors R 1 , R 2 ) 12 are used, and a contact portion 14 is provided at the center of the terminal end portion 13 of the loop-shaped resistor to connect the Al wiring.
上記構造において、コンタクト穴１４は十分に
大きくされ、ループ状抵抗を実質的に横切るよう
に設けられる。このように、コンタクト穴を十分
に大きくすれば、例え、マスクずれにより、Ｘ方
向の半導体抵抗領域１２に対するコンタクト部の
ずれが生じても、ループ状抵抗内のコンタクト部
付近の電流の流れ、或いは電気力線は均一にされ
るから、Ｘ方向のマスクずれに基づく抵抗値の誤
差或いは偏差は防止できる。 In the above structure, the contact hole 14 is sufficiently large and provided to substantially cross the loop-shaped resistor. In this way, if the contact hole is made sufficiently large, even if the contact part is misaligned with respect to the semiconductor resistance region 12 in the X direction due to mask misalignment, the current flow near the contact part in the loop resistor or Since the lines of electric force are made uniform, errors or deviations in resistance values due to mask displacement in the X direction can be prevented.
このようにして、抵抗値の誤差は、Ｙ方向のマ
スクずれにより支配されるようになるが、本発明
によれば、Ｙ方向のコンタクト部の位置ずれに従
つて、互いに並列接続される２つの抵抗R1，R2
の抵抗値が互いに反対方向に変化するので、マス
クずれによる抵抗値の誤差を防止することてでき
る。 In this way, the resistance value error comes to be dominated by the mask shift in the Y direction, but according to the present invention, two parallel-connected Resistance R 1 , R 2
Since the resistance values change in opposite directions, errors in resistance values due to mask displacement can be prevented.
いま、コンタクト穴の位置１４が全くずれてい
ない時のR1とR2の抵抗値が、R1＝R2＝Ｒtとなる
ように設計する。さらに、この時、Ｒｔ／２＋R′＝Ｒ
となるように、R′の値を決定する。R′の値は、
抵抗領域１０の幾何学的構造を決めるパターンマ
スクにより一義的に設定できるから、このR′の
抵抗値は、コンタクト穴の位置ずれによつて変化
することはない。従つて、コンタクト穴の位置ず
れによつて変化するのは、ループ状抵抗部１２の
抵抗R1とR2との合成並列抵抗の変化となる。 Now, the design is made so that the resistance values of R 1 and R 2 when the position 14 of the contact hole is not shifted at all are as follows: R 1 =R 2 = Rt . Furthermore, at this time, the value of R' is determined so that R t /2+R'=R. The value of R′ is
Since it can be uniquely set using a pattern mask that determines the geometrical structure of the resistance region 10, the resistance value of R' does not change due to positional deviation of the contact hole. Therefore, what changes due to the positional shift of the contact hole is a change in the combined parallel resistance of the resistances R 1 and R 2 of the loop-shaped resistance section 12.
仮りに、コンタクト穴の位置１４が、マスクず
れに基づいて上側にずれたとすると、ループ状抵
抗部の抵抗R1の抵抗値は減少し、逆に、R2の抵
抗値は増加する。 If the position 14 of the contact hole were to shift upward due to mask displacement, the resistance value of the resistance R 1 of the loop-shaped resistance portion would decrease, and conversely, the resistance value of R 2 would increase.
コンタクト穴の位置ずれによる抵抗の変化分
（バラツキ）をΔＲとすれば、R1＝Ｒt−ΔR1、
R2＝Ｒt＋ΔＲとなり、第４図に示すような等価
回路のR1とR2との並列合成抵抗R1R2は、
R1R2＝Ｒｔ／２｛１−（ΔＲ／Ｒｔ）２｝
となる。 If the change (variation) in resistance due to positional deviation of the contact hole is ΔR, then R 1 = R t −ΔR 1 ,
R 2 = R t + ΔR, and the parallel combined resistance R 1 R 2 of R 1 and R 2 in the equivalent circuit as shown in FIG. t ) 2 }.
上記の式から明らかなように、例えば、マスク
ずれにより、ΔＲが設計値Ｒtに対し10％変化し
たとしても
R1R2＝0.99Ｒｔ／２＝0.99（Ｒ−R′）
となり、一桁の精度向上が期待できる。 As is clear from the above equation, for example, even if ΔR changes by 10% from the design value R t due to mask displacement, R 1 R 2 = 0.99 R t /2 = 0.99 (R - R'), and It is expected that the accuracy of digits will improve.
コンタクト部を第５図に示すように抵抗の幅ｄ
より広くとつた「ドツグボーン」型とすればＸ方
向のずれは相殺できる。 As shown in Figure 5, the width of the resistor is d.
By using a wider "dogbone" type, the deviation in the X direction can be offset.
並列抵抗R1，R2は第６図のように非対称な
（R1≠R2）ループ状抵抗１５であつてもよくこの
場合もコンタクト部１６のズレによる抵抗の精度
をかなり向上することができる。 The parallel resistors R 1 and R 2 may be asymmetrical (R 1 ≠ R 2 ) loop-shaped resistors 15 as shown in FIG. can.
本発明の他の実施例は第７図に示すようにＸ方
向にそつて形成した横長の半導体抵抗１７、例え
ば第７Ａ図を参照し基板１８上に絶縁膜１９を介
して形成した多結晶半導体層１７の両端部を第７
図のようにＹ方向に対称的に延長してＴ字形部２
０を形成し、その先端にコンタクト部２１，２１
を形成し、これらを層間絶縁膜２２を介してAl
配線２３により短絡するようにしたものである。 Another embodiment of the present invention is a horizontally long semiconductor resistor 17 formed along the X direction as shown in FIG. Both ends of layer 17 are
T-shaped part 2 is extended symmetrically in the Y direction as shown in the figure.
0, and contact portions 21, 21 are formed at the tips of the contact portions 21, 21.
are formed, and these are connected to Al through the interlayer insulating film
The wiring 23 is used to create a short circuit.
この場合、r1＝r2＋ｒ３／２ (1) になるようにｌ，Ｗを決める。 In this case, l and W are determined so that r 1 =r 2 +r 3 /2 (1).
先端Ｔ字状突起部分２０の抵抗をＲ，ｌ、半導
体抵抗の面積抵抗をσとすると
Ｒ＝ｒ３／２＝ｌ／２Ｗσ (2)
いまコンタクトが上（下）側へ△ｌずれたとす
るとその時の抵抗R′は（Ｔ状部分の両サイドの
長さはｌ＋△ｌ、ｌ−△ｌとなるから）
R′＝ｌ２−△ｌ２／２ｌＷσ (3)
∴R′／Ｒ＝（l2−△l2）／l2
＝１−（△ｌ／ｌ）２ (4)
したがつて半導体抵抗における両端の抵抗精度
は
r′／ｒ＝１±（△ｌ′／ｌ′）２ (5)
以上述べたところからＹ方向のズレによる精度
は、(4)式により抵抗比精度が△ｌ／ｌ→（△ｌ／ｌ）
２と改
善され、又、突起部分が並列となるためｌが従来
の場合よりも長くなり△ｌ／ｌも改善される。こ
の例の場合にも、Ｘ方向に対するズレはコンタク
トの寸法を抵抗の幅Ｗより大きくとつておけば影
響を無視できる。 Let the resistance of the T-shaped protrusion 20 at the tip be R, l, and the sheet resistance of the semiconductor resistor be σ. R=r 3 /2=l/2Wσ (2) If the contact is now shifted △l to the upper (lower) side The resistance R' at that time is (because the lengths on both sides of the T-shaped part are l+△l and l-△l) R'=l 2 - △l 2 /2lWσ (3) ∴R'/R=( l 2 −△l 2 )/l 2 =1−(△l/l) 2 (4) Therefore, the resistance accuracy at both ends of the semiconductor resistor is r'/r=1±(△l'/l') 2 (5) From the above, the accuracy due to the deviation in the Y direction is determined by equation (4), where the resistance ratio accuracy is △l/l → (△l/l)
2 , and since the protruding portions are parallel, l is longer than in the conventional case, and Δl/l is also improved. In this example as well, the effect of deviation in the X direction can be ignored if the dimensions of the contact are set larger than the width W of the resistor.
この発明は高精度Ｄ／Ａ、Ａ／Ｄ変換用ICに
適用して極めて有効である。 This invention is extremely effective when applied to high-precision D/A and A/D conversion ICs.
第１図は従来の半導体分割抵抗の例を示す平面
図、第１Ａ図は第１図のＡ―Ａ視断面図、第２図
は従来の半導体分割抵抗の他の例を示す平面図で
ある。第３図は本発明による半導体抵抗の一実施
例を示す要部平面図、第４図は第３図の等価回路
図、第５図、第６図は第３図の変形例を示す平面
図、第７図は本発明による半導体抵抗の他の実施
例を示す平面図、第７Ａ図は第７図のＡ―Ａ視断
面図である。
１…半導体基板、２…拡散抵抗層、３…絶縁
膜、４…コンタクト穴、５…Al配線、６…半導
体抵抗、７ａ，７ｂ…抵抗引出し線、８ａ，８ｂ
…両端のコンタクト部、９…Al配線、１０…横
長半導体抵抗、１１ａ，１１ｂ…抵抗引出し線、
１２…ループ状抵抗、１３…Ｙ方向に延びる部
分、１４…コンタクト部、１７…横長半導体抵
抗、１８…基板、１９…絶縁膜、２０…Ｔ字形
部、２１…コンタクト部、２２…層間絶縁膜、２
３…Al配線。
FIG. 1 is a plan view showing an example of a conventional semiconductor dividing resistor, FIG. 1A is a sectional view taken along line AA in FIG. 1, and FIG. 2 is a plan view showing another example of a conventional semiconductor dividing resistor. . FIG. 3 is a plan view of essential parts showing an embodiment of a semiconductor resistor according to the present invention, FIG. 4 is an equivalent circuit diagram of FIG. 3, and FIGS. 5 and 6 are plan views showing modifications of FIG. 3. , FIG. 7 is a plan view showing another embodiment of the semiconductor resistor according to the present invention, and FIG. 7A is a sectional view taken along line AA in FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffused resistance layer, 3... Insulating film, 4... Contact hole, 5... Al wiring, 6... Semiconductor resistor, 7a, 7b... Resistance lead line, 8a, 8b
...Contact parts at both ends, 9...Al wiring, 10...Horizontally long semiconductor resistor, 11a, 11b...Resistance lead wire,
DESCRIPTION OF SYMBOLS 12... Loop-shaped resistance, 13... Portion extending in the Y direction, 14... Contact part, 17... Laterally elongated semiconductor resistor, 18... Substrate, 19... Insulating film, 20... T-shaped part, 21... Contact part, 22... Interlayer insulating film ,2
3...Al wiring.
Claims (1)
と、この抵抗領域の複数個所にコンタクト部とを
有する抵抗装置において、上記抵抗領域の一部
は、前記抵抗領域の他の部分から分岐してそれら
の末端で閉じた並列抵抗部分として形成され、こ
の並列抵抗部分の末端側で前記並列抵抗路を横切
る方向にコンタクト部を設けたことを特徴とする
抵抗装置。 ２ 基板上の一方向に沿い形成された抵抗領域
と、この抵抗領域の複数個所にコンタクト部とを
有する抵抗装置において、前記抵抗領域の一部
は、前記一方向にのびる抵抗領域の他の部分から
それと直交して相対向する両方向へのびる一対の
枝部として形成され、該一対の枝部の端部にそれ
ぞれコンタクト部を設けて、これら一対の端部間
を配線により短絡して成ることを特徴とする抵抗
装置。[Scope of Claims] 1. In a resistor device having a resistor region formed along one direction on a substrate and contact portions at a plurality of locations in the resistor region, a part of the resistor region is located outside the resistor region. A resistor device, characterized in that it is formed as a parallel resistance portion branched from a portion thereof and closed at its end, and a contact portion is provided in a direction across the parallel resistance path at the end side of the parallel resistance portion. 2. In a resistor device having a resistor region formed along one direction on a substrate and contact portions at a plurality of locations on the resistor region, a part of the resistor region is different from other parts of the resistor region extending in the one direction. It is formed as a pair of branch parts extending in opposite directions perpendicularly to the branch part, a contact part is provided at each end of the pair of branch parts, and the pair of ends are short-circuited by wiring. Characteristic resistance device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9155879A JPS5617052A (en) | 1979-07-20 | 1979-07-20 | Semiconductor resistor device |
| DE19803027332 DE3027332A1 (en) | 1979-07-20 | 1980-07-18 | Surface resistance for integrated circuit chips - has layer with branched or loop widened connection end to ensure connection accuracy for strip formation resistance pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9155879A JPS5617052A (en) | 1979-07-20 | 1979-07-20 | Semiconductor resistor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5617052A JPS5617052A (en) | 1981-02-18 |
| JPS6246985B2 true JPS6246985B2 (en) | 1987-10-06 |
Family
ID=14029830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9155879A Granted JPS5617052A (en) | 1979-07-20 | 1979-07-20 | Semiconductor resistor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5617052A (en) |
| DE (1) | DE3027332A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182918A (en) * | 1982-04-21 | 1983-10-26 | Toshiba Corp | Voltage dividing circuit |
| JPS58224668A (en) * | 1982-06-21 | 1983-12-27 | Sukeroku Shokuhin Kk | Processed food made from head-foot part of cuttlefish as main raw material and preparation thereof |
| EP0298574B1 (en) * | 1987-07-10 | 1993-12-29 | Koninklijke Philips Electronics N.V. | Linear integrated resistor |
-
1979
- 1979-07-20 JP JP9155879A patent/JPS5617052A/en active Granted
-
1980
- 1980-07-18 DE DE19803027332 patent/DE3027332A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5617052A (en) | 1981-02-18 |
| DE3027332A1 (en) | 1981-02-05 |
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