JPS6247257B2 - - Google Patents
Info
- Publication number
- JPS6247257B2 JPS6247257B2 JP55088016A JP8801680A JPS6247257B2 JP S6247257 B2 JPS6247257 B2 JP S6247257B2 JP 55088016 A JP55088016 A JP 55088016A JP 8801680 A JP8801680 A JP 8801680A JP S6247257 B2 JPS6247257 B2 JP S6247257B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- pulse width
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 230000008676 import Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000005856 abnormality Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000000284 extract Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R21/00—Arrangements for measuring electric power or power factor
- G01R21/127—Arrangements for measuring electric power or power factor by using pulse modulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
Description
【発明の詳細な説明】
本発明は電子式電力量計の改良に係り、特に故
障検出機能を持つた電子式電力量計に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an electronic watt-hour meter, and particularly to an electronic watt-hour meter having a failure detection function.
一般に、単相電子式電力量計では、電圧変換部
分例えば計器用変圧器に断線故障が生ずると、乗
算機能が停止され電力に比例するパルスが出なく
なるので容易に外部から異常と判断できる。しか
し、三相電子式電力量計の場合は、何れか1つの
相に故障が生じても他方が正常に動作していれ
ば、積算値を得ることができて外部から故障を確
認できない。 Generally, in a single-phase electronic watt-hour meter, if a disconnection failure occurs in the voltage conversion part, for example, the voltage transformer, the multiplication function is stopped and pulses proportional to the electric power are no longer output, so it can be easily determined from the outside that there is an abnormality. However, in the case of a three-phase electronic watt-hour meter, even if a failure occurs in one of the phases, as long as the other phase is operating normally, an integrated value can be obtained and the failure cannot be confirmed from the outside.
そこで、従来、第1図のような構成の故障検出
回路を採用して以上の不都合を回避していた。同
図において1は負荷電圧に比例した信号を取り出
す計器用変圧器であつて、これの1次側に電流を
検出する抵抗2を接続し、この抵抗2によつて得
られた電圧を増幅器3で適宜増幅した後、整流回
路4で整流し、この整流出力値と予め定めた基準
値とを比較回路5で比較し、異常があれば表示部
6に表示するようになつている。 Therefore, conventionally, a failure detection circuit having a configuration as shown in FIG. 1 has been adopted to avoid the above-mentioned inconvenience. In the figure, reference numeral 1 denotes an instrument transformer that extracts a signal proportional to the load voltage.A resistor 2 for detecting current is connected to the primary side of this transformer, and the voltage obtained by this resistor 2 is transferred to an amplifier 3. After being appropriately amplified, the output value is rectified by a rectifier circuit 4, and this rectified output value is compared with a predetermined reference value by a comparator circuit 5. If there is an abnormality, it is displayed on a display section 6.
しかし、以上のような故障検出手段では、計器
用変圧器1に負担がかかつて特性を悪くし、結果
的に変圧器1の2次側に接続される図示しない乗
算部の特性補償が必要となり、電力測定精度にも
不都合をきたす欠点がある。 However, the above-described failure detection means places a heavy burden on the potential transformer 1, worsening its characteristics, and as a result, it becomes necessary to compensate for the characteristics of a multiplier section (not shown) connected to the secondary side of the transformer 1. However, there are also disadvantages in terms of power measurement accuracy.
本発明は上記事情にかんがみてなされたもので
あつて、電圧変換部に負担をかけることなく、こ
の電圧変換部の故障を検出できるようにする故障
検出機能を持つた電子式電力量計を提供するもの
である。 The present invention has been made in view of the above circumstances, and provides an electronic watt-hour meter having a failure detection function that allows failure of the voltage conversion unit to be detected without placing a burden on the voltage conversion unit. It is something to do.
以下、本発明の一実施例を説明するにあたり、
先ず、本発明の要旨となる故障検出機能を付加す
る一般的な電子式電力量計について第2図を参照
して説明する。同図において11は電力給電線の
負荷電圧に比例した信号を検出する電圧変換部
(計器用変圧器)であつて、これの2次側には同
電圧変換部11の出力信号によつてパルス幅変調
しパルス幅デユーテイサイクル信号を出力するパ
ルス幅変調回路12が接続されている。また、電
圧変換部11とは別個に電力給電線の消費電流に
比例した信号を検出して出力する電流変換部13
(電流変成器)があり、これの2次側巻線両端に
抵抗14を接続して電圧信号に変換し時分割乗算
回路15に供給している。この時分割乗算回路1
5は複数のアナログ・スイツチで構成され、パル
ス幅変調回路12のパルス幅デユーテイサイクル
信号で上記アナログ・スイツチを選択的に制御し
ながら消費電流に比例した電圧信号を取り入れて
時分割乗算を行なつている。乗算結果は後続の抵
抗およびコンデンサよりなる積分回路16a,1
6bで積分し電力に比例する電圧信号を得た後、
これを電圧―パルス周波数変換回路17により電
力に比例した周波数のパルスに変換し、さらに分
周回路18で分周して積算値を表示部19に表示
するものである。 Below, in explaining one embodiment of the present invention,
First, a general electronic watt-hour meter to which a failure detection function is added, which is the gist of the present invention, will be explained with reference to FIG. In the figure, reference numeral 11 denotes a voltage converter (instrument transformer) that detects a signal proportional to the load voltage of the power supply line. A pulse width modulation circuit 12 that performs width modulation and outputs a pulse width duty cycle signal is connected. Also, separate from the voltage converter 11, a current converter 13 detects and outputs a signal proportional to the current consumption of the power supply line.
(current transformer), a resistor 14 is connected to both ends of the secondary winding of this transformer to convert it into a voltage signal and supply it to a time division multiplier circuit 15. This time division multiplication circuit 1
5 is composed of a plurality of analog switches, and while selectively controlling the analog switches with the pulse width duty cycle signal of the pulse width modulation circuit 12, a voltage signal proportional to the current consumption is taken in to perform time division multiplication. is being carried out. The multiplication result is transferred to the subsequent integrating circuit 16a, 1 consisting of a resistor and a capacitor.
After integrating at 6b and obtaining a voltage signal proportional to the power,
This is converted into a pulse with a frequency proportional to the electric power by a voltage-pulse frequency conversion circuit 17, and further divided by a frequency dividing circuit 18, and the integrated value is displayed on a display section 19.
次に、第3図は第2図に示すパルス幅変調回路
の具体的構成である。つまり、この回路は、演算
増幅器A1の反転入力部に抵抗R1を、また反転
入力部と出力部との間にコンデンサC1を設けて
積分回路を構成するとともに、積分回路の出力部
をコンパレータA2の非反転入力部に接続してい
る。このコンパレータA2はヒステリシス特性を
持つ積分出力ekが反転入力部に供給される電圧
eh=〓1/2er(この〓1/2erは基準電圧±erを
インバータ回路INで反転し抵抗R3=R4で分圧さ
れた値)に達するごとに反転して論理回路を出力
するものである。つまり、コンパレータA2の出
力は論理信号“1”の時に+er、論理信号
“0”の時に−erなる振幅となるように構成され
ている。R2は抵抗である。 Next, FIG. 3 shows a specific configuration of the pulse width modulation circuit shown in FIG. 2. In other words, this circuit configures an integrating circuit by providing a resistor R 1 at the inverting input section of operational amplifier A1 and a capacitor C 1 between the inverting input section and the output section, and connects the output section of the integrating circuit to a comparator. Connected to the non-inverting input of A2. This comparator A2 has a voltage e h =〓1/2e r (this 〓1/2e r is obtained by inverting the reference voltage ±e r with an inverter circuit IN and resisting the voltage e h =〓1/2e r where the integral output e k having hysteresis characteristics is supplied to the inverting input section). Each time the voltage reaches R 3 = the value divided by R 4 ), it is inverted and output from the logic circuit. In other words, the output of the comparator A2 is configured to have an amplitude of + er when the logic signal is "1" and -er when the logic signal is "0". R 2 is the resistance.
今、ev=0であつてコンパレータA2の出力
が論理信号“1”で整定されているとすると、同
コンパレータA2の反転入力部電圧ehは第4図
aのようにR3=R4によつて−er/2が印加されてい
る。さらに、抵抗R2によつて+erなる基準電圧
が演算増幅器A1に導入されている。この結果、
積分回路A1の出力は第4図bのように負方向に
傾斜して下降し、ek=−er/2に達するとek≦eh
と
なつてコンパレータA2の出力は“0”即ち−e
rに設定される。 Now, assuming that e v =0 and the output of comparator A2 is set to a logic signal "1", the inverting input voltage e h of comparator A2 is R 3 = R 4 as shown in Figure 4a. -er /2 is applied by. Furthermore, a reference voltage +e r is introduced into the operational amplifier A1 by means of a resistor R 2 . As a result,
The output of the integrating circuit A1 slopes downward in the negative direction as shown in FIG. 4b, and when e k =-e r /2 is reached, e k ≦e h
Therefore, the output of comparator A2 is "0", that is, -e
Set to r .
そうすると、今度はコンパレータA2の反転入
力部に+er/2の電圧が印加され、一方、抵抗R2によ
つて演算増幅器A1に−erが導入される。この
結果、積分回路の出力ekは正方向に積分傾斜を
示して上昇し+er/2に達しek≧ehとなると、コン
パレータA2は論理信号“1”に正転する。 Then, a voltage of + er /2 is now applied to the inverting input of the comparator A2, while -er is introduced into the operational amplifier A1 by the resistor R2 . As a result, the output e k of the integrating circuit increases with an integral slope in the positive direction, reaches + er /2, and when e k ≧e h , the comparator A2 normally rotates to the logic signal "1".
今、コンパレータA2の出力が論理信号“1”
の時間区間をta、論理信号“0”の時間区間を
tbとすると、積分回路の出力ekは、
ek(ta)=−(1/R1C1∫ta 0evdt+1/R
2C1∫ta 0erdt)
=−er ……(1)
となる。ここで、R1=R2とすれば、
ta=erR1C1/er+ev ……(2)
ek(tb)=−(1/R1C1∫tb 0evdt−1/R
2C1∫tb 0erdt)
=+er ……(3)
tb=erR1C1/er−ev ……(4)
となる。したがつて、パルス幅変調回路12から
出力するパルス幅デユーテイサイクル信号は、
D=ta/ta+tb=er−ev/2er …(5)
=tb/ta+tb=er+ev/2er ……(6)
となる。 Now, the output of comparator A2 is a logic signal “1”
When the time interval of is t a and the time interval of logic signal "0" is t b , the output e k of the integrating circuit is e k (t a )=-(1/R 1 C 1 ∫ ta 0 e v dt+1 /R
2 C 1 ∫ ta 0 e r dt) = -er ...(1). Here, if R 1 = R 2 , then t a = e r R 1 C 1 / e r + e v ...(2) e k (t b ) = -(1/R 1 C 1 ∫ tb 0 e v dt-1/R
2 C 1 ∫ tb 0 e r dt) = + e r ... (3) t b = e r R 1 C 1 / e r - e v ... (4). Therefore, the pulse width duty cycle signal output from the pulse width modulation circuit 12 is D=t a /t a +t b = er − e v / 2er (5) =t b /t a +t b = e r + e v /2 e r (6).
次に、以上のようなパルス幅変調回路12の動
作原理に基づいて電圧変換部の故障を検出する例
につき第5図ないし第7図を参照して説明する。
なお、第5図および第6図は理解を深めるための
前提説明、第7図は一実施例としての構成であ
る。 Next, an example of detecting a failure in the voltage conversion section based on the operating principle of the pulse width modulation circuit 12 as described above will be described with reference to FIGS. 5 to 7.
Note that FIGS. 5 and 6 are premise explanations for better understanding, and FIG. 7 is a configuration as an example.
今、電圧回路側に断線その他の故障が生じる
と、電圧変換部11の2次側の出力は0となり、
(5)式、(6)式から明らかなようにパルス幅変調回路
12のデユーテイサイクル信号は第5図aのよう
に50%になり、これを後続の積分回路16a,1
6bで一サイクル積分すれば0となる。従つ
て、故障が生じた際、一定期間積分しても第5図
bから明らかなように0である。電圧変換部1
1が正常の場合は絶えずパルス幅変調をしてお
り、このためデユーテイサイクル信号は第6図a
のように変化している。従つて、ある期間積分回
路16a,16bで積分すれば第6図bのように
必ず積分値が出てくる。よつて、パルス幅変調回
路12の出力をある期間積分して0であれば、
電圧変換部11に異常が生じ、積分出力が出れば
正常であることが分る。 Now, if a disconnection or other failure occurs on the voltage circuit side, the output on the secondary side of the voltage converter 11 becomes 0,
As is clear from equations (5) and (6), the duty cycle signal of the pulse width modulation circuit 12 becomes 50% as shown in FIG.
If one cycle is integrated at 6b, it becomes 0. Therefore, when a failure occurs, even if the integral is integrated for a certain period of time, the result is 0, as is clear from FIG. 5b. Voltage converter 1
1 is normal, the pulse width is constantly modulated, so the duty cycle signal is as shown in Figure 6a.
It's changing like this. Therefore, if the integration circuits 16a and 16b perform integration for a certain period, an integrated value as shown in FIG. 6b will always come out. Therefore, if the output of the pulse width modulation circuit 12 is integrated over a certain period and is 0, then
If an abnormality occurs in the voltage converter 11 and an integral output is output, it is known that the voltage converter 11 is normal.
次に、第7図はパルス幅変調回路12の出力部
に接続して電圧回路側の故障を検出する回路構成
図である。パルス幅変調回路12の出力部にスイ
ツチ回路S1および抵抗R5、コンデンサC2の積分
回路を介して複数のコンパレータA3,A4の非
反転入力部に接続する。一方のコンパレータA3
の反転入力部には電圧VDDを抵抗R6,R7で分圧
した電圧が印加され、またコンパレータA4の反
転入力部に電圧−VSSを抵抗R8,R9で分圧した
電圧が印加されている。これらコンパレータ回路
A3,A4は排他的論理回路ORを介し、抵抗
R10、駆動トランジスタTrを介して故障時に発光
する例えば発光ダイオードLEDに接続されてい
る。R11は抵抗である。 Next, FIG. 7 is a circuit configuration diagram that is connected to the output section of the pulse width modulation circuit 12 to detect a failure on the voltage circuit side. The output part of the pulse width modulation circuit 12 is connected to the non-inverting input parts of a plurality of comparators A3 and A4 via a switch circuit S1 , a resistor R5 , and an integrating circuit including a capacitor C2 . One comparator A3
A voltage obtained by dividing the voltage V DD by resistors R 6 and R 7 is applied to the inverting input portion of the comparator A4, and a voltage obtained by dividing the voltage −V SS by resistors R 8 and R 9 is applied to the inverting input portion of the comparator A4. is being applied. These comparator circuits A3 and A4 are connected to resistors via an exclusive logic circuit OR.
R 10 is connected to, for example, a light emitting diode LED, which emits light in the event of a failure, via the drive transistor Tr. R 11 is the resistance.
次に、第7図に示す回路の動作を説明する。パ
ルス幅変調回路12の出力をスイツチ回路S1を介
して取り込んだ後、積分回路で一定期間(evの
1/2サイクル)積分し、この積分出力をコンパレ
ータA3の反転入力部に供給する。このコンパレ
ータA3は積分出力が電圧VDDの分電圧以上にな
ると、“H”レベルとなりこれが排他的論理和回
路ORの一方入力部に供給される。また、コンパ
レータA4は積分出力が電圧−VSSの分電圧以上
になると、“H”レベルとなりこれが排他的論理
和回路ORの他方入力部に供給される。同回路OR
はこれら2つのコンパレータA3,A4の排他的
論理和をとつて出力する。 Next, the operation of the circuit shown in FIG. 7 will be explained. After taking in the output of the pulse width modulation circuit 12 via the switch circuit S1 , it is input for a certain period of time (e v
1/2 cycle) and supplies this integrated output to the inverting input of comparator A3. When the integrated output of the comparator A3 becomes equal to or higher than the voltage VDD , the comparator A3 attains an "H" level and is supplied to one input of the exclusive OR circuit OR. Further, when the integrated output of the comparator A4 becomes equal to or higher than the voltage divided by the voltage -V SS , the comparator A4 attains an "H" level and is supplied to the other input section of the exclusive OR circuit OR. Same circuit OR
calculates the exclusive OR of these two comparators A3 and A4 and outputs the result.
今、R5,C2からなる積分回路の出力が0の
場合、コンパレータA3の出力が“L”、コンパ
レータA4の出力が“H”となり、トランジスタ
Trの動作によつて発光ダイオードLEDが発光す
る。それ以外では排他的論理和回路ORの出力は
“L”であるので、発光ダイオードLEDは発光し
ない。このように電圧回路側の故障はパルス幅変
調回路12の出力を用いて表示部の点灯によつて
容易に知りうるものである。 Now, when the output of the integrating circuit consisting of R 5 and C 2 is 0, the output of comparator A3 becomes "L", the output of comparator A4 becomes "H", and the transistor
The light emitting diode LED emits light due to the operation of the Tr. Otherwise, the output of the exclusive OR circuit OR is "L", so the light emitting diode LED does not emit light. In this way, a failure on the voltage circuit side can be easily detected by lighting the display section using the output of the pulse width modulation circuit 12.
なお、本発明はその要旨を逸脱しない範囲で
種々変形実施できることは勿論である。 It goes without saying that the present invention can be modified in various ways without departing from the spirit thereof.
以上詳記したように本発明によれば、パルス幅
変調回路のパルス幅デユーテイサイクル信号を用
いてある電圧と比較しその比較結果に基づいて電
圧回路側の故障を判定するので、電圧変換部に何
ら負担をかけずに故障を検出でき、さらにパルス
幅変調回路の後続回路に影響を与えないので電力
量を高精度に計量できる電子式電力量計を提供で
きる。 As detailed above, according to the present invention, the pulse width duty cycle signal of the pulse width modulation circuit is used to compare it with a certain voltage, and a failure on the voltage circuit side is determined based on the comparison result. It is possible to provide an electronic watt-hour meter that can detect a failure without placing any burden on the circuit, and that can measure electric power with high precision because it does not affect the circuits subsequent to the pulse width modulation circuit.
第1図は従来の故障検出回路の構成図、第2図
は電子式電力量計の一般的構成図、第3図は第2
図のパルス幅変調回路の具体例を示す構成図、第
4図a〜cは第3図の動作を説明する図、第5図
および第6図は電圧回路側の故障を検出するため
の前提をなす説明図、第7図は本発明の要部を示
す故障検出回路の構成図である。
11…電圧変換部、12…パルス幅変調回路、
13…電流変換部、15…時分割乗算回路、16
a,16b…積分回路、17…電圧−パルス周波
数変換回路、18…分周回路、19…表示部、
R5,C2…積分回路、A3,A4…コンパレー
タ、OR…排他的論理和回路、Tr…駆動トランジ
スタ、LED…発光ダイオード。
Figure 1 is a configuration diagram of a conventional failure detection circuit, Figure 2 is a general configuration diagram of an electronic watt-hour meter, and Figure 3 is a configuration diagram of a conventional failure detection circuit.
Figures 4a to 4c are diagrams explaining the operation of Figure 3. Figures 5 and 6 are prerequisites for detecting failures on the voltage circuit side. FIG. 7 is a configuration diagram of a failure detection circuit showing the main part of the present invention. 11... Voltage converter, 12... Pulse width modulation circuit,
13...Current converter, 15...Time division multiplication circuit, 16
a, 16b... Integrating circuit, 17... Voltage-pulse frequency conversion circuit, 18... Frequency dividing circuit, 19... Display unit,
R5 , C2 ...Integrator circuit, A3, A4...Comparator, OR...Exclusive OR circuit, Tr...Drive transistor, LED...Light emitting diode.
Claims (1)
ス幅変調回路でパルス幅デユーテイサイクル信号
に変換し、この信号を用いて複数のスイツチを選
択し給電線の消費電流に比例した信号を取り込ん
で時分割乗算を行なう電子式電力量計において、
前記パルス幅変調回路の出力部に、前記パルス幅
デユーテイサイクル信号を前記信号evの1/2サイ
クルで積分する積分回路と、この積分回路の出力
の有無を判定する回路とを有する故障検出回路を
設けたことを特徴とする電子式電力量計。1 Convert the signal e v proportional to the load voltage of the power supply line into a pulse width duty cycle signal using a pulse width modulation circuit, use this signal to select multiple switches, and generate a signal proportional to the current consumption of the power supply line. In an electronic watt-hour meter that imports data and performs time-sharing multiplication,
A fault in which the output section of the pulse width modulation circuit includes an integrating circuit that integrates the pulse width duty cycle signal over 1/2 cycle of the signal e v , and a circuit that determines the presence or absence of an output of the integrating circuit. An electronic watt-hour meter characterized by being equipped with a detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8801680A JPS5713363A (en) | 1980-06-28 | 1980-06-28 | Electronic system electric energy meter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8801680A JPS5713363A (en) | 1980-06-28 | 1980-06-28 | Electronic system electric energy meter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5713363A JPS5713363A (en) | 1982-01-23 |
| JPS6247257B2 true JPS6247257B2 (en) | 1987-10-07 |
Family
ID=13931033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8801680A Granted JPS5713363A (en) | 1980-06-28 | 1980-06-28 | Electronic system electric energy meter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5713363A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0275970A (en) * | 1988-09-13 | 1990-03-15 | Tokyo Electric Power Co Inc:The | Electronic watthour meter |
| JP2542305B2 (en) * | 1991-12-18 | 1996-10-09 | コマツ電子金属株式会社 | Ingot cutting method |
-
1980
- 1980-06-28 JP JP8801680A patent/JPS5713363A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5713363A (en) | 1982-01-23 |
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