JPS6248254B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to an improvement in a division device in a Galois field suitable for decoding an error correction code used, for example, in an optical digital audio disc (DAD) playback device. [Technical background of the invention] As is well known, the recently developed optical system
Cross-interleaved Reed-Solomon code (CIRC) is used as an error correction code for DAD playback devices (particularly CD (compact disk type)).
is adopted. In other words, it is broadly defined as having the highest error correction ability among the typical random error correction codes known to date.
It uses a Reed-Solomon code, which is a type of BCH code, but it is also accompanied by signal processing called cross-interleaving in order to have a high correction ability even for burst errors. By the way, decoding, that is, error correction of the Reed-Solomon code can be performed in the same way as that of the BCH code. Let us now examine a decoding method for a Reed-Solomon code consisting of a code length (n), information symbols (k), and check symbols (nk). However, each of the above symbols is an element of a Galois field CF(2 ^m ) which is a finite field having (m) binary bits, that is, 2 ^m elements. In this case, the generating polynomial g _(x) of the (t) multiple error correction Reed-Solomon code is expressed as the following equation (1) or (2), where (α) is a primitive element of the Galois field GF (2 ^m ). is expressed in g _(x) = (x+α) (x+α ² ) …(x+α ^2t ) …(1) g _(x) = (x+α ₀ ) (x+α) …(x+α ^2t-1 ) …(2) Also, the transmission code word is C _(x) and the received codeword as R _(x)
, and if the error polynomial is E _(x) , then
The following relationship holds between these. R _(x) = C _(x) + E _(x) …(3) In this case, the coefficients of the polynomial are Galois field GF (2 ^m )
, and the error polynomial E _(x) contains only terms corresponding to the error location and value (magnitude). Therefore, if the error value at position x _j is Y _j In Equation (4), Σ means the sum of errors over all positions. Here, if we define the syndrome S _i as S _i =R (α ⁱ ) [where i = 0, 1...2t-1] ...(5), then from the above equation (3), S _i = C (α ⁱ )+E(α ⁱ ). In this case, since C _(x) is always divisible by g _(x) , C (α ⁱ ) = 0, so S _i = E (α ⁱ ). Therefore, from equation (4) above, It can be expressed as However, α ^j =X _j , where X _j represents the error location at α ^j . Here, the error location polynomial σ ( _x is
Let the number of errors be e is defined as Moreover, σ ₁ to σ _e in equation (7) are related to the syndrome S _i as follows. S _i+e +σ ₁ S _i+e-1 + …σ _e-1 S _i+1 +σ _e S _i …(8) In other words, the decoding procedure for the Reed-Solomon code as described above is given by equation () (5). Calculate the syndrome S _i . () Calculate the coefficients σ ₁ to σ _e of the error location polynomial using equation (8). () Find the root X _j of the error location polynomial using equation (7). () Find the error value Y _j using equation (6), and find the error polynomial using equation (4). () Error correction is performed using equation (3). This results in the steps () to (). Next, as a specific example of error correction using the above decoding procedure, a case will be described in which four check symbols are used for one block of data. That is, the raw voice generator polynomial g _(x) in this case is g _(x) = (x + 1) (x + α) (x + α ² ) (x + α ³ ), and it is possible to correct up to double errors. Here, we will discuss the two methods [A] and [B] separately. [Method A] () Calculate syndromes _S0 to _S3 . () Rewriting equation (8) for e=1 and e=2, in the case of e=1, becomes. Also, in the case of e=2 becomes. Here, assuming that the actual decoder starts its operation from the case where e=1, it is first necessary to find a solution σ ₁ that satisfies the simultaneous equations (9). Then, if this solution does not exist, the decoder then e
In the case of =2, solutions σ ₁ and σ ₂ that satisfy simultaneous equations (10) must be found. Note that if no solution is obtained here, it is assumed that e≧3. The solution σ ₁ of equation (9) is obtained as σ ₁ =S ₁ /S ₀ =S ₂ /S ₁ =S ₃ /S ₂ , and the solutions σ ₁ and σ ₂ of equation (10) are obtained as σ ₁ =S ₀ S ₃ +S ₁ S ₂ /S ₁ ² +S ₀ S ₂ ,σ ₂
It is determined as =S ₁ S ₃ +S ₂ ² /S ₁ ² +S ₀ S ₂ . () Once the coefficient σ _i of the error location polynomial has been obtained as described above, the roots of the error location polynomial are then determined using equation (7). First, when e=1, σ _(x) =x+σ ₁ =0, ∴X ₁ =σ ₁ . In addition, in the case of e = 2, σ _(x) = x ² + σ ₁ x + σ ₂ = 0 ...(11), and the elements of the Galois field GF (2 ^m ) are sequentially substituted into equation (11) to solve the problem. All you have to do is find the roots, and now let these roots be X ₁ and X ₂ . () Once the roots of the error location polynomial have been found, the error value Y _j is then found using equation (6). First, when e=1, S ₀ =Y ₁ ∴Y ₁ =S ₀ . In addition _, in the case of e=2, S ₀ =Y ₁ +Y ₂ S ₁ =Y ₁ X ₁ +Y ₂ X ₂ ∴Y ₁ = _{X 2} S _{0 + S 1 /} ) Error values Y ₁ , Y ₂ obtained as above
Corrections will be made. By the way, if the value of the error location can be accurately known using the pointer erasure method or the like, it is possible to correct up to quadruple errors using the above-mentioned Reed-Solomon code for double error correction. This is [Method B], which will be described later. [Method B] () Calculate syndromes _S0 to _S3 . (), () Find out the error location using another detection method. () Calculate the error value using equation (6). First, in the case of e=1 and e=2, it is the same as () of the above-mentioned [method A]. If e=3, S ₀ =Y ₁ +Y ₂ +Y ₃ S ₁ =Y ₁ X ₁ +Y ₂ X ₂ +Y ₃ X ₃ S ₂ =Y ₁ X ₁ ² +Y _{2 X 2 2} ^{+ Y} ₃ Solve Y ₁ =(S ₂ +X ₃ S ₁ )+X ₂ (S ₁ +X ₃ S ₀ )/(
X ₁ +X ₂ )(X ₁ +X ₃ ) Y ₂ =(S ₁ +X ₃ S ₀ )+Y ₁ (X ₁ +X ₃ )/(X ₂
+X ₃ ) Y ₃ =S ₀ +Y ₁ +Y ₂ . In addition, in the case of e=4, S ₀ =Y ₁ +Y ₂ +Y ₃ +Y ₄ S ₁ =Y ₁ X ₁ +Y ₂ X ₂ + ^Y ₃ X ₃ +Y _{4 X 4 S 2} = _{Y 1} ² +Y ₃ ^X ₃ ² ₊ ^Y ₄ X ₄ ² _{S 3} =Y ₁ X ₁ ³ _{+ Y 2 X 2} ³ _{+ Y 3 3} + (S ₁ X ₄ +S ₂ )}X ₂ + ₍ S ₁ X ₄ +S ₂ ) _{X 3 +} (S 2
₁ +X _{2 )} (X ₁ +X ₃ )(X ₁ +X ₄ ) Y ₂ =(S ₀ X _{4 +} S ₁ ) _{X 3 + ( S 1 4} )/(X ₂ +X ₃ )(X ₂ +
_{X 4 ) Y 3} = (S ₀ X ₄ + S _{1 )} + Y ₁ ( _{X 1} + X ₄ ) + Y _{2 ( X 2 +} . () Correction is made using Y ₁ to _{Y 4} obtained as described above. FIG. 1 is a schematic configuration diagram showing an actual Reed-Solomon code decoding system based on the above principle. That is, the data to be corrected (of course Reed-Solomon code is used for error correction) led through the input terminal (IN) is divided into two parts, one of which is used as a data buffer during the decoding operation described later. 11, and the other one is led to the syndrome calculator 12 and below for decoding operations. The syndrome calculated by the syndrome calculator 12 is stored in the syndrome buffer 13. Here, the OR gate 14 connected to the output part of the syndrome buffer 13 indicates the presence or absence of an error, and if there is an error, an error correction operation is started according to the procedure described above. In other words, the error location polynomial calculator 15
calculates the coefficients of the error location polynomial σ _(x) , the error location calculator 16 calculates the roots of the error location polynomial, and the error value calculator 1
7 calculates the error value, and by these error locations and error values, the above data buffer 1
This is to correct the data output from 1. By the way, each of the calculators 12, 15, 16, and 17 of such a decoding system detects whether or not it is 0 and performs necessary algebraic operations such as addition, multiplication, and division. Conventionally, an error location polynomial calculator (Japanese Patent Publication No. 56-20575) constructed as shown in FIG. 2 is known. That is, in FIG. 2, 21 is a syndrome buffer, which is a RAM for storing the syndrome S _i .
1 stores each syndrome which is an element of the Galois field GF(2 ^m ) in m-bit binary format. Further, 22 is a work buffer, which is used to store intermediate results and final results of algebraic operations when calculating the coefficients of the error location polynomial.
Partial results used in later calculations are also stored in the working buffer 22. 23 is a sequence control device for instructing the order of algebraic operations, and the syndrome buffer 2
1 and working buffer 22 to access appropriate storage locations;
It is used to check the result of the algebraic operation executed and branch to the next appropriate operation. Furthermore, 24 and 25 are each Galois field GF
These are a logarithm buffer and an antilog buffer consisting of a ROM that stores the original logarithm and antilog of (2 ^m ) separately in the form of a table. Here, the address of the former logarithm buffer 24 is the binary representation of the element α ⁱ , and its entry is the logarithm of α with α as the base, that is, i, but the entry at the address i of the latter logarithm buffer 25 is This is the binary representation of α ⁱ . For example, if the modulus polynomial F _(x) of the Galois field GF (2 ⁸ ) is F _(x) = x ⁸ + x ⁶ + x ⁵ + x ⁴ + 1, the elements other than 0 are the powers of the root α of F _(x) = 0. or linear combination from α ⁰ to α ⁷

[Problems with background technology]

However, the conventional error correction device as described above requires a logarithm buffer and an antilog buffer for multiplication and division among the algebraic operations in the error location polynomial calculator. Since the memory capacity of ROM etc. becomes enormous, it hinders the conversion to LSI and creates the problem that large capacity memory must be externally attached. If one symbol is 8 bits as in the example above, this means 255 x 8 bits = 2040 bits of ROM.
This can be easily seen from the fact that two are required, totaling 4080 bits. In other words, conventionally known multipliers and dividers in Galois fields require logarithm buffers and antilog buffers consisting of large-capacity memories that store the logarithms and antilogarithms of these elements separately in the form of tables. Therefore, there was a problem in that the configuration was complicated and the price was high. [Purpose of the Invention] The present invention has been made in view of the above-mentioned points, and it is an object to perform division in a Galois field without using a logarithm buffer or an antilog buffer that requires a particularly large capacity of memory. It is an object of the present invention to provide an extremely good division device in a Galois field that can contribute to simplifying the configuration, lowering the cost, and increasing processing speed. [Summary of ^the Invention] That is, the division device in a Galois field according to the present invention divides ^two elements α ⁱ and α ^j (where α is a modulus polynomial F _{( x)} root)), divide ^{α i ÷ α j} by
The first ^{multiplication} [α ⁱ・α
^M ] and the second multiplication [α ^j・α ^M ], and the second multiplication is α ^j・α ^M = α ^2m-1 = α ⁰
= 1, as a result α ⁱ ÷ α ^j = α ⁱ・
The element α j is processed by converting it into a multiplication α ^M , and the element α ^j is directly used as the dividend data, or an appropriate number of α ^N1 , α ^N2 ... multiplication circuits (however, N ₁ , N ₂ ... are 1<
N ₁ , N ₃ ... < 2 ^m-1 ), the first linear shift register group is set respectively through
ⁱ is directly or an appropriate number of α ^N as divisor data
¹ , α ^N2 . . . a second linear shift register group set respectively via a multiplication circuit;
one detection circuit group for detecting one output from each register of the linear shift register group; a first means for shifting the shift register group together; an output for each register of the second linear shift register group;
It is characterized by comprising a second means for ANDing the output of each detection circuit of the detection circuit group and deriving the ANDed register output. [Embodiments of the invention] First, an optical type (CD type) to which this invention is applied
An overview of a digital audio disc (DAD) playback device will be explained. That is, as shown in FIG. 3, the turntable 1 is rotated by a disk motor 111.
A disk 113 mounted on the optical pickup 112 is played back by an optical pickup 114. in this case,
The optical pickup 114 is a semiconductor laser 114.
A beam splitter 114b transmits the light emitted from the
It illuminates the signal surface of the disk 113 through the objective lens 114c, and corresponds to the digitized (PCM) data of the audio signal to be reproduced that is recorded on the disk 113 in a form with predetermined (EFM) modulation and interleaving. The reflected light from the pits (irregularities with different reflectances) is reflected by the objective lens 11.
4c, the beam splitter 114b leads to a 4-split photodetector 114d, and the 4 playback signals photoelectrically converted by the 4-split photodetector 114d can be outputted to the outside, and from the beam splitter 114b to a pick-up feed motor 115. Therefore, the disk 113 is linearly driven in the radial direction. The four reproduced signals from the four-division photodetector 114d are then supplied to the matrix circuit 116 and subjected to predetermined matrix calculation processing, thereby being separated into a focus error signal F, a tracking error signal, and a high frequency signal RF. . Of these, the focus error signal F is used together with the focus search signal from the focus search circuit 110 to drive the focus servo system FS of the optical pickup 114. Further, the tracking error signal T is sent to the optical pickup 1 along with a search control signal given via a system controller 117, which will be described later.
It is used to drive the 14 tracking servo systems TS and to control the pick-up feed motor 115 (linear tracking). The remaining high frequency signal RF is then supplied to the reproduction signal processing system 118 as the main reproduction signal component. That is, this reproduced signal processing system 118 first passes the reproduced signal to a slice level (eye pattern) detector 119.
The signal is guided to a waveform shaping circuit 120 controlled by a PLL type synchronous clock regeneration circuit 121 and a first signal processing system 122 to separate unnecessary analog components and necessary data components.
edge detector 122a. Here, the synchronous clock from the synchronous clock regeneration circuit 121 is guided to the synchronous signal separation clock generation circuit 122b in the first signal processing system 122 for data demodulation, and is used to generate a synchronous signal separation clock. . On the other hand, the reproduced signal that has passed through the edge detector 122a is guided to a sync signal detector 122c, where the sync signal is separated by the sync signal separation clock, and is also guided to a demodulation circuit 122d where it is demodulated (EFM). . Among these, the synchronization signal is transmitted to the synchronization signal protection circuit 122.
The signal is guided to the input data processing timing signal generation circuit 122f together with the synchronization signal separation clock through the signal line e in a state where it is protected from malfunction. Also, the demodulated signal is transmitted to the data bus input/output control circuit 1.
A second signal processing system 123 to be described later via 22g
is supplied to the input/output control circuit 123a of
The control signal and display signal components, which are subcodes, are sent to the control display processing circuit 1.
22h and subcode processing circuit 122i. The subcode data subjected to necessary error detection and correction by the subcode processing circuit 122i is sent to the system controller 117 via the system controller interface circuit 122g.
is supplied to Here, the system controller 117 includes a microcomputer, an interface circuit, a driver integrated circuit, etc., and controls the DAD playback device to a desired state based on command signals from the control switch 124, and also controls the above-mentioned subcodes (e.g. It is used to display the index information of the played song on the display 125. The timing signal from the input data processing timing signal generation circuit 122f is provided to control the data bus input/output control circuit 122g via the data selection circuit 122j, and is also used to control the data bus input/output control circuit 122g. 1
22l and PWM modulator 122m to drive the disc motor 111 at constant linear velocity (CLV).
It is provided with automatic frequency control AFC and automatic phase control APC to drive the system. In this case, the phase detector 122l is supplied with a system clock from a system clock generation circuit 122p which operates based on an oscillation signal from a crystal oscillator 122n. The demodulated data passing through the input/output control circuit 123a of the second signal processing circuit 123 is sent to the syndrome detector 1 for error detection and correction or correction.
23b, an error pointer control circuit 123c, a correction circuit 123d, and a data output circuit 123e, the data is subjected to necessary error correction, deinterleaving, error correction, etc. processing, and then outputted to a digital-to-analog (D/A) converter 126. . In this case, the external memory control circuit 123f cooperates with the data selection circuit 122j to select the external memory 127 in which data necessary for correction is written.
By controlling the above input/output control circuit 12
3a, data necessary for correction is taken in. Furthermore, the timing control circuit 123g is configured to supply timing control signals necessary for error correction and correction and D/A conversion based on the system clock from the system clock generation circuit 122p. Additionally, the mutating (detection) control circuit 123
h performs predetermined muting control necessary for error correction and for starting and ending the operation of the DAD playback device based on the output from the error pointer control circuit 123c or the control signal given via the system controller 117. It is offered to Then, the audio signal converted back to an analog signal by the D/A converter 126 is passed through a low-pass filter 128 and an amplifier 129, and is then provided to the speaker 130 to produce sound. Next, an embodiment of a division device in a Galois field according to the present invention applied to an error correction section of a DAD playback device as described above will be described in detail with reference to the drawings. That is, FIG. 4 shows the above-mentioned error location polynomial calculator section mainly included in the correction circuit 123d of the second signal processing circuit 123 in FIG. A multiplication device 41 that allows multiplication and division in a Galois field without using
It is the same as that of FIG. 2 described above except that it includes a dividing device 42 and a dividing device 42. In other words, the role of the error location polynomial calculator is to perform various algebraic operations for decoding (error correction) the Reed-Solomon code, which is a type of BCH code used as an error correction code. Of these, addition and detection of whether or not it is 0 are explained in the second section.
Since they are performed in the same way as those in the figure, the same reference numerals are given and the explanation thereof will be omitted. Multiplication and division that are different from those in FIG. 2 will be described below. First, let's look at multiplication in a Galois field. For example, the multiplication of elements α ⁱ and α ^j of Galois field GF (2 ⁸ ) (α ⁱ · α ^j , where α is the modulus polynomial F _(x) = X ⁸ + X ⁶
+X ⁵ +X ⁴ +1 root) is α ⁱ =C(α)=c ₀
+c ₁ α+...c ₇ α ⁷ α ^j = D (α) = d ₀ + d ₁ α+... d ₇ α ⁷ (However, c ₀ to c ₇ and d ₀ to d ₇ are 0 or 1. ) α ⁱ・α ^j =C(α)・D(α)=d ₇ α ⁷ C(α)+d ₆
α ⁶ C(α)……d ₀ C(α)=α ⁶ [αd ₇ C(α)+
d ₆ C (α)] + d ₅ α ⁵ C (α) + ... + d ₀ C (α) = α
⁵ [α[αd ₇ C (α) + d ₆ C (α)] + d ₅ C (α)] +
d ₄ α ⁴ C(α)＋……＋d ₀ C(α) 〓 = [α〔α〔α〔α〔α〔α〔αd ₇ C(α)＋
d ₆ C(α)〕＋d ₅ C(α)〕＋d ₄ C(α)〕＋d ₃ C
(α)] + d ₂ C (α)] + d ₁ C (α) + d ₀ C (α)]. In other words, the element α ⁱ of such Galois field GF(2 ⁸ )
This shows that the multiplication of α ^j by α j can be realized by a multiplier configured as shown in FIG. 5 using a linear shift register. That is, in FIG. 5, AND ₀ to AND ₇ are serially supplied with coefficients d ₀ to _{d 7} of the multiplier D (α) in order from the upper bit to one end of each, and
At each other end are c ₀ to _{c 7} which are the coefficients of the multiplicand C(α) above.
is an AND gate in which the bits are supplied in parallel in order from the most significant bits. In addition, FF ₀ to FF ₇ are connected via exclusive OR gates (EX-OR ₀ ) to (EX-OR ₇ ) to which the outputs from the AND gates AND ₀ to AND ₇ are supplied correspondingly to one input end. This is a flip-flop circuit that constitutes a linear shift register group _SR0 by being continuously connected and feedback connected. In this case, the flip-flop circuits FF ₃ in the 4th and 5th stages, the 5th and 6th stages, and the 6th and 7th stages are
- FF ₄ , FF ₄ - FF ₅ , FF ₅ - Between the stages of FF 7, exclusive OR gates (EX-OR ₄ '), (EX-OR _{5 '} , EX- OR ₆ ′) is further inserted. Further, a clock pulse CP from a clock generator (not shown) is supplied in parallel to the clock input terminal CK of each of the flip-flop circuits FF ₀ to _{FF 7} . In other words, by inputting _the coefficients c ₀ to _{c 7} of C(α) in a bit-serial manner, X ₀ is first calculated, then X _{1 ,} is X ₇ or C
(α)·D(α) is realized, and the outputs x ₀ , x _{1 .} . . x ₇ of each flip-flop circuit FF ₀ to FF ₇ give the multiplication result. Here, X ₀ to X ₇ are as follows. X ₀ = d ₇ C (α) X ₁ = αX ₀ + d ₆ C (α) X ₂ = αX ₁ + d ₅ C (α) X ₃ = αX ₂ + d ₄ C (α) X ₄ = αX ₃ + d ₃ C (α) X ₅ = αX ₄ + _{d 2 C (} α) X ₆ = αX _{5 + d 1 C} ( _α ) The multiplication device for the Galois field GF(2 ⁸ ) as described above is a logarithm buffer or an antilog buffer consisting of a large capacity memory such as a ROM that stores the logarithm and antilog of the elements of the Galois field GF(2 ⁸ ) in the form of a table. Since this can be done simply by using a linear shift register without using a , it has the advantage that the configuration can be made simple and inexpensive. Next, let's look at division in a Galois field. For example, the division of the elements α ⁱ and α ^j of the Galois field GF(2 ⁸ ) is α ⁱ ÷ α ^j (where α is the modulus polynomial F(x) = x ⁸ + x ⁶ +
x ⁵ + x ⁴ + 1 root) is equivalent to α ⁱ ÷ α ^j = (α ⁱ・α ^M ) ÷ (α ^j・α ^M ) (where M is an integer) In this case, α ^j・α If ^M = α ²⁵⁵ = α ⁰ = 1, then α ⁱ ÷ α ^j = α ⁱ・α ^M. In other words, when performing division (α ⁱ ÷ α ^j ) between elements α ⁱ and α ^j of the Galois field GF(2 ⁸ ), the dividend α ⁱ and the divisor α ^j
In the process of multiplying each by α M times, α
If α ^j・α ^M = 1 when multiplied by
α which is the product of the dividend α ⁱ and α ^m at that time
Utilizing the fact that ⁱ ·α ^M is the result of division, the desired division can be performed using multiplication processing. It goes without saying that the multiplication process is performed using a multiplication device using a linear shift register as described above. By the way, in this case α ^j・α ^M = α ²⁵⁵ = α ⁰ = 1
The number of times of multiplication by α required to obtain is at most 254 when the divisor α ^j = α ¹ (that is, M =
254), but simply allowing it to do so would undesirably increase the time required for the multiplication process. Therefore, in this invention, by multiplying the dividend α ⁱ and the divisor α ^j by α an appropriate number (N) times in advance, the number of times actually required for multiplication by α is reduced, and the multiplication process (delayed) is done in a short time. The purpose of this is to make it possible to perform division processing. FIG. 6 shows the configuration of a division device that realizes division in a Galois field by multiplication processing as described above. In this case, the above (N) is N ₁ = 64, N ₂
= 128, N ₃ = 192, that is, α ⁶⁴ , α ¹²⁸ , α ¹⁹² are multiplied in advance. That is, the divisor α ^j data is directly or α ⁶⁴
Linear shift registers A ₁ , _A ^{2 ,}
Set to A ₃ and A ₄ . Here, the linear shift registers A ₁ , A ₂ , A ₃ , and A ₄ are configured similarly to the linear shift register SR ₀ shown in _FIG . It is shifted by _p and multiplied by α for every shift. 1 detection circuits 54, 55, 56, which are supplied with the outputs of the shift registers _A1 , _A2 , _A3 , _A4 ,
57 is designed to produce a 1 detection output when the contents of the register become (10000000)=1. The 4-input NOR gate NOR ₁₀ to which each output of the 1 detection circuits 54, 55, 56, and 57 is supplied is activated by the output becoming "0" when any of the 1 detection outputs occurs. Said and gate
Through AND ₁₀ , the passage of the clock pulse C _p is controlled from the previously permitted state to the prohibited state. In addition, the dividend α ⁱ data is also transmitted directly or via the α ⁶⁴ multiplication circuit 58, α ¹²⁸ multiplication circuit 59, and α ¹⁹² multiplication circuit 60 to ^the linear shift registers B ₁ , B ₂ , B ₃ , B as well as the divisor α j data. After being set to ₄ ,
α is multiplied an appropriate number of times by the clock pulse C _p . Here, each output of the shift registers B ₁ , B ₂ , B ₃ , B ₄ corresponds to each output from the above-mentioned 1 detection circuits 54 , 55 , 56 , 57 and the AND circuits 61 , 62 , 6 .
3,64, an AND is taken. Then, by passing each output of the AND circuits 61, 62, 63, and 64 to the OR circuit 65, a division result of α ⁱ ÷ α ^j can be obtained. FIG. 7 shows a specific example of the 1 detection circuits 54 to 57 in the above, and shows the linear shift registers A ₁ to 57.
Among the outputs from _A4 , only the output corresponding to ^α1 is passed through the inverter _I10 , and the other outputs ^α2 to
This is a case where the circuit is configured with an 8-input NOR gate NOR ₁₁ to which the output corresponding to α ⁷ is directly added. FIG. 8 shows a specific example of the AND circuits 61 to 64 described above, in which each input terminal is supplied with each output from the linear shift registers B ₁ to B ₄ correspondingly, and each input terminal is supplied with one terminal at the other end. This is a case where the outputs of the detection circuits 54 to 57 are constructed of eight two-input AND gates _AND20 to _AND27 , which are respectively supplied in common. FIG. 9 shows a specific example of the OR circuit 65 described above, which includes eight 4-input OR gates to which each output of the AND circuits 61 to 64 is supplied correspondingly.
This is a case where it is composed of OR ₂₀ to OR ₂₇ . FIG. 10 shows a specific example of the above α ⁶⁴ multiplier circuit 58, in which α ^j is expressed as α ^j =B(α)=b ₇ α ⁷ +b ₆ α ⁶ +...b ₁ α+b ₀ It is based on the following principle (however, b ₁ to b ₇ are 0 or 1). In other words, α ⁶⁴ = α ⁷ + α ⁶ + α ⁵ , so α ⁶⁴・B(α) = (α ⁷ + α ⁶ + α ⁵ ) (b ₇ α ⁷
+…+b ₁ α+b ₀ )=(b ₀ +b ₁ +b ₅ +b ₇ )α ⁷ +(b ₀ +
b ₄ + b ₆ ) α ⁶ + (b ₀ + b ₁ + b ₃ ) α ⁵ + (b ₁ + b ₂ + b ₅ ) α
⁴ + (b ₄ + b ₅ ) α ³ + (b ₃ + b ₄ ) α ² + (b ₂ + b ₃ + b ₇ )
α+(b ₁ + b ₂ + b ₆ ). In other words, such an operation is an exclusive OR group (EX-OR ₁₁ ) as shown in Figure 10.
It is realized by ~(EX-OR ₂₅ ), and B(α)
If is input, a multiplication output of α ⁶⁴ ·B(α) can be obtained. Note that the α ¹²⁸ multiplication circuit 59 and the α ¹⁹² multiplication circuit 60
can also be easily constructed in accordance with the α ⁶⁴ multiplication circuit 58 described above. Next, as a specific example, a case where α ²⁰⁰ ÷ α ¹⁸⁰ = α ²⁰ is executed will be described. In this case, shift registers A ₁ to A ₄ , B ₁ to B ₄
is set as follows. A ₁ : α ¹⁸⁰ A ₂ : α ¹⁸⁰・α ⁶⁴ = α ²⁴⁴ A ₃ : α ¹⁸⁰・α ¹²⁸ = α ³⁰⁸ = α ⁵³ A ₄ : α ¹⁸⁰・α ¹⁹² = α ³⁷² = α ¹¹⁷ B ₁ : α ²⁰⁰ B ₂ : α ²⁰⁰・α ⁶⁴ = α ²⁶⁴ = α ⁹ B ₃ : α ²⁰⁰・α ¹²⁸ = α ³²⁸ = α ⁷³ B ₄ : α ²⁰⁰・α ¹⁹² = α ³⁰² = α ¹³⁷ And 11 clock pulses C _p are included. In this state, the contents of the shift register A ₂ become α ²⁵⁵ =1, and when this is detected by the 1 detection circuit 55, the supply of the clock pulse C _p is stopped. At this time, the content of shift register B ₂ is α ²⁰ , and the output α ²⁰ is outputted via AND circuit 62 and OR circuit 65 . In this way, the number of times α is multiplied is at most 63
The desired division can be performed by multiplier processing while reducing the number of times (when α ^j =α ¹ ). In this case, by increasing the number of linear shift register pairs, the number of times of multiplication by α can be reduced. It goes without saying that the present invention is not limited to the embodiments described above and illustrated, and that various modifications and applications can be made without departing from the gist of the invention. For example, it is suitable for devices that require algebraic operations using Galois fields, such as tape PCM and other digitized information transmission, recording and reproducing systems, computer systems, and the like. [Effects of the Invention] Therefore, as detailed above, according to the present invention, it is possible to perform division in a Galois field without using a logarithm buffer or an antilog buffer that requires a large capacity of memory. It becomes possible to provide an extremely good division device in a Galois field that contributes to a simplified configuration, lower cost, and higher processing speed.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram showing a Reed-Solomon code decoding system, Fig. 2 is a block diagram showing a conventional error location polynomial calculator, and Fig. 3 is an overview of a DAD playback device to which the present invention is applied. A configuration diagram, FIG. 4 is a configuration diagram showing an embodiment of the present invention,
5 is a block diagram showing a specific example of the multiplication device section in FIG. 4, FIG. 6 is a block diagram showing a specific example of the division device section in FIG. 4, and FIGS. 7 to 10 are respectively shown in FIG. 6. 1 detection circuit section, AND circuit section, OR circuit section, α ⁶⁴
FIG. 3 is a configuration diagram showing a specific example of a multiplication circuit section. _A1 to _A4 , _B1 to _B4 ...Linear shift register, 5
1,58...α ⁶⁴ multiplication circuit, 52,59...α ¹²⁸ multiplication circuit, 53,60...α ¹⁹² multiplication circuit, 54-57
...1 detection circuit, 61-64...AND circuit, 65...
AO circuit, AND ₁₁ …AND gate, NOR ₁₀ …Noah gate.

Claims (1)

[Claims] 1. Division α i between two elements α ^{i and} α ^j (where α is the root of the modulus polynomial F _(x) ) among 2 ^m elements ⁱⁿ the Galois field GF (2 ^m ) ÷α ^j in the form of the quotient of the first multiplication [α ⁱ · ^{α M} ] and the second multiplication [α ^j · α ^M ], which is α i · α ^M ÷ α ^j · α ^M (where M is an integer). Using the fact that the second multiplication is α ^j · α ^M = α ^2m-1 = α ⁰ = 1, the result is converted to the multiplication α ⁱ ÷ α ^j = α ⁱ · α ^M. The element α ^j is used as the dividend data directly or as an appropriate number of α ^N1 , α ^N2
…multiplication circuit (however, N ₁ , N ₂ … is 1<N ₁ , N ₂ …<2 ^m
-1 ), and the element α ⁱ is set individually as divisor data either directly or via an appropriate number of α ^N1 , α ^N2 . . . multiplication circuits. a second linear shift register group to be detected, one detection circuit group for detecting one output from each register of the first linear shift register group, and one output detected by any one of the one detection circuit group. a first means for shifting the first and second linear shift register groups together an appropriate number of times until the output of each register of the second linear shift register group and each detection of the first detection circuit group; 1. A division device in a Galois field, comprising: second means for ANDing the output of each circuit and deriving the ANDed register output.