JPS638648B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to an improvement of a multiplication device in a Galois field suitable for decoding an error correction code used, for example, in an optical digital audio disk (DAD) playback device. [Technical background of the invention] As is well known, the recently developed optical system
Cross-interleaved Reed-Solomon code (CIRC) is used as an error correction code for DAD playback devices (particularly CD (compact disk type)).
is adopted. In other words, it is broadly defined as having the highest error correction ability among the typical random error correction codes known to date.
It uses a Reed-Solomon code, which is a type of BCH code, but it is also accompanied by signal processing called cross-interleaving in order to have a high correction ability even for burst errors. By the way, decoding, that is, error correction of the Reed-Solomon code can be performed in the same way as that of the BCH code. Let us now examine a decoding method for a Reed-Solomon code consisting of a code length (n), information symbols (k), and check symbols (nk). However, each symbol above is a Galois field, which is a finite field having (m) binary bits, that is, 2 ^m elements.
It is the source of GF2 ^m . In this case, the generating polynomial g(x) of the (t) multiple error correction Reed-Solomon code is expressed as the following equation (1) or (2), where (α) is a primitive element of the Galois field GF(2 ^m ). is expressed in g (x) = (x + α) (x + α ² ) ... (x + α ^2t ) ... (1) g (x) = (x + α ⁰ ) (x + α) ... (x + α ^2t- ) ... (2) Also, transmission The code word is C(x), and the received code word is R.
(x) and the error polynomial is E(x), the following relationship holds between them. R(x)=C(x)+E(x)...(3) In this case, the coefficients of the polynomial are contained in the Galois field GF(2 ^m ), and the error polynomial E(x) is the error location and value. Contains only terms corresponding to (size). Therefore, if the error value at position x ^j is Y ^j , E(x) = 〓 ^j Y _j x ^j ...(4), and in equation (4), Σ means the sum of errors over all positions. ing. Here, if we define the syndrome S _i as S _i =R (α ⁱ ) [where i=0, 1...2t-1] ...(5), then from the above equation (3), S _i = C (α ⁱ )+E(α ⁱ ). In this case, since C(x) is always divisible by g(x), C(α ⁱ )=0, so S _i =E(α ⁱ ). Therefore, from equation (4) above,
It can be expressed as Si=E(α ⁱ )=〓 ^j Y _j (α ⁱ ) ^j =〓 ^j Y _j X ⁱ _j (6). However, α ^j =X _j , where X _j represents the error location at α ^j . Here, the error location polynomial σ(x) is
It is defined as σ(x)=〓i(x−X _i )=x ^e +σ ₁ x ^e−1 +……+σ _e ……(7) where the number of errors is e. Moreover, σ ₁ to σ _e in equation (7) are related to syndrome S _i as follows. S _i+e +σ ₁ S _i+e-1 +...σ _e-1 S _i+1 +σ _e S _i ...(8) In other words, the decoding procedure for the Reed-Solomon code as described above is () (5) Calculate the syndrome S _i by the formula. () Calculate the coefficients σ ₁ to σ _e of the error location polynomial using equation (8). () Find the root X _j of the error location polynomial using equation (7). () Find the error value Y _j using equation (6), and find the error polynomial using equation (4). () Error correction is performed using equation (3). This results in the steps () to (). Next, as a specific example of error correction using the above decoding procedure, a case will be described in which four check symbols are used for one block of data. That is, the generator polynomial g(x) in this case is g(x)=(x+1)(x+α)(x+α ² )(x+
α ³ ), which makes it possible to correct up to a double error, but here we will discuss the cases using two methods [A] and [B] separately. [Method A] () Calculate syndromes _S0 to _S3 . () Rewriting equation (8) for e=1 and e=2, in the case of e=1, S ₁ +σ ₁ S ₀ =0 S ₂ +σ ₁ S ₁ =0 S ₃ +σ ₁ S ₂ =0... …(9) becomes. Also, in the case of e=2
S ₂ +σ ₁ S ₁ +σ ₂ S ₀ =0 S ₃ +σ ₁ S ₂ +σ ₂ S ₁ =0 (10). Here, assuming that the actual decoder starts its operation from the case where e=1, it is first necessary to find a solution σ ₁ that satisfies the simultaneous equations (9). If this solution does not exist, then the decoder must find solutions σ ₁ and σ ₂ that satisfy the simultaneous equations (10) for e=2. Note that if no solution is obtained here, it is assumed that e≧3. The solution σ ₁ of equation (9) is obtained as σ ₁ =S ₁ /S ₀ =S ₂ /S ₁ =S ₃ /S ₂ , and the solutions σ ₁ and σ ₂ of equation (10) are obtained as σ ₁ =S ₀ S ₃ +S ₁ S ₂ /S ₁ ² +S ₀ S ₂ ,σ ₂ =S ₁ S ₃ +S ₂ ² /S ₁ ²
Find it as +S ₀ S ₂ . () Once the coefficient σ _i of the error location polynomial has been obtained as described above, the roots of the error location polynomial are then determined using equation (7). First, when e=1, σ(x)=x+σ ₁ =0, ∴X ₁ =σ ₁ . In addition, in the case of e=2, σ(x)=x ^{2 +} _{σ 1} All you have to do is find the solution, and now find this root.
Let X ₁ and X ₂ be. () Once the roots of the error location polynomial have been found, the error value Y _j is then found using equation (6). First, when e=1, S ₀ =Y ₁ ∴Y ₁ =S ₀ . Also, in the case of e=2
S ₀ = Y ₁ + Y _{2 S 1} = _{Y 1} X ₁ + Y ₂ From X ₂ ∴Y ₁ = X _{2 S 0 +} S ₁ /X _{1 +} Error value Y ₁ ,
Correct by Y ₂ . By the way, if the value of the error location can be accurately known using the pointer erasure method or the like, it is possible to correct up to quadruple errors using the Reed-Solomon code for double error correction described above. This is [Method B], which will be described later. [Method B] () Calculate syndromes _S0 to _S3 . () () Know the error location using another detection method. () Calculate the error value using equation (6). First, in the case of e=1 and e=2, it is the same as () of the above-mentioned [method A]. Then, in the case of e=3, S ₀ = Y ₁ + Y ₂ + Y ₃ ^S ₁ = Y ₁ X _{1 +} Y ₂ X _{2 +} Y ₃ X ₃ S ₂ = Y _{1 X 1} ² + ^Y ₂ Solve Y ₁ = (S ₂ + X ₃ S ₁ ) + X ₂ (S ₁ + X ₃ S ₀ ) _/ (X _{1 +}
+X ₃ ) Y ₂ =(S ₁ +X ₃ S ₀ )+Y ₁ (X ₁ +X ₃ )/(X ₂ +X ₃ ) Y ₃ =S ₀ +Y ₁ +Y ₂ . Also, in the case of e=4, S ₀ =Y ₁ +Y ₂ +Y ₃ +Y ₄ S ₁ =Y ₁ X ₁ +Y ₂ X ₂ +Y _{3 X 3} +Y _{4 X 4} ^S ₂ = _{Y 1} ² +Y ₃ ^X ₃ ² ₊ ^Y ₄ X ₄ ² _{S 3} =Y ₁ X ₁ ³ _{+ Y 2 X 2} ³ _{+ Y 3 3} + (S ₁ X ₄ + S ₂ )}X ₂ + (S ₁ X ₄
+S ₂ )X ₃ +(S ₂ X ₄ +S ₃ )/(X ₁ +X ₂ )(X ₁ +X ₃ )(X ₁ +
X ₄ ) Y ₂ = (S ₀ X ₄ + S ₁ ) X ₃ + (S ₁ X ₄ + S ₂ ) + Y ₁ (X ₁ + X ₃ )
_{( X 1} +X ₄ )/ ₍ X ₂ +X ₃ ) (X ₂ + _{X 4} ) _{Y 3 = ( S 0}
(X ₃ +X ₄ ) Y ₄ =S ₀ +Y ₁ +Y ₂ +Y ₃ . () Correction is made using Y ₁ to _{Y 4} obtained as described above. FIG. 1 is a schematic configuration diagram showing an error correction circuit which is an actual Reed-Solomon code decoding system based on the above principle. That is, the data to be corrected (of course Reed-Solomon code is used for error correction) led through the input terminal (IN) is divided into two parts, one of which is used as a data buffer during the decoding operation described later. 11, and the other one is led to the syndrome calculator 12 and below for decoding operations. The syndrome calculated by the syndrome calculator 12 is stored in the syndrome buffer 13. Here, the OR gate 14 connected to the output part of the syndrome buffer 13 indicates the presence or absence of an error, and if there is an error, an error correction operation is started according to the procedure described above. In other words, the error location polynomial calculator 15
calculates the coefficients of the error location polynomial σ(x), the error location calculator 16 calculates the roots of the error location polynomial, the error value calculator 17 calculates the error value, and these error locations and The data output from the data buffer 11 is corrected based on the error value. By the way, each of the calculators 12, 15, 16, and 17 of such a decoding system detects whether or not it is 0 and performs necessary algebraic operations such as addition, multiplication, and division. Conventionally, an error location polynomial calculator (Japanese Patent Publication No. 56-20575) constructed as shown in FIG. 2 is known. That is, in FIG. 2, 21 is a syndrome buffer, which is a RAM for storing the syndrome S _i .
Each syndrome, which is an element of the Galois field GF (2 ^m ), is stored in m-bit binary format. Further, 22 is a work buffer, which is used to store intermediate results and final results of algebraic operations when calculating the coefficients of the error location polynomial.
Partial results used in later calculations are also stored in the working buffer 22. 23 is a sequence control device for instructing the order of algebraic operations, and the syndrome buffer 2
1 and working buffer 22 to access appropriate storage locations;
It is used to check the result of the algebraic operation executed and branch to the next appropriate operation. Furthermore, 24 and 25 are each Galois field GF
These are a logarithm buffer and an antilog buffer consisting of ROMs that store the original logarithm and antilog of (2 ^m ) separately in the form of tables. Here, the address of the former logarithm buffer 24 is the binary representation of the element α ⁱ , and its entry is the logarithm of α with α as the base, that is, i, but the entry at the address i of the latter logarithm buffer 25 is This is the binary representation of α ⁱ . For example, if the modulus polynomial F(x) of the Galois field GF(2 ⁸ ) is F(x) = x ⁸ + x ⁶ + x ⁵ + x ⁴ + 1, then the elements other than 0 are the powers of the root α of F(x) = 0. or a linear combination from α ⁰ to α ⁷
₇ 〓 ⁱ⁼⁰ a _i α ⁱ (however, a _i =0 or 1). Furthermore, in this case, eight coefficients from a ₀ to a ₇ can be extracted and expressed as a binary vector. For example, α ¹ =0・α ⁰ +1・α ¹ +0・α ² +0・α ³ +0・α ⁴
+0・α ⁵ +0・α ⁶ +0・α ⁷ = (01000000) α ⁷ =0・α ⁰ +……+0・α ⁶ +1・α ⁷ = (00000001) α ⁸ =1+α ⁴ +α ⁵ +α ⁶ (10001110) α ⁹ =α・α ⁸ =α+α ⁵ +α ⁶ +α ⁷ (01000111), and elements other than these can be expressed as vectors in the same way. In this case, the logarithm table address 1~
255 is an 8-bit binary vector representation of element α ⁱ ,
The corresponding entry is the binary representation of index i. Further, the antilog table uses the index i as an address, and the entry is a binary vector representation of α ⁱ . Next, the actual algebraic operations performed by the error location polynomial calculator shown in FIG. 2 will be explained separately. (1) Addition When elements α ⁱ and α ^j are added, these two elements are subjected to an exclusive OR gate 27 via the A register 20 and the B register 26 for each bit. The result of the sum of the two elements thus obtained is transferred to the working buffer 22 via the C register 19. (2) Detection of whether or not element α ⁱ is 0 When checking whether element α i is 0, element α ⁱ
are logically summed by the OR gate 29 via the H register 28. This result is transferred to the working buffer 22 via the M register 30. In this case, the contents of the M register 30 become 0 only when the element α ⁱ is 0. (3) Multiplication When multiplying elements α ⁱ and α ^j , first it is checked whether these two elements are 0 or not. If,
If either element is 0, the multiplication result is 0 without actually needing to be multiplied. However, if both are non-zero, these elements are sequentially loaded into the address register 31 for the logarithmic buffer 24. Then, the outputs i and j from the logarithm buffer 24 are converted to 2 ⁸ −
One's complement addition is performed modulo one. This results in the result i+j=t mod (2 ⁸ -1)
is the above antilog buffer 25 via the L register 35.
is loaded into the address register 36 for. In this case, if the address input of the antilog buffer 25 is t, the output α ^t is the multiplication result of the G register 3.
7 to the working buffer 22. (4) Division The division of α ⁱ by the element α ^j (α ⁱ /α ^j ) is basically the same as the multiplication in (3) above, but the contents of the E register 33 are transferred to the D register 32. They differ in that they are subtracted from the content. That is, the logarithm of element α ^j in the E register 33 is complemented by the complement converter 38 and sent to the one's complement adder 34 via the F register 39. and,
The following processing is performed in the same manner as in the case of multiplication (3), but in this case, the output of the antilog buffer 25 is the result of the division, that is, the quotient. [Problems with Background Art] However, the conventional error correction device as described above requires a logarithm buffer and an antilog buffer for multiplication and division among the algebraic operations in the error location polynomial calculator. However, the memory capacity of the ROM and other devices used for this purpose was enormous, which hindered LSI implementation and resulted in the problem of having to attach large-capacity external memory. This is 255 x 8 bits = 2040 bits when one symbol is 8 bits as in the example above.
This can be easily seen from the fact that two ROMs are required, totaling 4080 bits. In other words, conventionally known multipliers and dividers in Galois fields require logarithm buffers and antilog buffers consisting of large-capacity memories that store the logarithms and antilogarithms of these elements separately in the form of tables. Therefore, there was a problem in that the configuration was complicated and the price was high. [Purpose of the Invention] The present invention has been made in view of the above points, and provides an object to perform multiplication in the Galois field without using logarithm buffers or antilog buffers that require particularly large amounts of memory. It is an object of the present invention to provide an extremely good multiplication device in a Galois field that can contribute to simplifying the configuration and reducing the cost. [Summary of the Invention] That is, the multiplication device in a Galois field according to the present invention is a generator polynomial G(x) of a Galois field GF(2 ^m ).
Multiplicand data B(α) where α is the first root of
(α)=b _n-1 α ^m-1 +b _n-2 α ^m-2 +……+b ₀ ) and multiplier data C(α) (however, C(α)=c _n-1 α ^m-1 +c _n-2
α ^m-2 +……+c ₀ ) is multiplied by B(α)・C(α)=αB
(α) + B (α) (However, =c _n-1 α ^m-2 +c _n-2
α ^m-4 +c _n-3 α ^m-6 +……+c ₁ , =c _n-2 α ^m-2 +c _n-4
α ^m-4 +c _n-6 α ^m-6 +…+c ₀ ), the first partial multiplication [αB (α)] and the second partial multiplication [B (α)
], the first means processes the first partial multiplication in a first step, and the second means processes the second partial multiplication in a second step. and a third means for adding the partial multiplication outputs of the first and second means, it is possible to significantly simplify the configuration by making it hardware, and to make the basic clock in two steps. The feature is that the processing time can be shortened by making the processing possible. [Embodiments of the invention] First, an optical type (CD type) to which this invention is applied
An overview of a digital audio disc (DAD) playback device will be explained. That is, as shown in FIG. 3, the turntable 1 is rotated by a disk motor 111.
A disk 113 mounted on the optical pickup 112 is played back by an optical pickup 114. in this case,
The optical pickup 114 is a semiconductor laser 114.
A beam splitter 114b transmits the light emitted from the
It illuminates the signal surface of the disk 113 through the objective lens 114c, and corresponds to the digitized (PCM) data of the audio signal to be reproduced that is recorded on the disk 113 in a form with predetermined (EFM) modulation and interleaving. The reflected light from the pits (irregularities with different reflectances) is reflected by the objective lens 11.
4c, the beam splitter 114b leads to a 4-split photodetector 114d, and the 4 playback signals photoelectrically converted by the 4-split photodetector 114d can be outputted to the outside, and from the beam splitter 114b to a pick-up feed motor 115. Therefore, the disk 113 is linearly driven in the radial direction. The four reproduced signals from the four-division photodetector 114d are then supplied to the matrix circuit 116 and subjected to predetermined matrix calculation processing, thereby generating a focus error signal (F), a tracking error signal, and a high frequency signal (RF). separated into Of these, the focus error signal (F) is used together with the focus search signal from the focus search circuit 110 to drive the focus servo system (FS) of the optical pickup 114. Further, the tracking error signal (T) is used to drive the tracking servo system (TS) of the optical pickup 114 and the pickup feed motor 115 together with a search control signal given via the system controller 117 (described later).
(linear tracking). The remaining high frequency signal (RF) is then supplied to the reproduction signal processing system 118 as the main reproduction signal component.
That is, the reproduced signal processing system 118 first passes the reproduced signal to the slice level (eye pattern) detector 1.
19 to separate unnecessary analog components and necessary data components, and only the data components are sent to a PLL-type synchronous clock regeneration circuit 121 and a first signal processing system 122. The signal is supplied to the edge detector 122a. Here, the synchronous clock from the synchronous clock regeneration circuit 121 is guided to the synchronous signal separation clock generation circuit 122b in the first signal processing system 122 for data demodulation, and is used to generate a synchronous signal separation clock. . On the other hand, the reproduced signal that has passed through the edge detector 122a is guided to a sync signal detector 122c, where the sync signal is separated by the sync signal separation clock, and then guided to a demodulation circuit 122d (EFM).
demodulated. Among these, the synchronization signal is transmitted to the synchronization signal protection circuit 122.
The signal is guided to the input data processing timing signal generation circuit 122f together with the synchronization signal separation clock through the signal line e in a state where it is protected from malfunction. Also, the demodulated signal is transmitted to the data bus input/output control circuit 1.
A second signal processing system 123 to be described later via 22g
is supplied to the input/output control circuit 123a of
The control signal and display signal components, which are subcodes, are sent to the control display processing circuit 1.
22h and subcode processing circuit 122i. The subcode data subjected to necessary error detection and correction by the subcode processing circuit 122i is sent to the system controller 117 via the system controller interface circuit 122q.
is supplied to Here, the system controller 117 includes a microcomputer, an interface circuit, a driver integrated circuit, etc., and controls the DAD playback device to a desired state by command signals from the control switch 124, and also controls the above-mentioned subcode ( For example, the display 125 is used to display the index information of the played music on the display 125. The timing signal from the input data processing timing signal generation circuit 122f is provided to control the data bus input/output control circuit 122g via the data selection circuit 122j, and is also used to control the data bus input/output control circuit 122g. 1
22l and PWM modulator 122m to drive the disc motor 111 at constant linear velocity (CLV).
Automatic frequency control (AFC) for driving
and automatic phase control (APC). In this case, the phase detector 122l is supplied with a system clock from a system clock generation circuit 122p which operates based on an oscillation signal from a crystal oscillator 122n. The demodulated data passing through the input/output control circuit 123a of the second signal processing circuit 123 is sent to the syndrome detector 1 for error detection and correction or correction.
23b, an error pointer control circuit 123c, a correction circuit 123d, and a data output circuit 123e.
A) Derived to converter 126. In this case, the external memory control circuit 123f cooperates with the data selection circuit 122j to select the external memory 127 in which data necessary for correction is written.
By controlling the above input/output control circuit 12
3a, data necessary for correction is taken in. Further, the timing control circuit 123g is configured to supply timing control signals necessary for error correction and correction and D/A conversion based on the system clock from the system clock generation circuit 122p. Additionally, the mutating (detection) control circuit 123
h performs predetermined muting control necessary for error correction and for starting and ending the operation of the DAD playback device, based on the output from the error pointer control circuit 123c or the control signal given via the system controller 117. It is offered to Then, the audio signal converted back to an analog signal by the D/A converter 126 is passed through a low-pass filter 128 and an amplifier 129, and then sent to a speaker 130 for sounding. Next, an error correction circuit applied to the DAD playback device as described above will be explained. First, to explain the principle, the Galois field GF
When expressed as a polynomial, the double-corrected BCH code in (2 ⁸ ) can be expressed as U ₀ , U ₁ , U ₂ ... U _n-1 , P ₀ , P ₁ , P ₂ , P ₃ ... (21) . However, it is assumed that U ₀ to _{U n-1} are information symbols, and m symbols each having 8 bits are grouped together. It is also assumed that P ₀ to _{P 3} are parity symbols, and four parity symbols are added to the m information symbols. In other words, the expression (21) is based on the fact that the parity symbol can be corrected to be the same as the information symbol, and this means that W _n+3 , W _n+2 , W _n+1 ...W ₃ , W ₂ , W ₁ , W ₀ ...(22). As a result, the transmission polynomial F(x) is F(x)=W _n+3 x ^m+3 +W _n+2 x ^m+2 +...+W ₁ x+W ₀ ...(
23) and the receiving polynomial F
(x)′ is F(x)′=W _n+3 ′x ^m+3 +W _n+2 ′x ^m+2 +……+W ₁ ′x
+W ₀ ...(24) It can be expressed as follows. Here, the generator polynomial G(x) of the Galois field GF(2 ⁸ )
If the 1st root of is α, then the above F(x) is revised 2nd
Since the BCH code has four roots of 1, α, α ² , α ³ , F(1)= _n+1 〓 ⁱ⁼⁰ W ₁ =0 F(α)= _n+3 〓 ^{i= 0} W _i α ⁱ =0 F(α ² )= _n+3 〓 ⁱ⁼⁰ W _i (α ² ) ⁱ =0 F(α ³ )= _n+3 〓 ⁱ⁼⁰ W _i (α ³ ) ⁱ = 0 (25). In other words, on the transmitting side, parity symbols are determined and transmitted so as to satisfy equation (25) above, but on the receiving side, due to the intervention of the transmission system, the parity symbols cannot necessarily be received in their original form. is corrected as an error. In this case, according to the double correction BCH code described above, it is possible to correct up to two symbol errors out of a total of m+4 symbols. Now, suppose that an error occurs in the two symbols W _i and W _j in the above receiving polynomial, resulting in W′ _i =W _i +e _i W′ _j =W _j +e _j . In this case, it is assumed that symbols other than W' _i and W' _j have no errors and are expressed as W' _k =W _k (where k=0 to m+4 k≠i, k≠j). Here, if we substitute 1, α, α ² and α ³ for the receiving polynomial F'(x) in the same way as when transmitting, we get
F′(1)=e _i +e _j =S ₀ F′(α)=e _i α ^j +e _j α ^j =S ₁ F′(α ² )=e _i α ²ⁱ +e _j α ^2j =S ₂ F′ (α ³ ) = e _i α ³ⁱ + e _j α ^3j = S ₃ (26). Here, S ₀ to _{S 3} are called syndromes, and in the case of two symbol errors, they have the information content of equation (26). By the way, in the case of double correction in BCH code theory, there is a method using the error location polynomial as described above, which is σ ₁ = α ⁱ + α ^j = S ₀ S ₃ +S ₁ S ₂ /S ₁ ² +S ₀ S ₂ ...(27) σ ₂ = α ⁱ α ^j = S ₁ S ₃ +S ₂ ² /S ₁ ² +S ₀ S ₂ ...(28) f(x)=x ² +σ ₁ x+σ ₂ ...(29 ). In other words, in (27) and (28), σ ₁ and σ ₂ are determined by the syndromes S ₀ to _{S 3} and substituted into equation (29), but in this case, for x in equation (29), Assume that α ⁰ to ^{α m+3} are substituted in order. Here, equation (29) should give f(x) = 0 at α ⁱ and α ^j , so if we find the point where f(x) = 0, we can obtain 2
It becomes possible to find the error location for each error. Next, since the method for finding the error pattern is known, from α ⁱ and α ^j , using equation (26) above, e _i =S ₀ α ^j +S ₁ /α ⁱ +α ^j ...(30A) e _j =S ₀ +e _i ...(30B). By the way, it is possible to perform multiplication and division in the Galois field, which are necessary when finding error locations (polynomials) and error patterns, with a hardware configuration without using the aforementioned large-capacity memory. This is the aim of this invention. However, in this case, even if multiplication and division in the Galois field with g(x) as the generator polynomial are performed without using a large capacity memory, although the multiplication can be performed relatively easily as described below, Since division is still difficult, it is desirable to reduce division as much as possible. Therefore, the method for determining the error location and error pattern described above will be developed in a direction that reduces the number of divisions. First, regarding the generation of the error location (polynomial), since the denominators of the right-hand sides of equations (27) and (28) above are equal,
S _a = S ² ₁ + S ₀ S ₂ S _b = S ₀ S ₃ + S ₁ S ₂ S _c = S ₁ S ₃ + S ² ₂ ...If we set it as (31), we get equations (27) and (28). is as follows: σ ₁ = α ⁱ + α ^j = S _b /S _a ...(32) σ ₂ = α ⁱ α ^j = S _c /S _a ...(33). Substituting these equations (32) and (33) into equation (29) yields f(x)=x ² +S _b /S _a x+S _c /S _a ...(34). Since the error location can be found in equation (34) by substituting α ⁰ to α ^m+3 for x and checking that f(x) = 0, we can transform it as follows. Even if f′(x)=S _a f(x)=S _a x ² +S _b x+S _c ……(35), by substituting α ⁰ to α ^m+3 for f′(x), α ⁱ and α ^j should be found at the point where f′(x)=0. In other words, it is possible to eliminate division when determining the error location polynomial in this way. Next, regarding the generation of error patterns, regarding the division (S ₀ α ^j + S ₁ /α ⁱ + α ^j ) required to obtain e _i using the above equation (30A), the denominator α ⁱ +
If the reciprocal of α ^j (α ⁱ + α ^j ) ^-1 is known in advance, then e _i = (S ₀ α ^j + S ₁ ) (α ⁱ + α ^j ) ^-1 ……(30A′) becomes possible. Next, let's look at how to find the reciprocal (α ⁱ + α ^j ) ^-1 . If we insert equation (32) into equation (35) above, we get f'(x) = S _a x ² + S _a (α ⁱ +α ^j )x+S _c ...(36). The operation of substituting α ⁰ to α ^m+3 into x in equation (36) is necessary to obtain the above error location, but substituting α ⁰ to ^{α m+3} In the meantime, we focus on the term S _a (α ⁱ + α ^j )x in equation (36) and perform an operation to find x such that S _a (α ⁱ + α ^j )x=α ^r ...(37). Specifically, if m = 28 now, x in equation (37)
will be assigned from α ⁰ to α ³¹ , but in the Galois field GF(2 ⁸ ), α ^28-1 = α ²⁵⁵ = 1 is the maximum, and in this case it is a cyclic code from α ⁰ to α ²⁵⁴ . Only α ⁰ to α ²⁵⁴ are handled. Since we are now substituting α ⁰ to α ³¹ , from 7 < 255/32 < 8, α ^32m → α ^-32m (however, m
The eight reciprocal data up to =0, 1...7) are coded as shown in the table below.

〔Effect of the invention〕

Therefore, as detailed above, according to the present invention, it is possible to perform multiplication in a Galois field without using a logarithm buffer or an antilog buffer that requires a large capacity memory, thereby simplifying the configuration and It becomes possible to provide an extremely good multiplication device in a Galois field that can contribute to cost reduction.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram showing an error correction circuit comprising a Reed-Solomon code decoding system, Fig. 2 is a block diagram showing a conventional error location polynomial calculator, and Fig. 3 is a DAD playback to which this invention is applied. 4 is a configuration diagram showing a specific example of the error correction circuit shown in FIG. 3; FIG. 5 is a timing chart for explaining a specific example of the operation shown in FIG. 4; FIG. The figure is a block diagram showing a multiplication device provided in the arithmetic unit section of FIG. 4 as an embodiment of the present invention, FIG. 7 is a timing chart for explaining a specific example of the operation of FIG. 6, and FIG. , FIG. 9 is a block diagram showing a specific example of the α multiplication circuit and the α ² multiplication circuit shown in FIG. 51, 52, 66, 68...Latch circuit, 53...
α multiplication circuit, 54, 55, 56, 59, 62, 6
5... Select circuit, 57, 60, 64... α ² multiplication circuit, 58, 61, 63, 67... Exclusive OR circuit.

Claims (1)

[Claims] 1 1 of the generator polynomial G(x) of the Galois field GF(2 ^m )
Multiplicand data B(α) whose root is α (however, B(α)
=b _n-1 α ^m-1 +b _n-2 α ^m-2 +……+b ₀ ) and multiplier data C(α) (however, C(α)=c _n-1 α ^m-1 +c _n-2 α ^m-2
+……+c ₀ ) is multiplied by B(α)・C(α)=αB(α)
+B(α) (However, =c _n-1 α ^m-2 +c _n-2 α ^m-4 +c _n-3 α ^m-6 +……+c ₁ , =c _n-2 α ^m-2 +c _{n- 4} α ^m-4 +c _n-6 α ^m-6 +……+c ₀ ) Converting to the form of the sum of the first partial multiplication [αB (α)] and the second partial multiplication [B (α)] a first means for processing said first partial multiplication in a first step; a second means for processing said second partial multiplication in a second step; A multiplication device in a Galois field, comprising: third means for adding the partial multiplication outputs of the second means.