JPS624879B2 - - Google Patents
Info
- Publication number
- JPS624879B2 JPS624879B2 JP4337782A JP4337782A JPS624879B2 JP S624879 B2 JPS624879 B2 JP S624879B2 JP 4337782 A JP4337782 A JP 4337782A JP 4337782 A JP4337782 A JP 4337782A JP S624879 B2 JPS624879 B2 JP S624879B2
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- punched
- wiring board
- printed circuit
- product size
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 5
- 230000037431 insertion Effects 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 238000004080 punching Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
Landscapes
- Punching Or Piercing (AREA)
Description
本発明は印刷回路板の製造法に関する。
印刷回路板を製造する場合、印刷配線板への部
品自動挿入およびはんだ付け工程の合理化のため
に印刷配線板で１ケづつ単独に打抜加工せずに複
数枚の印刷配線板をマザーボードと称する大型基
板の中に納めて作業している。この場合、まず部
品挿入穴等を打抜加工すると同時に、印刷配線板
の製品サイズ外形を打抜き、再び打抜かれたあと
に印刷配線板を嵌合し、この状態で部品挿入、は
んだ付けなど必要な工程を流し印刷回路板を製造
し、最後に機械または手作業で各々の印刷回路板
を取り出している。
マザーボードに納められる複数枚の印刷配線板
の製品サイズ外形を打抜き、再び、打抜かれたあ
とに印刷配線板を嵌合するには、プツシユバツク
金型が用いられているが、プツシユバツクによる
打抜嵌合する段階で発生するヒズミでマザーボー
ドのそりが大きく発生し、部品の自動挿入等でト
ラブルが生じる。
本発明はこのような点に鑑みてなされたもの
で、一枚の印刷配線板用基板の中で、複数枚の印
刷配線板の製品サイズ外形を打抜き、再び打抜か
れたあとに印刷配線板を嵌合し、この状態で部品
挿入、はんだ付けなどの必要な工程を経る印刷回
路板の製造法に於て、印刷配線板を打抜かれた箇
所に嵌合するに先立つて印刷配線板の製品サイズ
外形の外側にスリツト又は一連の打抜穴を設ける
ことを特徴とするものである。
すなわち本発明はプツシユバツク加工時の打抜
嵌合する段階で発生するヒズミによるそりを低減
させるために印刷配線板の打抜外形の外側にスリ
ツトや打抜穴を作ることによつてヒズミを除き、
マザーボードのそりを低減することにある。
印刷配線板を打抜かれた箇所に嵌合するに先立
つて、印刷配線板の製品サイズ外形の外側にスリ
ツト又は一連の打抜穴を設けるには、印刷配線板
を打抜くと同時に、スリツト又は一連の打抜穴を
打抜くのが好ましい。更にこの時同時に、印刷配
線板に必要な貫通孔等を打抜くことが好ましい。
しかしながら、スリツト又は一連の打抜穴は、
印刷配線板を打抜く前に設けておいても良い。
スリツト又は一連の打抜穴を設けるには、打抜
きのみならず、ドリル等によつても行うことが出
来る。
実施例
紙フエノール片面銅張り積層板を用いて、基板
サイズ150×200mm内に４面の印刷配線板（120×
35mm）を保有する印刷配線板をまず部品挿入穴の
打抜加工時に製品サイズに打抜くと共に４面の印
刷配線板の周囲に一連の打抜穴を作る。このあと
印刷配線板を、打抜き箇所に嵌合した。
比較例
印刷配線板の周囲に一連の打放穴を作ることな
く、印刷配線板の打抜き、嵌合を行つた。
実施例、比較例で仕上つた印刷配線板のそりを
測定した結果は別表のとうりであり実施例の方式
でプツシユバツク加工をしたものがそりが小さく
仕上つている。
The present invention relates to a method for manufacturing printed circuit boards. When manufacturing printed circuit boards, multiple printed wiring boards are called a motherboard instead of being punched out individually in order to automatically insert parts into the printed wiring board and to streamline the soldering process. I am working inside a large board. In this case, first punch holes for component insertion, etc., and at the same time punch out the product size outline of the printed wiring board. After being punched out again, the printed wiring board is fitted, and in this state, necessary parts such as parts insertion and soldering are performed. Printed circuit boards are manufactured through a series of steps, and each printed circuit board is finally removed by machine or hand. A pushback mold is used to punch out the product size outline of multiple printed wiring boards to be housed in the motherboard and then fit the printed wiring boards together after being punched out again. The distortion that occurs during this process can cause major warping of the motherboard, causing trouble when automatically inserting parts, etc. The present invention has been made in view of these points, and the product size outlines of a plurality of printed wiring boards are punched out from a single printed wiring board substrate, and the printed wiring boards are punched out after being punched out again. In the manufacturing method of printed circuit boards, in which the printed circuit boards are mated and then go through necessary processes such as parts insertion and soldering, the product size of the printed circuit boards is It is characterized by a slit or a series of punched holes on the outside of the profile. That is, the present invention eliminates warpage by forming slits or punched holes on the outside of the punched outline of the printed wiring board in order to reduce warpage due to distortion that occurs during the punching and fitting stage during pushback processing.
The purpose is to reduce warpage of the motherboard. To provide a slit or series of punched holes on the outside of the product size outline of the printed wiring board prior to fitting the printed wiring board into the punched area, the slit or series of punched holes may be formed at the same time as the printed wiring board is punched. Preferably, punch holes are punched out. Furthermore, at the same time, it is preferable to punch out necessary through holes and the like in the printed wiring board. However, a slit or series of punched holes
It may be provided before punching out the printed wiring board. The slit or series of punched holes can be provided not only by punching but also by drilling or the like. Example Using a paper phenol single-sided copper-clad laminate, four printed wiring boards (120×
35mm) is first punched out to the product size during the punching process for component insertion holes, and a series of punched holes are created around the printed wiring board on all four sides. After this, the printed wiring board was fitted into the punched out area. Comparative Example A printed wiring board was punched and fitted without making a series of punch holes around the printed wiring board. The results of measuring the warpage of the printed wiring boards finished in Examples and Comparative Examples are shown in the attached table, and the warpage was smaller when the printed wiring boards were subjected to pushback processing using the method of Examples.
【表】
以上説明したように本発明に於ては、プツシユ
バツク打抜加工時のそりを低減することが出来
る。[Table] As explained above, according to the present invention, warping during pushback punching can be reduced.
Claims (1)
刷配線板の製品サイズ外形を打抜き、再び打抜か
れたあとに印刷配線板を嵌合し、この状態で部品
挿入、はんだ付けなどの必要な工程を経る印刷回
路板の製造法に於て、印刷配線板を打抜かれた箇
所に嵌合するに先立つて印刷配線板の製品サイズ
外形の外側にスリツト又は一連の打抜穴を設ける
ことを特徴とする印刷回路板の製造法。 ２ スリツト又は一連の打抜穴を、印刷配線板の
製品サイズ外形を打抜くと同時に打抜くことを特
徴とする特許請求の範囲第１項記載の印刷回路板
の製造法。[Claims] 1. The product size outlines of multiple printed wiring boards are punched out from a single printed wiring board substrate, and after being punched out again, the printed wiring boards are fitted together, and in this state, the parts are assembled. In the method of manufacturing printed circuit boards that involves necessary steps such as insertion and soldering, a slit or a series of slits are formed on the outside of the product size outline of the printed wiring board before the printed wiring board is fitted into the punched area. A method of manufacturing a printed circuit board characterized by providing punched holes. 2. A method for manufacturing a printed circuit board according to claim 1, characterized in that the slit or a series of punched holes are punched at the same time as the product size outline of the printed circuit board is punched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4337782A JPS58159392A (en) | 1982-03-17 | 1982-03-17 | Method of producing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4337782A JPS58159392A (en) | 1982-03-17 | 1982-03-17 | Method of producing printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58159392A JPS58159392A (en) | 1983-09-21 |
| JPS624879B2 true JPS624879B2 (en) | 1987-02-02 |
Family
ID=12662128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4337782A Granted JPS58159392A (en) | 1982-03-17 | 1982-03-17 | Method of producing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159392A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439080U (en) * | 1990-07-27 | 1992-04-02 | ||
| JP2008263225A (en) * | 2008-07-07 | 2008-10-30 | Dainippon Printing Co Ltd | Printed wiring board manufacturing equipment |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62257787A (en) * | 1986-04-30 | 1987-11-10 | 富士通株式会社 | Multiple forming of module printed boards |
| JPH0360091A (en) * | 1989-07-27 | 1991-03-15 | Kokusai Electric Co Ltd | Push-back method |
| JPH07105581B2 (en) * | 1990-10-29 | 1995-11-13 | 日立エーアイシー株式会社 | Method for manufacturing printed wiring board |
-
1982
- 1982-03-17 JP JP4337782A patent/JPS58159392A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439080U (en) * | 1990-07-27 | 1992-04-02 | ||
| JP2008263225A (en) * | 2008-07-07 | 2008-10-30 | Dainippon Printing Co Ltd | Printed wiring board manufacturing equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58159392A (en) | 1983-09-21 |
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