JPS624896B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a locking method for reliably locking a PLL (Phase Locked Loop) to an input signal within a lock range.

The PLL uses a voltage controlled oscillator (hereinafter referred to as VCO)
There is a capture range centered around the free-running frequency of the device, which transitions from a non-lock state to a lock state if the frequency of the input signal is within this range, and a range in which the device can maintain the lock state once it locks to the input signal. The lock range that can be achieved is defined. Commercially available PLL ICs vary depending on how they are used, but the capture range uses VCO.
The lock range is about ±10% of the free-running frequency of the VCO, and the lock range is about ±10% of the free-running frequency of the VCO. Therefore, there was a drawback that the PLL could not lock onto an input signal whose frequency fluctuation range was outside the capture range, and the PLL could not function.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL locking method that eliminates the above drawbacks and allows the PLL to lock to the input signal even if the frequency fluctuation range of the input signal is outside the capture range as long as it is within the lock range. shall be.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example in which the present invention is implemented in a toner density controller for a copying machine. The power supply section 11 is a circuit that generates positive and negative power supplies +Vcc and -Vcc from one power supply input, and is composed of resistors R1 and R2, an operational amplifier _u1 , transistors TR1 and TR2, and a capacitor C1.
Positive and negative power supplies determined by the voltage division ratio of resistors R1 and R2 with the ground potential as a reference; in this example, R ₁ = R ₂
As a result, a ±6V power supply is created from a 12V input voltage. The oscillator 12 consists of a transistor TR3, a coil L, capacitors _C2 , _C3 , and resistors _R3 to _R6 .
It is a Colpitts type oscillator that oscillates at a frequency determined by capacitors C ₂ and C ₃ and coil L. The coil L is installed in the developer flow path of the developing device of the copying machine, and the inductance of the coil L changes depending on the mixing ratio of the developer, which is a mixture of iron powder and toner, that is, the toner concentration, and the oscillator 12 changes according to the toner concentration. oscillates at a frequency. FM demodulator 13 is PLL
An IC (NE565A, manufactured by Signetakes) 14 is used, and the output of the oscillator 12 is input to the PLL 14 via a coupling capacitor C4. In this demodulator 13, resistors R7 and R8 are connected to the PLL 14.
constitutes an input bias circuit with diodes D1,
D2 constitutes an amplitude limiter and functions to protect the input circuit. Resistors R9, R10 and capacitor C5 are elements that determine the free running frequency of the VCO in PLL14, and by varying the resistance R9,
VCO by varying the current of the time constant circuit in VCO
By varying the free running frequency of the FM demodulator 13, the output level of the FM demodulator 13 can be changed and the toner concentration can be adjusted. Buffer 1 after FM demodulator 13
5. As is clear from the integrator 16, the output of the final stage swings from the +Vcc side to the -Vcc side with 0V as the reference, so when the toner concentration is a predetermined value, the output of the PLL 14, that is, the 6th and 7th terminals. Resistor R9 is adjusted so that the voltage between them is 0V. Capacitor C
6 and C7 constitute a low pass filter of the feedback loop of the PLL 14, and are for stabilizing the control loop. The buffer 15 includes an operational amplifier u ₂ , a capacitor C8, and resistors R11 to R14, and buffers the output of the PLL 14 so as not to overload it. The integrator 16 consists of an operational amplifier u ₃ , a capacitor C9, and resistors R15 and R16, and receives the output of the buffer 15.
Level detection is performed by integrating with 0V as a reference. It is PLL1 that performs level detection by integrator 16.
This is because the output of No. 4 includes ripples, and because the output includes ripples due to poor circulation of the developer, and to avoid output caused by high frequency ripples. Although the part where toner is replenished into the developer of the developing device is not shown here, when the output of the integrator 16 is at a low level, the bottle containing replenishment toner is rotated, and the dense toner is poured into the developing tank. It is structured to guide you.

PLL (NE565A) 14 in adjusting resistor R9
Based on the characteristics of the oscillator 12 at a predetermined toner concentration,
When the oscillation frequency r of the VCO matches the free running frequency o of the VCO, the voltage between terminals 6 and 7 of the PLL14 is not necessarily 0V, but is up to 200V from the catalog value.
Since it has an offset of mV, this maximum
It becomes necessary to adjust the free-running frequency o by changing the resistor R9 so as to cancel the voltage of 200 mV. The amount of adjustment is determined by the sensitivity of FM demodulation, and under the worst conditions, it is necessary to shift the free-running frequency o by 20% with respect to the oscillation frequency r. However, this
In PLL14, the capture range is approximately ±10
%, the locking range is approximately 60%, so if the free-running frequency o is shifted by 20%, the oscillation frequency r will deviate from the capture range by adjusting the free-running frequency o, so capacitor C1
If not, the PLL 14 would not lock onto the output signal of the oscillator 12 when the power is turned on, and a situation would arise in which the PLL 14 would not be able to function as a toner density controller. In this embodiment, a capacitor C1 is provided in parallel with a resistor R1 of the power supply section 11 to delay the rise of the positive power supply, thereby increasing the free-running frequency determining elements R9 and R10 of the VCO.
The rise of the voltage applied to the oscillator is made exponentially, and the charging current to the capacitor C5 decreases in the middle of the rise, and the free-running frequency o of the VCO is oscillated in a sweep manner to ensure that the PLL 14 uses the output signal of the oscillator 12. It is designed to lock. This state is shown by the alternating current component of the terminal voltage of the capacitor C5 at o in FIG. r in FIG. 3 is the output waveform of the oscillator 12, and since a predetermined voltage is applied to the oscillator 12 when the power is turned on, it oscillates at a constant frequency r from the beginning. Figure 2 shows the relationship between r and o with frequency as the horizontal axis.
As mentioned above, o may become higher than r and exceed the capture range. Even in this case, if o is swept as shown in Figure 3, o will gradually move from a low frequency to a high frequency and pass r, or r will enter the capture range and the PLL 14 will be in a locked state. . Once the PLL 14 is in the locked state, it operates within the lock range shown by the chain line in FIG. 2, so it can operate reliably even against large fluctuations in r caused by ripples in the flow of toner.

The above PLL is NE565A made by Signateix.
Although an example using PLL has been described, the present invention is applicable to PLL in general. This is especially necessary when the frequency shift band of the input is wide, such as when used in a motor speed control device or a toner density controller of a copying machine, and the PLL can perform reliable control. If the power supplies for the oscillator 12 (or signal receiver) and the PLL 14 are different, it is sufficient to sweep o of the PLL when the power supply that rises slowly rises.

As described above, according to the PLL locking method according to the present invention, power is supplied from the positive and negative power supplies, and a voltage change in one of the two power supplies changes the current in the time constant circuit in the VCO, causing the VCO to self-regulate. In a PLL whose running frequency changes, after the above power supply is turned on, the rise of one of the above power supplies is delayed to cause the VCO to sweep oscillate, so even if the frequency fluctuation of the PLL input signal is outside the capture range, it remains within the lock range. This allows the PLL to be locked, allowing the PLL to be used even when the input frequency varies widely.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a toner density controller to which the present invention is applied, and FIGS. 2 and 3 are diagrams for explaining the present invention. 11...Power supply section, C1...Capacitor, 13...
...FM demodulator, 14...PLL, R9, R10...
Resistor, C5...Capacitor, R17~R20...
Resistor, C10...capacitor, TR4...transistor, LED...light emitting diode, PTR...phototransistor.

Claims (1)

[Claims] 1. In a PLL in which power is supplied from positive and negative power supplies, and a voltage change in one of the two power supplies changes the current of a time constant circuit in the voltage controlled oscillator, and the free running frequency of the voltage controlled oscillator changes,
A PLL characterized in that after the power source is turned on, the rise of one of the power sources is delayed to cause the voltage controlled oscillator to sweep oscillate, thereby locking the PLL to an input signal within a lock range.
How to lock.