JPS624920B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a carrier color signal processing circuit in a PAL color television receiver, and provides a circuit particularly suitable for semiconductor integrated circuits. In the PAL system, the color difference signal (B-Y) signal and (R-Y) signal are
-Y) axis is subjected to quadrature two-phase modulation, and the (RY) signal is transmitted with its phase inverted every scanning line period. On the image receiving side, the PAL chroma signal (R- Y) Chroma signal component and (B-Y)
Separates into chroma signal components, supplies each to a (R-Y) demodulator and a (B-Y) demodulator, and (B-
Y) The demodulator has a local subcarrier of a predetermined phase and (R
-Y) The demodulator performs demodulation by inverting and adding local subcarriers of a predetermined phase to each line, obtaining (RY) and (B-Y) color difference signals from each, and further converting these into Synthesize (G-Y)
Obtaining color difference signals. The PAL color television system has the characteristic that it is relatively unaffected by phase distortion because it cancels the phase distortion (mainly differential phase) of the transmission system. FIG. 1 shows a system diagram of a conventional PAL color demodulation circuit using a delay line. In the figure, a chroma signal applied to an input terminal 1 is delayed by a delay line 2 for one scanning line period, and is further passed through an amplitude adjustment circuit 3 and a phase adjustment circuit 4 that adjust the amplitude and phase (delay time) to an adder 5 and The signal is added to the subtracter 6 and subjected to addition and subtraction processing together with the undelayed chroma signal. The (B-Y) chroma signal component obtained from the adder 5 and the (R-Y) chroma signal component obtained from the subtracter 6 are transmitted to a (B-Y) demodulator 8 and a (R-Y) demodulator 9, respectively. are demodulated by the (B-Y) local carrier for demodulation 10 and (R-Y) local subcarrier for demodulation 11, and the (B-Y) color difference signal and (R-Y) are output from the output terminals 13 and 14, respectively.
Obtain color difference signals. The (G-Y) color difference signal is obtained by combining the (B-Y) and (R-Y) color difference signals using a resistance matrix. Note that 7 is a carrier color signal processing circuit, and 12 is a demodulation circuit. To explain the operation of the carrier color signal processing circuit 7 in FIG. 1, consider the case where images of the same color are being transmitted on the screen. At this time, the chroma signal input terminal 1 in FIG. 1 has the vector shown in FIG.
PAL chroma signal is input. Now considering the Ln scanning line, adder 5 in Figure 1
A signal Fn shown in FIG. 2A is added to the subtracter 6 as a non-delayed chroma signal, and a signal Fn-1 shown in FIG. 2A is transmitted as a delayed chroma signal on a temporally preceding scanning line. The signals are added and addition and subtraction are performed, respectively. Here, the signals Fn-1, Fn, and Fn+1 shown in FIG. 2 are composed of the following components.

[Table] From equation (1), the adder output and subtracter output for Ln scanning lines are expressed as follows.

[Table] Equation (2) above is applied to the chroma signal input terminal 1.
This shows that the PAL chroma signal is separated into a (B-Y) chroma signal component and a (R-Y) chroma signal component, respectively. Next, considering the time of Ln+1 scanning line, the adder 5 and subtracter 6 in FIG. 1 receive a signal Fn+1 shown in FIG. 2C as a non-delayed chroma signal and a signal Fn+1 shown in FIG. 2A as a delayed chroma signal, respectively. A signal called Fn is added. Therefore, the adder output and subtracter output for the Ln+1 scanning line are expressed as follows.

[Table] From equations (2) and (3) above, the (B-Y) chroma signal component is obtained as the output of the adder 5 in FIG. 1, and the output of the subtracter 6 is obtained for one scanning line period. It is understood that (RY) chroma components whose phase is reversed are obtained each time. An example of a specific circuit configuration of the carrier color signal processing circuit in FIG. 1 is shown in FIG. A chroma signal is applied to input terminal 1, delayed by one scanning line period in delay circuit 2 via resistor 23, and then applied to addition/subtraction circuit 25. On the other hand, a portion of the chroma signal applied to the input terminal 1 is applied to an addition/subtraction circuit 25 after its amplitude is adjusted by a variable resistor 24 . The coils 21 and 22 are used to match the phase of the chroma signal applied to the addition/subtraction circuit 25. The adder/subtracter circuit 25 constitutes a closed circuit with resistors 27, 28, 29, 30 and a transformer. The midpoint of the transformer 26 is grounded, and the connecting point of the resistors 27 and 28 outputs the addition output, that is, (B-Y). The chroma signal component is
Further, a subtracted output, that is, a (RY) chroma signal component is obtained from the connection point between the resistors 29 and 30. After the amplitude of each output is adjusted by amplifiers 31 and 32, it is applied to a demodulation circuit via output terminals 33 and 34. In the carrier color signal processing circuit shown in FIG. 3, the addition/subtraction circuit 25 includes a transformer 26 for inverting the phase of the chroma signal, and the carrier color signal processing circuit is integrated into a semiconductor integrated circuit. In this case, it is desirable to configure the addition/subtraction circuit without using the transformer 26. Furthermore, since the conventional adder/subtractor circuit is constructed of passive elements, it is inevitable that the output will be considerably attenuated, which has the drawback of requiring an amplifier to amplify this. SUMMARY OF THE INVENTION An object of the present invention is to provide a carrier color signal processing circuit which is suitable for integrated circuits, particularly semiconductor integrated circuits, and whose output amplitude can be easily adjusted. According to the present invention, a PAL chroma signal input terminal, circuit means for inverting the phase of a PAL chroma signal applied to the input terminal and delaying the PAL chroma signal by one scanning line period, a first arithmetic circuit that obtains a chroma signal component by adding (R-Y) the outputs of the circuit means; and subtracting (B-Y) the PAL chroma signal applied to the input terminal and the output of the circuit means; and a second arithmetic circuit for obtaining a chroma signal component. FIG. 4 shows a system diagram of a carrier color signal processing circuit according to the present invention. A part of the PAL chroma signal applied to the input terminal 1 is phase-inverted by an amplifier 42, and its amplitude is appropriately adjusted by a variable resistor 43, and then applied to a delay circuit 2 where it is delayed by one scanning line period and then sent to an adder circuit 48. and is added to the subtraction circuit 47. The other part of the PAL chroma signal applied to the input terminal 1 is adjusted in amplitude by an attenuator 41 and then applied to an addition circuit 48 and a subtraction circuit 47. Coils 21 and 22 adjust the phases of two PAL chroma signals applied to addition circuit 48 and subtraction circuit 47. The subtraction circuit 47 is composed of a subtracter including, for example, a differential amplifier 44, and the addition circuit 48 is also composed of, for example, two differential amplifiers 45 and 46.
It consists of an adder consisting of. In other words, the phase of the PAL chroma signal delayed by one scanning line period is inverted by the amplifier 42 and applied to the addition circuit 48 and the subtraction circuit 47, so the addition circuit 48 outputs the (R-Y) chroma signal component as an addition output. can be obtained at the output terminal 50, and from the subtraction circuit 47, the (B-Y) chroma signal component can be obtained at the output terminal 49 as a subtracted output. Generally, the output of a subtracter is smaller than the output of an adder, so in order to obtain the same output, the load on the subtracter must be made about twice as large as the load on the adder. The same applies to the DC level generated at both ends of the load, and by selecting the resistance value of the load as described above, the same voltage drop can be obtained. On the other hand, a balance can be obtained by providing an amplification factor of 1.78 times for the demodulation of the (BY) component as compared to the demodulation of the (RY) component. However, if a normal adder is used in the addition circuit and a normal subtracter is used in the subtraction circuit, the same voltage drop will occur at the load (B-
Y) The chroma signal component becomes an extremely small output (R-Y) and the balance with the chroma signal component cannot be obtained,
Similarly, if the output is balanced, the load DC voltage drop will vary greatly, which is an undesirable result. In this regard, according to the present invention, the subtracter 47 is used at the output section of the processing circuit for (B-Y) chroma signal separation, and the adder 48 is used at the output section of the processing circuit for (R-Y) chroma signal separation. Therefore, the DC voltage drop that occurs across the load is equal, and a balanced output can be obtained. Next, a first specific embodiment of the present invention will be described with reference to FIG. The input terminal 130 is connected to the base of an input stage emitter follower transistor 131, and the output of the emitter resistor 132 is connected to the base of a transistor 133 constituting an inverting amplifier. The gain of the inverting amplifier is adjusted by a variable emitter resistor, and an inverted output is obtained from a load resistor 137, which is applied via a coupling capacitor 138 to a delay circuit 140 for delaying one scan line period.
Coils 139 and 141 are for phase adjustment. On the other hand, the emitters of transistors 105 and 106 are connected to a constant current source 115 via resistors 111 and 112 to form a differential amplifier. Input PAL
The chroma signal is passed through resistor 128 to transistor 1.
The output of delay circuit 140 is applied to the base of transistor 105 through capacitor 142, and these two signals are subjected to a subtraction operation. However, since the phase is inverted by the output transistor 133 of the delay circuit 140, the load 121 of the transistor 105 produces the summed output, that is, the (B-Y) chroma signal component according to the prior art, and the emitter resistor 123 has the emitter resistor 123. The (B-Y) chroma signal component can be taken out to the output terminal 120 via the follower transistor 122. Furthermore, the emitters of the transistors 101 and 102 are connected to the constant current source 1 through resistors 107 and 108.
Similarly, the emitters of transistors 103 and 104 are connected to constant current source 11 through resistors 109 and 110.
4 to form a differential amplifier. The collectors of transistors 102 and 103 are connected to each other and connected to a power supply. transistor 10
Collectors 1 and 104 are also connected to each other and applied to the power supply via a load resistor 117. Terminal 12 is connected to the bases of transistors 102 and 103.
The DC bias voltage applied to terminal 124 is applied to the bases of transistors 101 and 104 via resistors 125 and 127. added to input terminal 130
The PAL chroma signal is connected to the base of transistor 101 via resistor 128 and to the base of transistor 101 through delay circuit 140.
The PAL chroma signals delayed by a scan line period are each applied to the base of transistor 104, and these signals are summed and applied to the base of transistor 15.
Load resistance 117 through a circuit consisting of 0 to 153
is generated and output to the output terminal via an emitter follower transistor 118 having an emitter resistor 119. The circuits of transistors 101, 102, 103, and 104 are adder circuits, but the PAL chroma signal output from the delay circuit 140 and delayed by one scanning line period is phase-inverted by the inverting amplifier of the transistor 133. These transistors 101, 102, 103 and 10
4 provides a prior art subtracted output or (RY) chroma signal component. Terminal 129 is a power supply terminal, 134 is variable resistor 13
5 is a terminal for connecting, 136 is a delay circuit connection terminal,
143 is a delayed chroma signal input terminal. Generally, the (R-Y) chroma signal component and the (B-Y) chroma signal component in the carrier color signal have different amplitude limiting coefficients. In a real signal, each chroma signal component is amplitude limited as follows. (RY) Chroma signal component; (E _R ′-E _Y ′)/1.14 (B-Y) Chroma signal component; (E _B ′-E _Y ′)/2.03} ~(4) In the above equation, E _Y ' is a luminance signal component, and E _R ' and E _B ' are gamma-corrected red and blue primary color signals. Therefore, in order to obtain each chroma signal component of (RY) and (B-Y), the circuit that synthesizes the (B-Y) chroma signal component is compared to the circuit that synthesizes the (RY) chroma signal component. requires a gain of 1.78 times. However, in this embodiment, the current flowing through the resistor 117 is approximately twice the current flowing through the resistor 121, and the resistance value of the resistor 121 is designed to be approximately twice that of the resistor 117 in order to obtain the same voltage drop. be done. Therefore, if the resistance value of resistor 121 is designed to be 1.78 times the resistance value of resistor 117, resistors 117 and 121
Approximately the same output is obtained with the coefficients for amplitude limitation being corrected, and the direct current voltage drop can also be made approximately the same. Furthermore, since the adder and subtracter are constructed of differential amplifiers, they can be integrated into a semiconductor integrated circuit extremely easily. Transistors 101 and 104 or transistor 102
The phase of the (RY) chroma signal components obtained at the collectors 103 and 103 is inverted every scanning line period. Therefore, this (RY) chroma signal component must be processed to match the phase of each period thereafter. Transistors 101 and 104
The (RY) chroma signal component obtained at the collector of transistors 102 and 103 and the (RY) chroma signal component obtained at the collectors of transistors 102 and 103 are always in an opposite phase relationship. Therefore, the emitters of transistors 150 and 151, which are connected in a differential manner, are connected to the collectors of transistors 101 and 104, and the emitters of transistors 152 and 153, which are connected in a differential manner, are connected to the collectors of transistors 102 and 103. 15
The collectors of transistors 151 and 153 are connected to the power supply, and the collectors of transistors 151 and 153 are connected to the load 117. On the other hand, the collectors of transistors 151 and 153 are connected to the load 117, and the rectangular wave generating circuit is connected in synchronization with one scanning line period detected by the matching circuit 155. A rectangular wave is taken out from 154 and applied to the circuit of transistors 150, 151, 152, and 153. Now transistor 1 is activated by the square wave.
When 50 and 153 are conductive, the (RY) chroma signal component available at the collectors of transistors 102 and 103 is available at output terminal 116, while when transistors 151 and 152 are conductive, transistor 1
The (RY) chroma signal components available at the collectors of 01 and 104 are available at the output terminal 116. The signals obtained at the collectors of transistors 102 and 103 and the collectors of transistors 101 and 104 are always in opposite phases and inverted every scanning line period, so the output terminal 116 always receives signals (R
-Y) A chroma signal component will be obtained. In this way, in this embodiment, it is possible to match the output phases of the (RY) chroma signal components quite easily on the same semiconductor chip. Although the embodiments of the present invention have been described above, the adder,
It is preferable to use a differential amplifier as a subtracter in a semiconductor integrated circuit because thermal effects can be removed, but the subtracter is not particularly limited, and it goes without saying that circuits with other configurations can also be used.

[Brief explanation of the drawing]

FIG. 1 is an example of a system diagram of a general PAL color demodulation circuit. In the figure, 1 is a chroma signal input terminal, 2 is a 1-horizontal period delay line, 3 is an amplitude adjustment circuit, 4 is a phase adjustment circuit, 5 is an adder, 6 is a subtracter, 7 is a carrier color signal processing circuit, and 8 is (B-Y) demodulator, 9 is (RY) demodulator, 10 is (B-Y)
Local subcarrier for demodulation, 11 is (RY) local subcarrier for demodulation, 12 is demodulation circuit, 13 is (B-Y)
Color difference signal output terminal 14 is a (RY) color difference signal output terminal. FIG. 2 is a vector diagram of a PAL chroma signal. FIG. 3 is an example of a specific circuit configuration diagram of the carrier color signal processing circuit. In the same figure, parts common to those in FIG. 1 are indicated by the same numbers, 21 and 22 are transformers for phase adjustment, 23, 27, 28, 29, and 30 are resistors,
24 is a variable resistor, 26 is a phase inversion transformer,
25 is a resistance matrix circuit, 31 is a (B-Y) amplifier, 32 is a (R-Y) amplifier, and 33 is a (B-Y) amplifier.
Y) Chroma signal component output terminal, 34 is (RY)
This is a chroma signal component output terminal. FIG. 4 is a system diagram of a carrier color signal processing circuit according to the present invention. In this figure, parts common to those in FIG. 3 are designated by the same numbers, 41 is a non-delayed chroma signal attenuator, 42 is a phase inversion amplifier, 43 is an amplitude adjustment variable resistor, and 44, 45 and 46 are Differential amplifier, 47 is a subtraction circuit, 48 is an addition circuit, 49 is (B-Y) chroma signal component output terminal, 50 is (R
-Y) Chroma signal component output terminal. FIG. 5 is a circuit configuration diagram of an embodiment of the present invention. In the same figure, 101, 102, 103, 1
04, 105, 106, 118, 122, 13
1,133...transistor, 107,108,
109, 110, 111, 112, 117, 11
9,121,123,125,126,127,
128, 132, 137... Resistor, 135... Variable resistor, 138, 142... Capacitor, 13
9,141...trans, 113,114,11
5... Current source, 140 is a 1 horizontal period delay line, 11
6 is (R-Y) chroma signal component output terminal, 120
is (B-Y) chroma signal component output terminal, 124 is bias voltage supply terminal, 129 is power supply voltage supply terminal, 130 is chroma signal input terminal, 134 is amplitude adjustment terminal, 136 is delay line coupling terminal, 143 is delay This is a chroma signal input terminal. 150,15
1, 152, 153 are transistors, 154 is a square wave generator, and 155 is a verification circuit.

Claims (1)

[Claims] 1. Receive a color television signal that includes two color difference signals that are quadrature-phase modulated on a color subcarrier and that is transmitted with the phase of one of the color difference signals inverted every scanning line period; In a carrier color signal processing circuit that separates two color difference signals, there is an input terminal to which the carrier color signal is applied, and the carrier color signal applied to the input terminal is inverted in phase and delayed by one scanning line period. circuit means for obtaining the carrier color signal applied to the input terminal; and a first circuit for receiving the carrier color signal applied to the input terminal.
a first differential amplifier circuit formed of a transistor and a second transistor whose base receives a bias voltage; a third transistor whose base receives a delayed carrier color signal obtained by the circuit means; and a bias voltage. a second differential amplifier circuit formed by a fourth transistor whose base receives a voltage; a fifth transistor whose base receives a carrier color signal applied to said input terminal; and a delay obtained by said circuit means. a third differential amplifier circuit formed by a sixth transistor that receives the carrier color signal based on the signal; and a third differential amplifier circuit (B-
Y) a first output means for obtaining a color signal component; a first connection means for connecting the collectors of the first and third transistors; and a first connection means for connecting the collectors of the second and fourth transistors. a second output means for obtaining the (RY) color signal component; a switch circuit for selectively coupling the first and second connection means to the second output means; A carrier color signal processing circuit comprising: a phase comparison circuit that drives a switch circuit.