JPS6249679B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device configured on the same semiconductor substrate as an information processing device.

Recently, microprocessors with a built-in memory device on a single silicon chip have appeared, and their memory capacity continues to increase year by year. Therefore, there is a need for a storage device that occupies less space, has a faster read speed, and consumes less power.

As a conventional method based on such requirements, there is a method in which a synchronous storage device that requires preliminary charging is used as a storage device that is placed on the same chip as the information processing device. This is because the information processing device has a reference clock and it is easy to generate a synchronous clock for the storage device, and the pre-charging method makes it easier to create a large capacity storage device with a small circuit scale. However, if a large number of storage devices are used, synchronization with various signals, and read speed are taken into consideration, the synchronization signal becomes complicated and the number of synchronization signal generation circuits increases.

In view of these points, an object of the present invention is to configure a storage device with high read speed and low power consumption without requiring any special circuit.

An information processing device according to the present invention includes a storage device having N addresses and requiring preliminary charging, and an address generator capable of generating M (M>N) addresses, and the address generator is connected to the storage device. The present invention is characterized in that the storage device is pre-charged during a period when an address other than the address assigned to the device is being generated.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, numeral 10 is a read-only memory (hereinafter abbreviated as RM) that is placed on the same chip as the information processing device and stores a microprogram.
(for example, 1024) addresses are given. 20 is a random access memory (hereinafter referred to as RAM) that includes a program counter that specifies addresses of the ROM 10 and other memories, and a stack register that saves the contents of the program counter as necessary.
). RAM 20 has n bits of output information and can specify 2 ⁿ addresses, but this is
10 (for example, when n=11, the number of specifiable addresses is 2048). Although this extra address may not be used, in this embodiment, it is output via the address bus buffer 40 and used as the address of an external expansion storage device. Transistors T1 ₁ to T1k and T2 ₁
-T2n are precharging transistors connected to the output lines of the ROM 10 and RAM 20, respectively, and precharging the output lines to a constant potential during the period of the clock φP. Further, Q ₁ to Qn are D-type flips that hold the signal on the output line of the RAM 20 at φA, and R ₁ to R _R hold the signal on the output line of the ROM 10 using the signal φB. 30 is an address decoder that converts the outputs of flip-flops _Q1 to Qn into ROM address selection signals; 50 is an address decoder
This is a control device that receives the output of the ROM 10 and performs various arithmetic processing and controls timing and the like.

The operation of each block shown in FIG. 1 will be explained based on the timing chart in FIG. 2 and the circuit diagram of the RM 10 in FIG. 3. Now, when there is a command to read a new microprogram code from the control device 50, the pre-charging clock φP is output simultaneously with the read clock φA of the RAM 20. Therefore, during the period of φP, transistors T2 ₁ to T2 _o are conductive.
All output lines of RAM 20 are precharged to a high level (logic "1"). As a result, RAM20
All outputs of the program counter within are “1”,
In other words, address 2048 will be output. However, since only addresses 0 to 1024 are given to the ROM 10, even if an address pointing to address 2048 is input to the address decoder 30, the ROM 10
The selection signals b ₁ to _{b o} are in a completely non-selected state.
Therefore, using this timing, the output line of RM10 is precharged to a high level via precharging transistors T1 ₁ to T1 _R using the same precharging clock φP. At this time, as _is clear from FIG.
can be precharged to the tV level by the precharge clock φP.

As can be seen from the above explanation, the present invention enables the program counter (address generator) to
By pre-charging the ROM10 when an address other than the address given to is output,
This has the effect of correctly precharging the ROM 10 without using any complicated circuit.

On the other hand, conventionally, for pre-charging the ROM10, a pre-charging cycle is provided separately before the cycle for accessing this ROM10, and in this cycle, the ROM10 is pre-charged.
The ten precharge transistors T1 ₁ to T1 _R had to be turned off. Moreover, at this time
Since the levels of the selection signals b ₁ to b _o input to the ROM 10 are uncertain, there is _no guarantee that all the transistors in FIG. ~ _bo , the output line _a1 cannot be properly precharged. Therefore, in the past, a switching transistor was connected to the terminal -V and turned off during preliminary charging. However, according to the present invention, the outputs b ₁ to b _o of the address decoder 30
Since the ROM 10 is pre-charged during the period in which all of the signals b ₁ to _{b o}
Since is guaranteed to be "0", a switching transistor is not required and the pre-charging circuit can be simplified.

Note that when the program counter outputs an address for accessing the ROM 10, one of the address designation signals b ₁ to _{b o} specifies one of the N addresses that the ROM 10 has, so the preliminary charging has already been completed. The ROM 10 that is running outputs a lantern at high speed.

As explained in the above embodiment, by simultaneously precharging a storage device that requires precharging when an address not assigned to the storage device is output from the address generator, there is no special problem. A high-speed, low-power storage device that does not require any circuitry can be obtained.

In addition, in the above embodiment, as the first storage device
Although ROM is assumed, the effects of the present invention will not be impaired even if this is RAM. Further, the second storage device need not be a program counter, but may be a set of registers having the function of specifying addresses of other storage devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment of FIG. 1, and FIG. 3 is a block diagram of block 10 in FIG.
This is a typical circuit diagram. 10...RM, 20...RAM, 30...decoder, 40...output buffer, 50...control device, Q ₁
~Qn, R ₁ ~Rn...D type flip, T1 ₁ ~T
1 _R , T2 ₁ to T2n... precharging transistors.

Claims (1)

[Claims] 1 A storage device having N addresses and requiring preliminary charging, and an address generator capable of generating M (M>N) addresses, the address generator being given to the storage device. An information processing device characterized in that the storage device is pre-charged during a period when an address other than the address is being generated.