JPS6250016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical deflection circuit for a television receiver;
In particular, the present invention relates to a circuit that derives vertical deflection drive pulses and blanking signals from vertical oscillation pulses so as to maintain a stable screen. A conventional vertical deflection circuit includes a vertical oscillation circuit 1 , switching transistors 2 and 3, as shown in FIG.
a first switching circuit 4 having a charging resistor 5;
and a charging/discharging circuit 7 having a charging/discharging capacitor 6,
It consists of a comparator 8 and a second switching circuit 11 having switching transistors 9 and 10, which supplies voltage Vc.c. from a power supply terminal 12 and outputs a voltage from an output terminal 13.
Derive the blanking signal from . In this configuration, the oscillation output V _A of the vertical oscillation circuit 1 is applied as an on signal to the switching transistors 2 and 9 via the base resistors 14 and 15 at a positive voltage shown in FIG. 2A. In response to the positive voltage, the switching transistor 2 is turned on and the switching transistor 3 is turned off, and the charging/discharging capacitor 6 is charged by a charging current flowing through the charging resistor 5. Next, when the terminal voltage V _B (FIG. 2B) of the charging/discharging capacitor 6 exceeds the reference voltage V _V of the comparator 8, the comparator 8 outputs the voltage V _C shown in FIG. The switching transistor 10 is connected to the base of the switching transistor 10.
is turned on during the period t ₁ to t ₂ , and accordingly, the base voltage V _D of the switching transistor 9 (FIG. 2 D) remains on during the period t ₀ to _{t 1} , that is, until the voltage V _B reaches the reference voltage V _V is at a high level, the voltage V _D is inverted by the switching transistor 9, and the output voltage V _E obtains a negative polarity pulse as shown in FIG.
This voltage V _E is used as a blanking signal at terminal 13.
It is derived from However, according to the above-mentioned configuration, the vertical scanning period has already begun at timing _t2 , and many other component transistors are also turned on or off at timing _t2 , so that the vertical deflection circuit cannot be driven. Identical circuit blocks such as stages (e.g. monolithic
IC) and has a negative effect. As a specific example of the negative effects, the vertical drive stage is interfered with, and horizontal white line noise appears above the screen of the television receiver, which is very unsightly. Therefore, the present invention provides a novel vertical deflection circuit that eliminates the above-mentioned drawbacks, and the present invention will be described below with reference to the drawings. FIG. 3 shows a vertical deflection circuit of the present invention, and FIGS. 4A to 4F show waveform diagrams of various parts in FIG. In the drawings, the same elements as in FIG.
Among them, 17 and 18 constitute a flip-flop 19 provided as a storage means. The output terminal of the switching transistor 20 is connected to each input terminal of one of the first comparator 21 and the second comparator 22 via the charging/discharging circuit 7 . Reference voltages V ₁ and V ₂ are applied to the terminals, respectively. 23 is turned on by the output from the first comparator 21 , and the flip-flop 19
The reset transistors 24, 25 and 26 are switching transistors for deriving a blanking signal and a deflection drive pulse from the output terminals 13 and 27, respectively. Next, the operation of the circuit of the present invention will be described. A voltage V _A shown in FIG. 4A is applied from the vertical oscillation circuit 1 to the flip-flop 19 via the switching transistor 16. Along with this, the transistor 16 is turned on by a positive pulse during the period t ₀ to _{t 1} , the transistor 18 is set to the OFF state, and the voltages V _C and V _D become low and high levels, respectively, at timing t ₀ . , switching transistor 20
is turned off, the charging/discharging capacitor 6 of the charging/discharging circuit 7 starts charging, and the voltage V _B rises as shown in FIG. 4B. When the reference voltage V ₂ of the charge/discharge capacitor 6 is reached, the second comparator 22 first outputs the voltage V _F shown in FIG. 4E. Next, the charge/discharge capacitor 6
When the voltage reaches the reference voltage V ₁ , the input terminal of the first comparator 21 becomes the threshold voltage and becomes high level at timing t ₃ , so that the reset transistor 23 is immediately turned on and the flip-flop 19 is turned on. is reversed, and the charge in the charging/discharging capacitor 6 is discharged by turning on the switching transistor ₂₀ , and as shown in _FIG . Accordingly, the voltage V _F at the output terminal of the second comparator 22 is determined according to the timing as shown in FIG.
Between t ₂ and _{t 3} a pulse of positive polarity appears, while switching transistor 24 is at the voltage V _D and switching transistor 26 is at the voltage V _D and V _F
As a result, voltages having the waveforms shown in FIG. 4C and F are derived from the output terminals 13 and 27, respectively. Therefore, the voltage V _E of the output signal 13 is applied to the video amplification circuit as a blanking signal, and the output terminal 2
By applying voltage V _G of 7 to each of the deflection drive stages as a deflection drive pulse for vertical deflection, a predetermined operation can be performed. As described above, in the circuit of the present invention, after the flip-flop provided as a storage means is inverted, that is, after the timing _t3 in FIG. Since the pulse width can be made smaller than that of the conventional circuit, the vertical oscillation circuit turns on or off the transistors in the circuit block during the period from _t0 to _t1 in FIG. As described above, the present invention can prevent a plurality of transistors from turning on or off during periods other than the blanking period, so it is possible to prevent interference with other circuit blocks. It is possible to eliminate horizontal white line noise that occurs in the image. In the above example, the charging resistor connected to the input terminal of the first comparator, that is, one end of the load of the transistor 20 was connected to the power supply terminal Vc.c. Using the midpoint voltage of the connected vertical output stage, one end of the load is connected to the midpoint, and the charging/discharging voltage V of the charging/discharging capacitor 6 is
By changing the waveform of _B , controlling the pulse width of the deflection drive pulse applied to the vertical drive stage from the output terminal 27, and controlling the midpoint voltage as a result, an extremely stable vertical deflection circuit can be obtained. . In this case, when the midpoint voltage increases due to temperature fluctuations, the charging waveform of the voltage V _B becomes steeper, and the period t ₀ to t ₂ becomes shorter as the voltage V B exceeds the reference voltage V ₂ more quickly. Accordingly, the low level period of the output voltage V _H becomes shorter and the midpoint voltage of the vertical output stage decreases, so that the midpoint voltage is kept constant.

[Brief explanation of the drawing]

FIG. 1 shows a conventional vertical deflection circuit, FIG. 2 A to E show waveforms of each part of FIG. 1, FIG. 3 shows an embodiment of the station circuit of the present invention, and FIGS. A waveform diagram is shown. Explanation of main figure numbers, 1 ... Vertical oscillation circuit, 5...
Charging resistor, 6...Charging/discharging capacitor, 7 ...Charging/discharging circuit, 13, 27...Output terminal, 19 ...Flip-flop, 21 ...First comparator, 22 ...
Second comparator.

Claims (1)

[Claims] 1. A flip-flop that is set according to the output signal of the vertical oscillation circuit, a charging/discharging circuit whose charging/discharging is controlled according to the output signal of the flip-flop, and a first reference voltage at one end and the charging/discharging circuit at the other end. a first comparator circuit to which an output signal is applied, a second comparator circuit to which a second reference voltage is applied to one end and the output signal to the other end; a first output circuit that operates in response to the output signal of the flip-flop; and a first output circuit that operates in response to the output signal of the flip-flop and becomes inoperable in response to the output signal of the second comparison circuit. 1. A vertical deflection circuit comprising a second output circuit, wherein a blanking signal is derived from the first output circuit, and a deflection driving pulse is derived from the second output circuit.