JPH07105953B2 - Burst gate pulse forming circuit - Google Patents

Description

The present invention relates to a burst gate pulse forming circuit, and is particularly suitable for application to a color video signal processing circuit used in video equipment such as a video tape recorder.

B. SUMMARY OF THE INVENTION The present invention creates a triangular-wave-shaped signal that changes in synchronization with a horizontal synchronizing signal in a burst gate pulse forming circuit, and generates a burst gate pulse using the first and second slope portions of the signal. By doing so, a burst gate pulse having a highly accurate pulse width and a delay time from the horizontal synchronizing signal can be easily obtained.

C Conventional Technology Conventionally, in a video tape recorder or the like, a method such as that shown in FIG. 3 is used to make a burst of a predetermined period at a time point after a predetermined time delay from the rise of the horizontal sync signal of the reference composite sync signal COMP. The gate pulse SG is formed and used for signal processing of color video signals.

That is, for example, by using a boost trap circuit or a Miller integrating circuit, a sawtooth wave signal S1 (Fig. 3 (Fig. 3 (A)) starts to change from the composite synchronizing signal COMP (Fig. 3 (A)) at the falling time t0 of the horizontal synchronizing signal HD. B)) is made.

The sawtooth wave signal S1 is compared with the reference levels V1 and V2, and the comparison output SC (FIG. 3 (C)) shows that the sawtooth wave signal S1 rises when it reaches the first reference level V1 and the second reference level V1. A gate pulse SG (FIG. 3 (D)) that falls when reaching the reference level V2 is formed.

Here, the amplitude V0 of the sawtooth wave signal S1, the period T1 from the time t0 to the amplitude V0 and the values of the reference levels V1 and V2 are the delay time T3 of the gate pulse SG from the horizontal synchronizing signal HD and the pulse width of the gate pulse SG. T4 is selected to be a predetermined value.

D The problem to be solved by the invention However, in order to obtain a gate pulse SG with a high accuracy in the delay time T3 and the pulse width T4, the variations in the reference levels V1 and V2 must be taken into consideration.

For example, in FIG. 3, when the reference level V1 varies so as to increase (or decrease), the delay time T3 decreases (or increases) and the pulse width increases.
T4 becomes larger (or smaller).

In order to reduce the effect of such variations, it is conceivable to make the slope of the period T1 of the sawtooth wave signal S1 steep so that the changes in the periods T3 and T4 due to the reference levels V1 and V2 become small.

However, this inclination cannot be made higher than V0 / (T3 + T4), and it is still insufficient to obtain sufficient accuracy for practical use.

In addition to this, it is unavoidable that an unnecessary pulse PN is generated in the comparison output SC by crossing the reference levels V1 and V2 during the recovery time T2 of the sawtooth wave signal S1 (Fig. 3 (C)). , When outputting the gate pulse SG, the pulse
There is a problem that a circuit for removing PN must be provided separately.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a burst gate pulse forming circuit having a highly accurate delay time and a highly accurate pulse width with respect to a reference signal. .

E Means for Solving Problems The first aspect of the present invention is to solve the problems.
And the pulse output SG rising at the first slope and falling at the second slope of the waveform formed based on the terminal voltage V6 of the capacitor 6 charged and discharged by the second current sources 4 and 5. The pulse forming circuits 11 and 16 to be obtained and the switch circuits 1, 2, 3, 7 for switching the first and second current sources 4 and 5 based on the blanking pulse BLK, the horizontal synchronizing signal HD and the output V6 of the capacitor 6. 9, 12 and 13 are provided so that a pulse output is generated at a time point delayed from the horizontal synchronizing signal HD by a predetermined time.

Based on the F action blanking pulse BLK, the horizontal synchronizing signal HD, and the terminal voltage V6 of the capacitor 6, the two current sources 4 and 5 for charging and discharging the capacitor 6 are switched, and the current source 4,
A triangular signal waveform based on the charge / discharge current of 5 is obtained.
This signal waveform is supplied to the comparison circuits 11 and 16 to obtain a pulse output in which one of the charge slope and the discharge slope rises and the other falls.

Thus, since the rising and falling of the slope can be used as the comparison signal, it is possible to obtain a highly accurate burst gate pulse forming circuit with pulse output.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a burst gate pulse forming circuit as a whole, and receives a composite synchronizing signal COMP (FIG. 2 (A)) through the gate circuit 1. The gate circuit 1 is a logic circuit having a truth value as shown in FIG. 4, and receives the blanking pulse BLK (FIG. 2 (B)) and the control signal SN as a gate control signal.

Thus, at the output end of the gate circuit 1, the composite synchronization signal COM
P, blanking pulse BLK and control signal SN are logic "L"
At time t12, an input signal SS (FIG. 2 (C)) which rises from the logic "L" to the logic "H" is obtained and applied to the set input terminal S of the RS flip-flop circuit 2.

The reset pulse RST (FIG. 2 (G)) is input to the reset input terminal R of the flip-flop circuit 2, and the output control signal SQ (FIG. 2 (D)) is output to the switch circuit 3.

Thus, when the flip-flop circuit 2 is reset and the control signal SQ (FIG. 2 (D)) is in the logic "H" state.
When the signal SS becomes logic “H” at t12, the control signal SQ
Falls to logic "L". Then, at time t16, when the reset pulse RST (FIG. 2 (G)) becomes logic "H", the flip-flop circuit 2 is reset and the control signal
SQ becomes logic "H".

The switch circuit 3 connects and controls the non-earth side end 3a of the parallel circuit including the charging / discharging capacitor 6 and the constant current source 5 to the current source 4 having the constant current value 2I. As a result, when the flip-flop circuit 2 is set at time t12 and the control signal SQ becomes logic "L", the switch circuit 3 is turned off and the capacitor 6 is discharged at the current value I of the constant current source 5. , Its terminal voltage V6 decreases with a time constant determined by the current value I (FIG. 2 (E)).

When the flip-flop circuit 2 is reset at time t16 and the control signal SQ becomes logic "H", the capacitor 6 is charged with the current I which is the difference between the current sources 4 and 5, and when its terminal voltage V6 is determined by the current value I. It rises by a constant.

In addition to this, the non-earth side end of the capacitor 6 is a transistor whose base is supplied with the output voltage E1 of the reference power supply 7.
It is connected to the emitter of the transistor Q2 whose output voltage E2 of the power source 8 is applied to Q1 and the base. The collector of the transistor Q1 is connected to the power line Vc via the diode 13.
connected to c, the collector of transistor Q2 is diode 1
Connected to ground through 5.

Here, the voltages E1 and E2 are Vbe≈E1 << E2≈Vcc-Vbe (1), where vbe is the base emitter voltage of the transistors Q1 and Q2 and the diode voltage of the diodes 13 and 15 and Vcc is the voltage of the power supply line. Have been selected so that

Therefore, when the terminal voltage V6 of the capacitor 6 becomes lower than the voltage E1-Vbe, the transistor Q1 is turned on by being provided as the emitter voltage Ve1. On the other hand, the transistor Q2 is the terminal voltage of the capacitor 6.
When V6 becomes higher than the voltage E2 + Vbe, this is given as the emitter voltage Ve2 to turn on.

The collector of the transistor Q1 is supplied as a comparison input to the comparison circuit 12 which receives the voltage E4 satisfying the condition of the following formula Vcc>E4> Vcc-Vbe (2) from the reference power source 9 as the reference input. The output of the comparison circuit 12 is output to the reset terminal R of the flip-flop circuit 2 as a reset pulse RST.

Similarly, the collector of the transistor Q2 is given as a comparison input to the comparison circuit 14 which receives the voltage E5 satisfying the condition of the following expression 0 <E5 <Vbe (3) from the reference power source 10 as the reference input. The output of the comparison circuit 14 is output to the input terminal C of the gate circuit 1 as the control signal SN.

Further, the terminal voltage V6 of the capacitor 6 is given to the comparison circuit 16 which receives the output voltage E3 of the reference power source 11 as a reference, and when the terminal voltage V6 of the capacitor 6 becomes V6 <E3, the comparison circuit
Burst gate pulse SG of logic "H" level is transmitted from 16 output terminals. Here, the comparison voltage E3 is selected to be a value that satisfies the condition of the following expression E1-Vbe <E3 <E2 + Vbe (4).

In the above configuration, as shown at time t01 in FIG.
When both the composite synchronizing signal COMP (FIG. 2 (A)) and the blanking pulse BLK (FIG. 2 (B)) are logic "H", the flip-flop circuit 2 is in the reset state (see FIG. 2 (D)). )), The switch circuit 3 is in the ON state.

At this time, the capacitor 6 is charged by the current source 4, so that the terminal voltage V6 is charged to the upper limit voltage E2 + Vbe (Fig. 2 (E)), the transistor Q2 is turned on, and the transistor Q1 is turned off. It Therefore, the control signal SN (FIG. 2 (F)) obtained at the output terminal of the comparison circuit 14 becomes the logic "L" to control the gate circuit 1 to open, and the comparison circuit 14
The reset signal RST (FIG. 2 (G)) obtained at the 12 output terminals is logic "L". Thus, the burst gate pulse forming circuit operates as the burst gate pulse signal SG.
It is in a stable state in which (FIG. 2 (H)) is set to logic "L".

Eventually, the blanking pulse BLK falls to the logic "L" at the time t11, and then the composite synchronizing signal COMP falls to the logic "L" at the time t12, the set input signal SS rises to the logic "H" in sequence, The flip-flop circuit 2 is set and the switch circuit 3 is turned off.

At this time, the capacitor 6 is discharged by the current source 5, and its terminal voltage V6 decreases. Accordingly, the transistor Q2 is immediately turned off, and the comparison circuit 14 raises the control signal SN to the logic "H" and the signal SS to the logic "L". Thus, after that, the gate circuit 1 is controlled to be closed.

When the terminal voltage V6 becomes equal to or lower than the reference voltage E3 at time t15, the burst gate pulse signal SG rises to logic "H". However, the capacitor 6 continues to be discharged, and thus the terminal voltage V6 continues to drop.

After that, at time t16, the terminal voltage V6 becomes the lower limit voltage E1-Vbe.
In the following cases, the transistor Q1 turns on and the comparison circuit
Twelve reset signals RST rise to logic "H". At this time, the flip-flop circuit 2 sequentially performs the reset operation,
The switch circuit 3 is turned on and the capacitor 6 is turned on by the current source 4.
To return to the state of being charged. Accordingly, the terminal voltage V6 rises, but when it rises even slightly, the transistor Q1 immediately turns off and resets the reset signal RST to logic "L".

At time t17, when the terminal voltage V6 rises above the reference voltage E3, the burst gate pulse signal SG falls to the logic "L". However, the capacitor 6 continues the charging operation.

After that, at time t18, the terminal voltage V6 becomes the upper limit voltage E2 + Vbe
When it becomes higher, the transistor Q2 is immediately turned on sequentially, the control signal SN of the comparison circuit 14 falls to the logic "L", and the gate circuit 1 is controlled to be opened, thus returning to the stable state described at the time point t01. New blanking pulse
Awaiting arrival of BLK and composite sync signal COMP.

According to the above configuration, the rise time (that is, time t15 shown in FIG. 2) and the fall time (that is, time t17 shown in FIG. 2) of the burst gate pulse are set at the capacitor 6
It can be determined by using the falling slope and the rising slope of the terminal voltage V6.

However, the slope of the slope can be about twice as steep in order to obtain a gate pulse having the same pulse width as that of the conventional case when operated at an operating voltage almost equal to that of the conventional case. Therefore, the fluctuation of the delay time due to the change of the comparison voltage E3 can be reduced to about 1/2. Further, since the burst gate pulse signal SG is formed using one reference level, the pulse width variation factor is different from the case where the burst gate pulse signal SG is formed from a sawtooth wave using two reference levels as in the past. Can be reduced by one, and fluctuations in pulse width can be reduced. This makes it possible to obtain a burst gate pulse with higher accuracy than in the conventional case.

Further, a circuit for removing an unnecessary pulse PN (FIG. 3 (C)) generated when the slope is restored as in the conventional case is also unnecessary.

In addition, according to the above-described embodiment, since the blanking pulse BLK and the composite synchronizing signal COMP are used for driving, the composite synchronizing signal COMP, such as an equalizing pulse inserted in the vertical blanking period, is used. Even if pulses are mixed, it is possible to prevent malfunction.

Further, by changing the comparison voltage E3 of the reference power supply 11, the center of the burst gate pulse is delayed from the composite synchronizing signal COMP by a certain time (that is, the time points t12 to t16 are kept constant), and the pulse width (that is, the time point t15). To t17) can be changed freely.

Therefore, by connecting a plurality of comparison circuits having different comparison voltages to the terminals of the capacitor 6, it is possible to accurately obtain a plurality of signals having the same central time points t15 and different pulse widths.

Note that, in the above-described embodiment, the case where a pulse that rises with a descending slope and falls with an ascending slope is described has been described, but instead of this, the same effect can be obtained even when descending with a descending slope. Obtainable.

Further, in the above-mentioned embodiment, the case where the triangular waveform signal which is triggered by the composite synchronizing signal COMP to gradually fall and rise is described, but instead of this, 0
[V] A signal waveform that gradually rises and falls from the vicinity may be used.

Further, in the above-mentioned embodiment, the constant voltage E3 was used as the comparison voltage, but instead of this, a pulse is raised at the voltage EA in the slope falling portion using a plurality of reference voltages, and in the slope rising portion. It may be configured to fall at a voltage EB different from this.

H Effect of the Invention As described above, according to the present invention, a burst gate pulse forming circuit having a highly accurate pulse width and delay time is obtained by using slopes of rising and falling portions of a signal that changes into a triangular wave shape. Can be easily obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a burst gate pulse forming circuit according to the present invention, FIG. 2 is a signal waveform diagram thereof, FIG. 3 is a signal waveform diagram used for explaining a conventional example, and FIG. 4 is a gate circuit 1 of FIG.
Is a truth table of. 1 ... Gate circuit, 2 ... Flip-flop circuit, 3 ...
… Switch circuits, 4, 5 …… Current sources, 6 …… Capacitors, 7,8,9,10,11 …… Power supplies, 12,14,16 …… Comparison circuits, Q1, Q2 …… Transistors.

Claims (1)

[Claims] 1. An output pulse rising at a first slope and falling at a second slope of a waveform formed based on the terminal voltage of a capacitor charged and discharged by a first and a second current source. And a switch circuit for switching the first and second current sources on the basis of a blanking pulse, a horizontal synchronizing signal, and a terminal voltage of the capacitor, at a time point delayed from the horizontal synchronizing signal by a predetermined time. The burst gate pulse forming circuit is characterized in that the pulse output is generated in the above.