JPS6251034B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides information (hereinafter referred to as data) superimposed on a predetermined horizontal scanning period of a television signal, for example, in an unused area in a time-division manner. This relates to a data slicing circuit that slices and extracts data.

<Prior art> Information such as text or graphics is superimposed on an unused area (vertical blanking period) of a television signal in a time-division manner and transmitted, and the receiving side detects, decodes, and stores this television signal in memory. A teletext system, etc., which reproduces text and graphics on a sequential readout television, has been proposed, and the present invention provides a useful data slicing means for a receiver used on the receiving side of such a system, such as a teletext receiver, etc. .

Conventionally, this type of data slicing circuit slices and extracts a detected video signal at a constant level.

In general, when a television signal is sent out from a transmitter and transmitted through a television receiver's radio frequency (hereinafter referred to as RF) circuit, intermediate frequency (hereinafter referred to as IF) circuit, etc., the waveform becomes considerably distorted, especially "1", " A pulse signal such as a binary signal of 0'' has a large distortion in a high frequency range due to band limitations, etc., and becomes an almost triangular wave. If such a distorted video detection output is sliced at a fixed slice level as in a conventional slicing circuit, the reproduced data pulse will be quite different from the original pulse on the transmitting side. That is, it appears as a fluctuation in pulse width, and especially pulses in a high frequency region have narrower pulse widths.

When reading the data pulses reproduced by such a conventional slice circuit at a constant clock,
There are many reading errors, and the error rate becomes particularly high when the RF input is small. For example, when receiving teletext broadcasts, dot errors, coloring errors, control errors, etc. occur in characters, resulting in unsightly images. .

<Object of the Invention> Therefore, in view of the above points, the present invention aims to provide a data slicing circuit that can make sliced data pulses as close to their original form as possible. This method is characterized in that the slice level is varied by changing the slice level, making the reproduced data pulse waveform close to the original shape, which in turn contributes to reducing the error rate mentioned above.
The principle of the present invention will be explained with reference to the drawings.

FIG. 1 shows a block diagram when a data slicing circuit is added to a television receiver circuit.

A television signal (RF signal) received by antenna A is introduced into a video detection circuit through an RF circuit and an IF circuit to obtain a video signal.

As shown in Figure 2, data pulses are superimposed on the television signal, and the video signal obtained by detection includes data pulses. In Figure 2, SH represents the horizontal synchronizing signal, and S _B indicates a burst signal, S _P indicates a data pulse, and S _E indicates a video signal.

Here, the data pulse generally has a maximum frequency of several Mbit/s, and is a binary signal of "1 (high level)" and "0 (low level)".
The video signal detected by the video detection circuit D usually has considerable distortion.

The video signal is introduced into a video circuit, a color (color signal processing) circuit, a synchronization circuit, etc., and then normal television reception is performed.

Further, the video signal is introduced into the data slicing circuit S, and after being sliced as described later, is introduced into, for example, a teletext receiver, where it is subjected to character reception processing, and information such as characters is displayed. Note that the output of the data slice circuit S can also be used for purposes other than teletext receivers, such as copying.

FIG. 3 shows an explanatory diagram for theoretically explaining the data pulse slicing operation. In this figure, S ₁
indicates a data pulse superimposed on a television signal on the transmitting side, and _S2 indicates a video detection output signal (video signal) of the video detection circuit D.

When this video signal S ₂ is sliced at a constant slice level S _C shown by a dashed line in FIG. 3, that is, at the slice level of a conventional slicing circuit, a slice output signal S ₃ is obtained. As is clear from FIG. ₃ , in this slice output signal S3, pulses _S'3 and _S''3 corresponding to the single pulses _S'1 and _S''1 have a small pulse width.

This is because in the data pulse of the video detection output signal _S2 , if "1" continues, one "0" bit enters in the middle, and then "1" continues (or vice versa). Generally, a 1-bit "0" pulse (or "1" pulse) does not completely fall (or rise) to a low level (or high level), and in such a case, the pulse width changes, This is because in extreme cases, the data pulse may not be extracted without reaching the slice level.

When such pulse width fluctuations occur, the data processing circuit (not shown) following the data slice circuit S often fails to read the data pulses properly, which causes an increase in the error rate. .

The level S _V shown by the broken line in FIG. 3 corresponds to the slice level of the data slicing circuit of the present invention, and this slice level S _V can be peak-detected by peak-detecting the video signal S ₂ as described later. The output can be obtained as _S4 . By slicing the video signal S ₂ at this slice level S _V , a slice output signal S ₅ can be obtained. That is, the slice level changes depending on the size of the data pulse, and it is possible to obtain a slice output signal _S5 that approximates the original data pulse on the transmitting side.

<Embodiment> FIG. 4 shows a block diagram of an embodiment of the data slice circuit of the present invention.

The output signal of the video detection circuit D, that is, the video signal, is amplified to an appropriate level by the amplifier _A1 and then introduced to the clamp circuit _C1 .

This clamp circuit _C1 is a pedestal clamp circuit, and prevents the reference level (DC level) of the video signal from changing depending on the video content (width).

Further, the video signal is amplified to an appropriate level by the amplifier _A2 and then introduced to the peak detection circuit _P1 .

This peak detection circuit _P1 performs a peak detection operation with a small time constant. That is, in response to amplitude fluctuations of data pulses (data pulses included in the video signal), a peak detection output as shown by _S4 in FIG. 3 is obtained.

This peak detection output is introduced into the clamp circuit _C2 . This clamp circuit _C2 has the same function as the above-mentioned clamp circuit _C1 , and the DC component of the peak detection output is determined by the clamp level.

The voltage comparator O ₁ receives the output signal S _C1 of the clamp circuit C ₁ and the output signal S _C2 of the clamp circuit C ₂ , and derives an output by comparing the voltage of the former with the latter. Here, the output signal S _C2 corresponds to the slice level S _V , the output signal S _C1 corresponds to the video signal S ₂ , and the output S ₀ of the voltage comparator O ₁ corresponds to the video signal S 2.
is the sliced output signal obtained by slicing the former by the latter.
Obtained as _S5 .

Note that the clamp circuits C ₁ and C ₂ use a signal obtained by delaying the horizontal synchronization signal by several μs (delayed H
pulse) is input. Needless to say, this delayed H pulse can be obtained using a well-known technique.

An embodiment of the video slice circuit of the present invention is shown in the fifth embodiment.
This will be explained in detail with reference to the embodiments shown in the figures.

43 is a power supply for the slice circuit, to which a DC voltage of, for example, 12V is applied.

A video signal on which data pulses are superimposed (video detection output of the video detection circuit D) is input to the video input, and is input to the base of the transistor 24 through the coupling capacitor 2. transistor 2
4 and the transistor 12 coupled thereto corresponds to the above amplifiers A ₁ and A ₂ ,
Amplify the video signal to an appropriate value. The resistor 14 is
The load resistance of the transistor 12 is composed of a semi-fixed volume, and a signal taken out from its midpoint is inputted to the base of the transistor 25 through a coupling capacitor 25. Then, the signal taken out from the collector of the transistor 12 is
It is input to the base of transistor 15. In addition,
The polarity of the output signal of the transistor 12 is the same as that of the video signal of the video input, and is suitable for clamping in the next stage.

The transistor 15 and the FET 18 coupled thereto via the capacitor 17 constitute a clamp circuit corresponding to _C1 described above. Note that transistor 1
5 is an emitter follower with low impedance on the output side, which is connected to high impedance.
I received it with FET18.

Here, the transistor 44 coupled to the gate of the FET 18 constitutes an input stage for the clamp pulse, and the clamp level is determined by the resistors 20 and 21. Note that 22 is a bypass capacitor.

The delayed H pulse is input to this transistor 44, the clamp circuit operates as a pedestal clamp, and an output signal _SC1 is obtained at the output of the FET 18, which is input to the voltage comparator _O1 .

Further, the output side of the transistor 28 is connected to a resistor 30,
It is coupled to a peak detection circuit that also includes a diode 31, a capacitor 32, a resistor 33, and the like.
In this peak detection circuit, the charging and discharging time constants are mainly determined by the capacitor 32 and the resistors 30 and 33, and are appropriately selected to be small time constants so as to respond to high frequency data pulses.

This data detection circuit corresponds to _P1 above,
The output of this is introduced into the base of transistor 34.

The transistor 34, FET 37, and transistor 42 are a clamp circuit corresponding to _C2 , and are equivalent to the clamp circuit composed of the transistor 15, FET 18, and transistor 44, and operate as a pedestal clamp.

Here, the resistors 39 and 40 determine the clamp level, but they also determine the DC slice level. In this way, FET3
At the output of 7, an output signal S _C2 , that is, a slice signal S _V is obtained and is introduced as the other input of the voltage comparator O ₁ .

The voltage comparator O ₁ slices the output signals S _C1 and S ₂ by comparing the voltages at the output signal S _C2 , that is, the slice level S _V , and obtains the slice output signal S ₀ .
This slice output signal S ₀ corresponds to the signal S ₅ and is reproduced as a data pulse close to the original data pulse on the transmitting side.

<Effects of the Invention> According to the slicing circuit of the present invention, by slicing a signal that has been distorted due to passing through various transmission systems using a variable slice level obtained in accordance with the data pulse contained in the signal, A reproduced signal with distortion corrected is obtained, and when the thus reproduced data pulses are read in with a constant clock, the error rate becomes extremely low, and information close to that on the transmitting side can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram when a slicing circuit is added to a television receiver circuit, Fig. 2 is an explanatory diagram of data pulses superimposed on a TV signal, and Fig. 3 is a data slicing circuit of a conventional example and the present invention. FIG. 4 shows a block diagram of the data slicing circuit of the present invention, and FIG. 5 shows an electric circuit of an embodiment of the same. A ₁ and A ₂ : Amplifier, C ₁ and C ₂ : Clamp circuit, P ₁ : Peak detection circuit, O ₁ : Voltage comparator.

Claims (1)

[Claims] 1. In a circuit that slices and extracts information superimposed on a predetermined vertical blanking period of a television signal, a first signal obtained by clamping a video detection output signal is introduced into a voltage comparator. means for outputting a second signal obtained by clamping the output of the peak detection circuit; A data slicing circuit, characterized in that it comprises means for reproducing said information by slicing said first signal in accordance with a second signal, introduced as the other input of a voltage comparator.