JPH0213995B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a data slicing circuit that slices and extracts data pulses superimposed on a predetermined horizontal scanning period of a television signal.

<Prior art> In a teletext receiver that utilizes the vertical blanking period of a television signal and receives character signals transmitted in data packets whose unit length is one horizontal scanning period, the system shown in FIG. As shown, a television antenna A receives a television signal. Next, the television signal is processed through a high frequency circuit B, an intermediate frequency circuit C, and a video detection circuit D of the television receiver. In this way, the processed television signal is processed as a video signal by a circuit E including a video circuit, a color (color signal processing) circuit, and a synchronization circuit for normal television reception, while for teletext reception. It is also input to the data slice circuit F. By the way, the television signal processed in this way has horizontal synchronizing signals SH, as shown in FIG.
It includes a data pulse SP for text broadcasting along with a burst signal SB and a video signal SE. Such data pulse SP is transmitted to each circuit B~ in Figure 1.
The waveform is considerably distorted by passing through the signal D, and the distortion becomes particularly large in the high frequency range due to the band limitation.The signal is then input to the data slicing circuit F and subjected to slicing processing. However, in conventional data slicing circuits, the slicing level is set to a fixed level, so when slicing a data pulse with such large distortion, the reproduced data pulse is not the same as the original data pulse on the transmitting side. differ considerably in terms of pulse width. Particularly in the high frequency range, the pulse width of the reproduced data pulse is narrower than that of the original data pulse. Therefore,
When data pulses reproduced by conventional data slicing circuits are read at a constant clock, there are many errors in reading, and the error rate is particularly high in the high frequency range where the pulse width is narrow and the input level of the signal is small. growing. For this reason, in teletext broadcasting receivers and the like, it causes dot errors in characters, errors in coloring, errors in control, etc., resulting in unsightly images. In addition, some conventional examples use the value obtained by dividing the peak value of the input signal as the slice level, but this means that when the input signal has continuous "0" data,
The above-mentioned errors occur because noise in the level portion is sliced as data.

<Purpose> The present invention is designed to handle highly distorted data pulses and “0” data pulses.
The purpose is to slice the data pulse so that almost the original data pulse is reproduced even if the level signal is continuous.

<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

Before going into the description of this embodiment, the reason why the pulse width of the reproduced data pulse becomes narrower when the data slice level is fixed as in the conventional method will be explained. First, the higher the frequency, the lower the level of the data pulse signal in the transmission circuit from the television antenna to the data slice circuit. Therefore, the respective levels of the data pulse signal in the low frequency range and the data pulse signal in the high frequency range are smaller in the latter. However, since the data slice level is fixed, the level difference between the peak level of the data pulse signal in the high frequency range and the data slice level is small compared to that of the data pulse signal in the low frequency range, and it is extremely In some cases, the data slice level may be larger. Therefore, when a data pulse signal in a high frequency range is sliced and extracted, its pulse width becomes extremely narrow. This embodiment eliminates the above problem by relatively changing the data slice level according to the level of the data pulse signal.
Also, if the data pulse signal continues to have "0", it is equivalent to the signal disappearing, and its peak level will become "0". If there is noise etc. in the data pulse signal, it will be Use it as a signal and slice it.

The present invention limits the lower limit voltage of the slice level to prevent it from falling below a certain level. Therefore, even if "0" is consecutive, it can be determined as "0" and this problem is solved. This will be explained below.

FIG. 3 is a circuit diagram of this embodiment. The data slice circuit of this embodiment is applied to a teletext receiver, as shown in FIG. This data slice circuit has a circuit that clamps a video signal amplified to a predetermined level by a video amplification circuit. This clamp circuit fixes the pedestal level of the video signal to a potential of approximately 0 volts,
The slice level is not affected by the average video level. For this reason, the clamp circuit is
A DC cut capacitor _C1 , a switching transistor _Tr1 to which a clamp pulse is applied,
It has pace bias resistances R ₁ and R ₂ . This clamp pulse is, for example, a pulse obtained by delaying the horizontal synchronizing signal SH to the pedestal portion. The video signal given to the clamp circuit has its DC component cut off by the DC cut capacitor _C1 .
Next, a clamp pulse is applied to the switching transistor Tr ₁ so that the collector potential of the switching transistor Tr ₁ becomes approximately 0 volts, so that the pedestal portion is fixed at approximately 0 volts and is output from the clamp circuit. The first output signal S ₁ of the clamp circuit is applied to the normal input section + of the voltage comparator, and is also applied to the lower limit voltage limiting circuit. The lower limit voltage limit circuit is
A transistor Tr ₂ to which the first output signal S ₁ is applied to the base, a resistor R ₃ connected between the emitter of this transistor Tr ₂ and the ground potential part, and a resistor R ₇ connected between the DC power supply +V. including. At the emitter of transistor Tr ₂ there are usually resistors R ₃ and R ₇
A bias voltage of V _E2 is generated by the base current of the transistor Tr ₃ , which will be described later. The first output signal S ₁ input to the base of the transistor Tr ₂ of this lower limit voltage limiting circuit has a noise component near 0 volts. This noise component is cut by the base-emitter voltage V _BE2 and emitter voltage V _E2 of the transistor Tr ₂ . transistor
The second output signal S ₂ from the emitter of Tr ₂ is given to the peak detection circuit. The peak detection circuit includes a capacitor _C2 connected to the ground potential, a transistor _Tr3 , and a resistor _R4 connected between the emitter of the transistor _Tr3 and the DC power supply +V. Second output signal from lower limit voltage limit circuit
After the peak of S ₂ is detected by the capacitor C ₂ of the peak detection circuit, it is output as the third output signal S ₃ from the emitter of the transistor Tr ₃ . The third output signal S ₃ is obtained by superimposing the second output signal S ₂ on the base-emitter voltage V _BE3 of this transistor Tr ₃ . Therefore, the base-emitter voltage V _BE2 of transistor Tr ₂ of the lower limit voltage limiting circuit
The second output signal S ₂ whose level has been lowered is level-compensated by the base-emitter voltage V _BE3 of the transistor Tr ₃ of the peak detection circuit and becomes the third output signal S ₃
is output from the peak detection circuit as Thus, the third output signal _S3 from the peak detection circuit is
given to the voltage divider circuit V composed of resistors R ₅ and R ₆ ,
Here, an appropriate level, in this example, 1/1 of the input signal.
The pressure is divided to 1/2 for slicing at position 2. Therefore, the resistance values of the resistors R ₅ and R ₆ are set to be equal to each other. The third output signal _S3 , which has been divided into 1/2 level by the voltage dividing circuit V, is applied as the fourth output signal _S4 to the inverting input part of the voltage comparator, and is used as a reference in this voltage comparator. It is assumed to be a voltage signal.

FIG. 4 shows the first to fourth output signals _S1 to _S4 .
In Figure 4a, SH is the horizontal synchronization signal, and
SN indicates a noise component, respectively. As shown in FIG. 4a, the pedestal portion of the data pulse is clamped to approximately 0 volts by a clamp circuit and is applied to the lower limit voltage limiting circuit as a first output signal _S1 . Transistor of lower limit voltage limit circuit
Due to the base-emitter voltage V _BE2 of Tr ₂ , the first
The level of the output signal S ₁ is lowered as shown by the level line m ₁ and outputted from the emitter of the transistor Tr ₂ as a second output signal S ₂ as shown in FIG. 4b. In this case, it can be seen that V _E2 is always present, the input of the first output signal S ₁ is almost unaffected, and the potential above it is fluctuating due to the first output signal S ₁ . Here, Fig. 4b
As shown in , the rise of the second output signal S ₂ is steep. Due to this steep rise of the second output signal _S2 , even if a data pulse with a high frequency arrives, it is possible to reliably detect this data pulse. Next, the second output signal _S2 is the base-emitter voltage of the transistor _Tr3 of the peak detection circuit.
V _BE3 raises the level as shown by the level line m ₂ and outputs the third output signal S ₃ as shown in FIG. 4c.
is output from the emitter of this transistor _Tr3 .

Next, in the voltage comparator, the first output signal S ₁ and
A voltage level comparison is made with the fourth output signal _S4 , but the voltage level of the first output signal _S1 is _higher than that of the fourth output signal S4.
When that is larger, "1" is output as data, and when it is smaller, "0" is output as data.
Output. In this case, even if the noise component SN is superimposed on the first output signal _S1 , the lowest voltage level of the fourth output signal _S4 can be made sufficiently higher than the noise component SN. There is no possibility that the operation will be affected.

<Effects> As described above, according to the present invention, there are provided means for clamping the data pulse signal, means for limiting the lower limit voltage of the output signal from the clamping means using a DC bias, and a discharge time constant sufficiently smaller than the horizontal period. Since the data pulse to be sliced is When a signal is applied to the other comparison input of the voltage comparator, even if the level of the data pulse signal varies depending on the frequency range, the signal is applied to one reference input of the voltage comparator in response to this variation. The output signal that is applied and becomes the data slice level also varies. Therefore,
Due to the characteristics of the transmission path, even if the level of the data pulse signal decreases, especially in the high frequency range, the data slice level also decreases accordingly, so it is not possible to reproduce the data pulse accurately in correspondence with the original data pulse. can. In addition, since the level is set so that even data with a series of 0's does not fall below a certain level, misreading when reading data pulses using a certain clock is greatly reduced, making it easier for teletext receivers, etc. In this case, it is possible to contribute to providing an easy-to-see image.

[Brief explanation of drawings]

FIG. 1 is a simplified block diagram including a data slicing circuit in a teletext receiver;
3 is a partial waveform diagram of a television signal, FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a waveform diagram of an output signal for explaining the circuit of FIG. 3. ...clamp circuit, ...voltage comparator, ...
...peak detection circuit, ...voltage divider circuit, ...lower limit voltage limit circuit.

[Claims]

1 In a method that compresses information only for images in areas that have changed compared to the previous screen and transmits the information in a narrow band, the process of converting the difference between each pixel and the previous screen into an absolute value and the process of converting the difference between each pixel and each line parallel to each coordinate axis A process of cumulatively adding the absolute value of the difference of each pixel to A still image transmission method that consists of compressing and transmitting image information in a rectangular area determined by minimum and maximum values. 2. The still image transmission method according to claim 1, wherein the image information of the rectangular area is compressed and transmitted using a variable sampling density predictive coding method.