JPS6252346B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to an inter-processor communication system for a distributed processing system having a multiprocessor configuration.

[Description of prior art]

Conventionally, in a distributed processing system having a multiprocessor configuration, communication between processors has been performed. A communication buffer is required for this inter-processor communication, but since the communication buffer has a limited storage capacity, a deadlock condition occurs.

Here, the term "deadlock state" refers to a state in which all processors are unable to perform input processing because their output buffers are full and cannot perform internal processing, and data processing in the system is stopped.

Conventionally, such cases have been resolved by either processing through the intervention of a system maintainer or by providing a dedicated communication path for dealing with such situations. For this reason, there are disadvantages such as complicated processing and high cost if a dedicated communication path is provided.

[Purpose of the invention]

The present invention improves on this point, and aims to provide a communication method that can automatically release a system deadlock caused by a full communication buffer in a distributed processing system.

[Summary of the invention]

In the present invention, when a deadlock occurs, the communication buffer becomes full for a certain period of time or longer, so when the communication buffer becomes full for a certain period of time, which does not occur during normal system operation, it is determined that a deadlock has occurred after a certain period of time has elapsed. The invention is characterized in that it includes a device that automatically initializes the system.

That is, the present invention provides a distributed processing method in which processing is distributed to a plurality of information processing apparatuses and data is transmitted and received between the plurality of information processing apparatuses. It is equipped with a counter monitoring circuit that monitors the contents of the transmission buffer counter of the processing device, and a timer that is set when this counter monitoring circuit detects a predetermined value and reset when it detects a value below the predetermined value. When an output is generated, the related information processing device group is controlled to be set to an initial state.

[Explanation based on examples]

An embodiment of the present invention will be described based on the drawings.
The figure is a block diagram of essential parts of an embodiment of the present invention. The communication bus 1 includes each information processing device ₂₀ to _2o.
is connected. Each information processing device 2 ₀ to 2 _o
Transmission buffers SB ₀₁ to SB ₀₃ , SB ₁₁ to _{SB 13} ,
SB _o1 to SB _o3 and reception buffers RB ₀₁ to _{RB 03} ,,
RB ₁₁ to RB ₁₃ and RB _o1 to _{RB o3} are provided, respectively. In addition, in the figure, SBC ₀ , SBC ₁ , and SBC _o indicate transmission buffer counters, and RBC ₀ , RBC ₁ , and RBC _o
indicates the reception buffer counter. This buffer counter indicates how many buffers are currently in use.

In addition, the information processing device ₂₀ that forms the core of the system
A deadlock release circuit 3, which is a feature of the present invention, is connected to. That is, the counter monitoring section 4 is connected to the transmission buffer counter SBC ₀ of the information processing device ₂₀ , this output is connected to the timer section 5, this output is led to the initial state setting section 6, and this output is used to set each information. They are guided to processing devices 2 ₁ to 2 _o , respectively.

The characteristic operation of the present invention will be explained using such a circuit configuration. The counter monitoring section 4 constantly monitors the value of the sending buffer counter SBC ₀ , and when the sending buffer counter SBC _{0 indicates the value when the buffer is full, it sends a set signal to the timer section 5, and when the sending buffer counter SBC 0} indicates the value when the buffer is full, it sends a set signal to the timer section 5, When the time has expired, a reset signal is sent to the timer section 5. Now, if the timer section 5 is set and there is no reset signal from the counter monitoring section for a certain period of time set in the timer section 5, that is, if the buffer is full for a certain period of time, the timer section 5 is set. The initial state setting section 6 operates based on the output. As a result, each information processing device 2 ₁ to 2 _o is initialized and the system is initialized.

[Explanation of effects]

As explained above, according to the present invention, when the communication buffer remains full for more than a certain period of time that occurs during normal operation, this is detected and the system is initialized.

Therefore, the deadlock state is automatically detected, and at this time, each information processing device can be automatically initialized to release the deadlock state. Therefore, it has excellent effects such as not requiring the intervention of a maintenance person and not requiring the installation of a dedicated line.

[Brief explanation of the drawing]

The figure is a block diagram of essential parts of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Communication bus, _21-2o ...Information processing device, 3...Deadlock release circuit, 4...Counter monitoring section, 5...Timer _section , 6...Initial state setting section.

Claims (1)

[Scope of Claims] 1. In a distributed processing method in which processing is distributed to a plurality of information processing devices and data is transmitted and received among the plurality of information processing devices and processed, the information is transmitted to the plurality of information processing devices. A counter monitoring circuit that monitors the contents of a transmission buffer counter of a processing device; a timer that is set when this counter monitoring circuit detects a predetermined value and reset when it detects a value below the predetermined value; 1. A distributed processing method, sometimes comprising means for setting and controlling the information processing device to an initial state.