JPS6252458B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated semiconductor device comprising a silicon semiconductor body separated from a silicon substrate by a pn junction and having an island provided with circuit elements.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated semiconductor device structure which allows the packaging density of circuit elements to be significantly higher than in conventional devices.

The present invention uses a buried silicon oxide layer pattern. Such a buried silicon oxide layer can be obtained by local oxidation of silicon as described in Japanese Patent Application No. 42-63883.

The integrated semiconductor device of the present invention includes a silicon substrate main body provided with an epitaxial silicon layer, a number of islands separated from the substrate by pn junctions and having a portion of the epitaxial silicon layer, and a plurality of islands each having a portion of the epitaxial silicon layer. a silicon oxide layer pattern embedded in the epitaxial silicon layer between the islands, the junctions separating the islands terminating in the buried oxide pattern, and at least one other resistive layer pattern; an island, the resistor having a contact area adjacent to the surface of the island, the contact area being laterally defined along at least a portion of its periphery by the buried silicon oxide layer pattern. It is characterized by being surrounded.

Preferably, the silicon oxide layer features are embedded within the epitaxial silicon layer throughout its thickness;
To this end, in the practice of the invention, the oxidation-resistant mask is used as an etching mask to locally remove part of the thickness of the silicon layer before the oxidation process, or At least part of the thickness of the silicon oxide layer already formed during the interruption is removed.

Significant space savings can be made due to the lack of spacing between the lateral separation of the islands and the base and collector contact areas of the transistors and the need to account for tolerances in these distances during the manufacture of the device. Such space savings can be about 40% over conventional devices with diffusion separation regions between islands. The fact that high-quality silicon oxide layers can be obtained by locally oxidizing silicon makes the device more active.
The pn junction can be terminated with a silicon oxide layer pattern.

The invention will now be explained with reference to the drawings.

First, a means for manufacturing a semiconductor device according to the principles of the present invention will be explained with reference to FIGS. 3 and 4. This semiconductor device has a semiconductor body 1 made of silicon,
A semiconductor circuit element, that is, a transistor consisting of an emitter region 2, a base region 3, and a collector region 4 is provided thereon. This transistor 2,
3, 4, a substantially planar silicon oxide layer is provided adjacent to the silicon body 1 in the form of a patterned layer 5 of silicon oxide, after which the surface portions not covered by the pattern are coated with e.g. Processes conventionally used in semiconductor technology, such as providing diffusion regions and contacts, are performed to form the transistor. The figure 5 is formed on the surface of the silicon body 1 by oxidation treatment, and during this oxidation treatment, the surface 6 of the silicon body is locally oxidized-resistant masked with a mask layer 7, and the figure 5 of silicon silicide is formed to approximately the thickness. It is entirely embedded within the silicon body 1 (see FIGS. 1 and 2).

As starting material, a silicon body 1 consisting of a silicon layer provided on a support 8 is used. The oxidation process continues during the formation of the silicon oxide features 5 until the features 5 extend through the entire thickness of the silicon layer 1, thus dividing the silicon layer 1 into a plurality of parts or islands separated from each other by the features 5. Divide into 9 to 17 parts.

The silicon layer 1 is provided as an epitaxial layer of one conductivity type on a support 8 of semiconductor material of the opposite conductivity type.

The support 8 is composed of, for example, a p-type silicon crystal having a resistivity of about 0.2 Ω-cm and a thickness of about 250 μm. The other dimensions of the support 8 are chosen appropriately so that the desired number of mutually insulated parts of the epitaxial layer 1 to be formed are sufficiently obtained.

To simplify the drawings, in FIGS. 3 and 4 a portion of the semiconductor device is shown which completely constitutes only one insulating portion or island 9 of the epitaxial layer 1. In FIG. Further, the insulating layer 20 shown in FIG. 3 is omitted in FIG. 4 for clarity. For this reason, in FIG. 4, the holes made in this insulating layer 20 are shown by broken lines.

An n-type epitaxial silicon layer 1 is provided on a p-type support 8 . This silicon layer 1 has a thickness of about 2 μm, for example.
It shall have a specific resistance of approximately 2Ω-cm. As shown in FIG. 1, an epitaxial layer 1 can be obtained by depositing semiconductor material on a support 8 in a manner commonly used in the semiconductor industry. The support 8 is selected to have a low resistivity compared to the resistivity of the epitaxial layer 1 in order to prevent the formation of conductive channels in the support directly beneath the patterned layer 5 to be formed. It is preferable to do so. Once formed, this conductive channel interconnects parts of epitaxial layer 1 that are separated from each other by patterned layer 5.

Epitaxial layer 1 is provided with a mask layer 7 which acts as an oxidation-resistant mask. In this example, this mask layer 7 is formed of silicon nitride, but it can also be formed, for example, of a double layer of silicon oxide and silicon nitride. The silicon nitride layer 7 is formed, as is customary, for example by coating the silicon bodies 1, 8 with SiH ₄ and
It can be prepared by heating to a temperature of about 1000 °C in a gas mixture of NH ₃ and its thickness is about 20μ
Let it be m. This thickness is significantly smaller than the thickness of the patterned layer 5 to be formed.

A portion of the silicon nitride layer 7 is first removed by photolithography.
It is removed as shown in the figure so that figure 5 can be formed.

In order to obtain features 5 embedded in the silicon layer 1 over almost the entire thickness, the oxidation-resistant mask layer 7 is used as an etching mask to etch the silicon layer 1 before starting the oxidation process for forming the features 5. Layer 1 is locally removed by etching to about half its thickness. In this way, grooves 21 are formed. The etching described above can be carried out in any conventional manner.

In this example, the silicon layer 1 is oxidized by introducing water vapor at a pressure of about 1 atmosphere and a temperature of about 1000° C. to obtain the figure 5. In this case, the oxidation treatment continues until the formed figure 5 reaches at least the substrate 8 (see FIG. 2).

The structure thus obtained is such that the epitaxial layer 1 is divided in a simple and effective manner into mutually insulated and mutually separated parts 9 to 17 by the features 5 embedded therein over almost its entire thickness. The part can be treated by a planar method and its feature 5 consists of high quality silicon oxide.

The oxidation process can be interrupted and during this interruption at least part of the thickness of the already formed silicon oxide layer can be etched away using the oxidation-resistant mask layer 7 as an etching mask. In this case, no etching treatment is required prior to the oxidation treatment.

Alternatively, it is also possible not to use an etching process at all. However, in this case protruding features 5 are obtained on the surface of the epitaxial layer 1, which is not necessarily a drawback. In some cases, the parts of the figure 5 that protrude above the epitaxial layer 1 can also be removed later by an etching process, in which case the oxidation-resistant mask layer 7
Use as an etching mask. In this way, it is possible to project the figure 5 slightly above the surface of the epitaxial layer or to draw it down slightly below the surface.

The insulated portion of the epitaxial layer, that is, the island 9~
17 between the n-type layer 1 and the p-type support 8
It is insulated from the support 8 by bonding.

Since the pattern 5 made of high-quality oxide is obtained and almost the entire thickness of the pattern 5 is buried in the epitaxial layer 1, circuit elements can be provided extremely effectively in the part to be insulated. A region of the circuit element adjacent to the surface and adjacent to the figure along at least a portion of its periphery is provided in the insulated portion.
By doing so, significant space savings can be achieved.

For example, in FIGS. 3 and 4, base region 3 of transistors 2, 3, 4 adjoins figure 5 along most of its periphery.

The base region 3 can be provided by impurity diffusion in a conventional manner. In this case silicon nitride layer 7 can be used as a diffusion mask. but,
In this case, as shown in FIG. 3, the nitride layer 7 is first removed and replaced by a silicon oxide layer 20, which is commonly used as a diffusion mask. For example, the p-type base region 3 obtained by boron diffusion is approximately 0.6
It has a thickness of .mu.m and is adjacent to the surface 23 of the insulated part 9.

An n-type emitter region 2 with a thickness of about 0.3 μm is then provided in the base region 3, for example by diffusion of phosphorus.
This emitter region 2 adjoins the surface 23 of the insulated part 9 .

The collector regions of the transistors 2, 3, and 4 are constituted by the portion 4 of the insulated portion 9. This portion 4 is adjacent to the base region 3.

p-n between base region 3 and collector region 4
The longitudinal part 24 of the junction is small and therefore the capacitance between the base region 3 and the collector region 4 is also small.

A contact area 25 is provided in the collector area 4 . The contact area 25 is adjacent to the surface 23 of the insulated part 9 . This contact region 25 has the same conductivity type as the collector region 4, and has a higher impurity doping concentration. The contact area 25 adjoins the graphic 5 along most of its periphery, resulting in further significant space savings. Contact area 25
can be provided simultaneously with the emitter region 2 by diffusion of phosphorus.

Holes 26, 27 and 28 are provided in silicon oxide layer 20 to allow contacts to be made to regions 2, 3 and 25. These contacts (not shown for clarity)
can be provided in any conventional manner and extend in the form of a metal layer to the insulating layer 10 and the figure 5.

If necessary, a buried layer having the same conductivity type as the collector region 4 and having a higher impurity doping concentration can be provided by a conventional method. Such a buried layer 30 is shown in broken lines in FIG.

The sizes of the insulated portion 9 and the regions 2, 3 and 25 shown in plan view in FIG. 4 are not critical to the measures according to the invention and may be selected by conventional means taking into account the desired characteristics of the transistor. Can be done.

However, the epitaxial silicon layer 1 is 2.5 to 3 μm thick.
Preferably, it is not thicker. Actually, figure 5
needs to be approximately the same thickness as silicon layer 1.
It is difficult to provide good quality features 5 with a thickness of 2.5 to 3 μm or more with a reasonable oxidation time.

According to the invention, in addition to transistors, other circuit elements such as diodes, resistors and capacitors can be provided in the insulating part of the epitaxial layer. For example, in FIG. 5, an insulated part 40 of the epitaxial layer 1 can be provided with two connection contacts 42 and 43 and can be used as a resistor.

It is often necessary to have a resistor consisting of a diffused region. Such a minimally space-occupying resistor is shown in cross-section in FIG. In the insulated part 50 of the epitaxial silicon layer 1, a resistive region 51 can be provided in the form of a surface region adjacent to the figure 5 over its entire periphery. As a result, the resistance region 51 provided in the insulated region 50 occupies a minimum space. Two connection contacts 52 and 53 are provided in this resistance region 51. Resistance area 5
1 can be obtained in the usual way by diffusion of impurities, which have a conductivity type opposite to that of the insulated part 50, or have the same conductivity type as the insulated part 50 but with a higher impurity doping concentration.

Alternatively, for example, two resistors each consisting of a diffused surface area may be provided in the insulated part of the epitaxial layer 1, these surface areas may be juxtaposed at a certain distance from each other, and the pattern 5 may be formed along a part of its periphery. can be adjacent to

Therefore, the above-mentioned measures not only make it possible to simply and effectively obtain a silicon oxide pattern 5 extending over the entire thickness of the epitaxial layer 1, but also to obtain a silicon oxide pattern 5 of a better quality and to improve the quality of this pattern 5. is silicon layer 1
It also has a substantially flat surface so that the area of circuit elements adjacent to the graphic 5 can be provided by conventional planar methods. This results in significant space savings, allowing greater packaging density of circuit elements and lower insulation and wiring capacitances.

It is clear that the invention is not limited to the examples described above, but that various modifications can be made within the scope of the invention. For example, the conductivity type of all parts of the semiconductor device described above can be simultaneously converted from p conductivity type to n conductivity type and vice versa.

If a large number of circuit elements are provided, these circuit elements can be interconnected in a conventional manner by conductive strips provided on the insulating layer 20 and the graphic 5. Insulating layer 20 can be made of an insulating material other than silicon oxide, such as silicon nitride. Instead of diffusion, the regions of the circuit elements can be provided, for example, by ion implantation. Furthermore, the emitter section 2 shown in FIGS. 3 and 4 can also be adjacent to the figure 5 along part of its periphery. Also, holes in the insulating layer 20 corresponding to contact areas adjacent to the figure 5, for example holes 27 and 28 corresponding to areas 3 and 25.
can be placed adjacent to the figure 5, thereby achieving further space savings. In addition, an epitaxial silicon layer of one conductivity type on a substrate of an opposite conductivity type can be provided with regions of opposite conductivity type and subsequently provided with silicon oxide features. The epitaxial layer can also be constructed, for example, as a double layer with a first partial layer of one conductivity type on the support and a second partial layer of the opposite conductivity type on top of the first partial layer.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views showing the manufacturing process of an integrated semiconductor device according to the principle of the present invention shown in FIGS. 3 and 4, FIG. 3 is a cross-sectional view along the line -- in FIG. is a plan view of the integrated semiconductor device of the present invention,
5 and 6 are sectional views, respectively, similar to FIG. 3, showing an embodiment of an integrated semiconductor device according to the present invention. 1...Epitaxial silicon layer (semiconductor body),
2... Emitter, 3... Base, 4... Collector, 5... Figure, 6... Semiconductor body surface, 7...
Mask layer, 8...Support, 9 to 17, 40, 50
... Island (insulating part), 20 ... Silicon oxide layer, 21
... Groove, 23 ... Surface (island), 25 ... Contact area, 26, 27, 28 ... Hole, 42, 43, 5
2, 53... Connection contact, 51... Resistance area.

Claims (1)

[Claims] 1 A silicon substrate body provided with an epitaxial silicon layer, a number of islands separated from the substrate by pn junctions and having a portion of the epitaxial silicon layer, and an oxidized portion of the epitaxial silicon layer. a silicon oxide layer pattern embedded in the epitaxial silicon layer between the islands, the junctions separating the islands terminating in the buried oxide layer pattern, and at least one other island having a resistance. , the resistor has a contact area adjacent to the surface of the island, the contact area being laterally surrounded by the buried silicon oxide layer shape along at least a portion of its periphery. An integrated semiconductor device characterized by: