JPS6252893B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a data conversion method.

Bit-parallel word-serial data with a two-dimensional structure in which each digit (bit) constituting a word is processed in parallel and the word is processed serially multiple times is extremely common in the information processing field. It is a data format. On the other hand, bit-serial data with a one-dimensional structure in which each bit constituting the data is processed serially, one bit at a time, requires a small number of interface lines to carry the data, as typified by data on a data communication line. This is a data format adopted for the purpose of digitizing data.

For example, when connecting a device that processes bit-serial data to a device that processes bit-parallel word-serial data, it is necessary to perform data processing in the bit-parallel word-serial data format after data processing in the bit-serial data format. In some cases, it may be necessary to convert bit-serial data to bit-parallel word-serial data.

This type of conventional data conversion method involves inputting one bit at a time to a shift register several times to form a word, and then inputting the bits held by the shift register to a bit parallel processing device that processes bit-parallel word-serial word-serial data. The operation of transferring words is repeated several times.

By the way, there are cases where the data definition, that is, the order of the bit arrays, do not match between the shift register and the bit parallel processing device. For example, in a shift register, due to the convenience of the hardware configuration of a device connected to the shift register other than the bit parallel processing device, control information and data controlled by the control information form multiple groups, and the two types of groups On the other hand, in a bit parallel processing device, the bit array is often such that each of the two groups is concentrated.

In such cases, conventional data conversion methods use a program to convert the bit-parallel word serial data, which is input to the bit-parallel processing device as it is defined in the shift register, into the data definition in the bit-parallel processing device. Therefore, it has the disadvantage of complicating the program and slowing down the system processing speed.

An object of the present invention is to provide a data conversion method that simplifies programs and improves system processing speed.

The method of the present invention is a data conversion method for converting input bit serial data into bit parallel word serial data and outputting the data, which includes a data storage means for storing the converted bit serial data, and a storage position of the bit serial data. address information storage means in which address information for specifying the address information is stored in advance, and a register that holds the address information read from the address information storage means when the bit serial data is stored in the data storage means. , the address information read into the register is used as the address for reading the next address information from the address information storage means, and one bit is sent to the data storage means based on the address information held in the register. After the bit serial data is stored by writing one word at a time, the data storage means is read out to output the bit parallel word serial data.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an application example of this embodiment.

Referring to FIG. 1, this embodiment includes a data storage circuit 1 as data storage means, an address storage circuit 2 as address information storage means, and a register 3.
, a switching circuit 4, a selection circuit 5, a shift register 40, and an adapter 1 which is a bit parallel processing device.
Contains 0.

Referring to FIG. 2, this application example includes two logic devices 50, 51 and two shift registers 40, 4.
1, two maintenance panels 30, 31, two data conversion devices 20, 21, and two adapters 10, 1
1, four sets of connecting wires 71, 70, 61, 60,
Three interface lines 300, 201, 200
and a data communication line 100.

Logical devices 50 and 51 are maintenance panels 30 and 3, respectively.
Internal signals of logic devices 50 and 51 are sent to logic devices 50 and 51 through shift registers 40 and 41, and connection lines 70 and 71 and 60 and 61, respectively. Since the logic device 50, shift register 40, and maintenance panel 30 and the logic device 51, shift register 41, and maintenance panel 31 are each housed in one package, the connection lines 60, 70, 61
and 71 can be short or large, and these connecting lines transfer multiple bits in parallel.

Typically, in this manner, logical devices 50 and 5
1 sends internal signals for maintenance to the maintenance panels 30 and 31, respectively, but the data communication line 100
It is also possible to send internal signals to remote locations via the . In particular, the frequency of such remote maintenance is increasing with the spread of information processing through data communication.

Internal signals sent from logic device 50 or 51 to adapter 10 or 11 via shift register 40 or 41 and data conversion device 20 or 21, respectively, are sent to a remote location connected via data communication line 100. adapter 10 or 11 for an internal signal similar to the internal signal supplied to the maintenance panel 30 or 31.
This conversion process is performed in bit parallel. Between adapters 10 and 11,
Interface wire 300 is adapted to carry bit-serial data because of the relative distance, for example, between different floors within the same building or between different buildings within the same factory.

The implementation housing the logic device 50 or 51 is installed in a computer room or a user's workplace,
Adapters 10 and 11 are data communication lines 100
For convenience of connection with the interface line 300, the interface line 200 and 201 are also configured to carry bit serial data because they are installed at a relatively long distance from the mounting body.

Data converters 20 and 21 operate to convert bit-serial data on interface lines 200 and 201, respectively, to bit-parallel word-serial data at adapters 10 and 11, respectively.
However, although the data definition of the bit serial data on interface lines 200 and 201 matches the data definition of the data in shift registers 40 and 41, respectively, this data definition is
The data definition for bit parallel word serial data in 0 and 11 is different. Therefore, the data converters 20 and 21 need to convert both data format and data definition.

Referring again to FIG. 1, the address storage circuit 2
The address information specifying the bit position and word position of the data storage circuit 1 is stored in the shift register 40.
It is written in advance by the number of bits of bit serial data SD inputted from SD so that the bit order becomes the bit permutation of bit parallel word serial data PD that is ultimately desired to be output, and is constructed of, for example, a read-only memory.

Address information in which the first bit of the bit serial data SD should be stored is initially set in the register 3.

The switching circuit 4 first accepts the word WW of the address information held by the register 3 and supplies it to the data storage circuit 1, and the selection circuit 5 receives the bit WB of the address information held by the register 3 to the data storage circuit 1. supply One bit of the bit serial data SD sent from the shift register 40 is stored in the position of the data storage circuit 1 specified by the word WW and the bit WB.

Word WW and bit held in register 3
WB is also supplied to the address storage circuit 2, and the address WA (=WW+
WB).

In this way, after reading the bits of the bit serial data SD from the address storage circuit 2 several times and storing the bit serial data SD in the data storage circuit 1, the switching circuit 4 accepts the word RW supplied from the adapter 10. It operates to supply data to the data storage circuit 1. From the data storage circuit 1, one word of the bit parallel word serial data PD is read out to the bit parallel processing device from the word position specified by the word RW.

FIG. 3, FIG. 4, and FIG. 5 are diagrams specifically explaining the operation of an embodiment of the present invention.

First, FIG. 3 shows the format of data converted in this embodiment, in which 8-bit bit serial data SD is input, and bit parallel word serial data PD of 4 bits x 2 words is output.

Therefore, the data storage circuit 1 in FIG.
Bit x 2 word configuration, address storage circuit 2 is 3
It consists of bit x 8 words, and the word
Both WW and RW consist of 1 bit, and bit WB consists of 3 bits. Word WW is equal to the upper 1 bit of address WA, and bit WB is equal to address WA.
is equal to the lower two bits of

FIG. 4 shows the contents of the data storage circuit 1 and address storage circuit 2 for each address WA at this time, together with the words WW, RW and bit WB. FIG. 5 is a time chart when bit serial data SD is stored in the data storage circuit 1 from the shift register 40.

In the above configuration, the shift register 4
Data storage circuit 1 converts bit serial data SD from 0 to
This section explains the operation when storing data in a file.

First, the address register 3 is initialized to "6". Referring to FIG. 5, address register 3
At timing t ₀ when the initial value "6" is set to "6", the address WA becomes "6", the word WW which is the upper 1 bit of the address WA is "1", and the address
WB, which is the lower two bits of WA, is "2".
Therefore, bit serial data SD is stored in bit 2 of word 1 of data storage circuit 1. Here, the storage position of data in the data storage circuit 1 will be explained. First, the word position is the output of the switching circuit 4, that is, the word designated by the word WW when storing data. When word WW is "0", word 0 is used, and when word WW is "1", word 1 is used. The bit position is the bit specified by the input WB of the selection circuit 5. The selection circuit 5 is a circuit that sends a write signal to the bit position of the data storage circuit 1 specified by the input WB, and when WB is "0", it sends a write signal to bit 0 of the data storage circuit 1. Similarly, when WB is "1", go to bit 1, and when WB is "2", go to bit 2.
This circuit sends a write signal to bit 3 when WB is "3".

Referring again to Figure 5, at timing _t0 when address register 3 is set to ``6'', the address
Since WA is "6", the output of address storage circuit 2 is the content of word 6 of address storage circuit 2, "2".
becomes. Therefore, at timing _t1 , the address register 3 is set to the output "2" of the address storage circuit 2 at timing _t0 . When “2” is set in address register 3, the word
WW becomes "0", WB becomes "2", and data "C" is stored in bit 2 of word 0 of data storage circuit 1. Further, the output of the address storage circuit 2 becomes "7", and "7" is set in the address register ₃ at timing t2. When “7” is set in address register 3, word WW becomes “1” and WB
is "3", so word 1 of data storage circuit 1
Data "H" is stored in bit 3 of the address storage circuit 2, and the output of the address storage circuit 2 becomes "0", and "0" is set in the address register ₃ at timing t3.

As can be understood, by repeating the above operation until timing _t7 , "ABCD" is stored in word 0 of data storage circuit 1 in bit order, and "EFGH" is stored in word 1.

Next, when reading the adapter 10 heavy parallel word serial data PD from the data storage circuit 1, the address "0" is first output to the word RW. Therefore, data "ABCD" stored in word 0 of data storage circuit 1 is read out. Subsequently, when address "1" is output to word RW, data "EFGH" stored in word 1 of data storage circuit 1 is read out.

Therefore, as shown in FIG. 3, the bit serial data "GCHAFDBE" can be converted into the bit parallel word serial data "ABCD" (word 0) and "EFGH" (word 1).

According to the present invention, by changing the data definition using a program in the bit parallel processing device, instead of converting bit serial data into bit parallel word serial data with a different data definition,
By adopting the above configuration, the data definition change program can be made unnecessary;
Programs can be simplified and system processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, FIG. 2 is an application example of this embodiment, and FIGS. 3, 4, and 5 are diagrams for explaining this embodiment. In the figure, 1...data storage circuit, 2...address storage circuit, 3...register, 4...switching circuit, 5...selection circuit, 10, 11...adapter,
20, 21...data conversion device, 30, 31...
Maintenance panel, 40, 41...Shift register, 50,
51...Logical device, 60, 61, 70, 71...
Connection line, 100...Data communication line, 200,2
01,300...Interface line, WW, RW
...Word, WB...Bit, WA...Address, PD...Bit parallel word serial data, SD...
...bit serial data.

Claims (1)

[Claims] 1. In a data conversion method that converts input bit-serial data into bit-parallel word-serial data and outputs the data, for specifying a data storage means for storing the converted bit-serial data and a storage location of the bit-serial data. an address information storage means in which address information of the address information is stored in advance;
A register is provided for holding the address information read from the address information storage means when the bit serial data is stored in the data storage means, and the address information read to the register is stored from the address information storage means. After storing the bit serial data by writing one bit at a time to the data storage means based on the address information held in the register, the data storage means is stored. A data conversion method characterized in that the bit-parallel word-serial data is read out and outputted.