JPS6252894B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a data conversion method.

Bit-parallel word-serial data with a two-dimensional structure in which each digit (bit) constituting a word is processed in parallel and the word is processed serially multiple times is extremely common in the information processing field. It is a data format. On the other hand, bit-serial data with a one-dimensional structure in which each bit constituting the data is processed serially, one by one, requires a small number of interface lines to convey the data, as typified by data on a data communication line. This is a data format adopted for the purpose of digitizing data.

For example, when connecting a device that processes bit-parallel word-serial data to a device that processes bit-serial data, it is necessary to perform data processing in the bit-parallel word-serial data format followed by data processing in the bit-serial data format. In some cases, it may be necessary to convert bit-parallel word-serial data to bit-serial data.

In this type of conventional data conversion method, a bit-parallel processing device that processes bit-parallel word-serial data outputs one word at a time to a shift register so that the bit order of the bit-serial data can be maintained, and the shift register outputs each word to a shift register. Each bit of the word is shifted one bit at a time and output.

By the way, there are cases where the data definition, that is, the order of the bit arrays, do not match between the bit parallel processing device and the shift register. For example, in a bit parallel processing device, the control information and the data controlled by it are arranged in a bit array that concentrates in a group, whereas in a shift register, the control information and the data controlled by the control information are arranged in a bit array that concentrates in a group. Due to the convenience of the hardware configuration of the device connected to the shift register, the control information and the data controlled thereby form a plurality of groups, and the bit array is such that the two types of groups are mixed. There are many cases.

In such cases, conventional data conversion methods use a program in a bit-parallel processing device to convert bit-parallel word-serial data into bit-serial data in a bit array that matches the data definition of the shift register. This has the drawback of complicating the program and slowing down the system processing speed.

An object of the present invention is to provide a data conversion method that simplifies programs and improves system processing speed.

The method of the present invention is a data conversion method that converts input bit parallel word serial data into bit serial data and outputs the data bit by bit. address information storage means pre-stored with address information for specifying output bit order; and address information read out from the address information storage means after the bit parallel word serial data is stored in the data storage means. The address information read into the register is used as the next address information reading address from the address information storage means, and the address information is read out based on the address information held in the register. The bit serial data is output by reading each bit from the data storage means.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an application example of this embodiment.

Referring to FIG. 1, this embodiment includes a data storage circuit 1 as data storage means, an address storage circuit 2 as address information storage means, and a register 3.
, a switching circuit 4, a selection circuit 5, an adapter 10 which is a bit parallel processing device, and a shift register 4.
Contains 0.

Referring to FIG. 2, this application example includes two adapters 10, 11 and two data conversion devices 20, 2.
1, two maintenance panels 30, 31, two shift registers 40, 41, two logic devices 50, 51, data communication line 100, three antenna face lines 2
00, 201, 300 and four sets of connecting wires 60,
70, 61, and 71.

Logical devices 50 and 51 are maintenance panels 30 and 3, respectively.
1 through shift registers 40 and 41, connection lines 60 and 61, and 70 and 71, respectively, maintenance signals for logic devices 50 and 51 can be received. Maintenance panel 30, shift register 40
Since the logic device 50, the maintenance panel 31, the shift register 41, and the logic device 51 are each housed in one package, the connection lines 60, 70, 6
1 and 71 can be short and large, and these connecting lines transfer multiple bits in parallel.

Normally, maintenance panels 30 and 31 are
The data communication line 100 is maintained from a remote location.
Maintenance of logical devices 50 and 51 can also be performed via. In particular, the frequency of such remote maintenance is increasing with the spread of information processing through data communication.

Data sent in bit series from a remote location via the data communication line 100 is sent to each maintenance panel 3.
It is converted in adapter 10 or 11 into a maintenance signal similar to the maintenance signal supplied to 0 or 31, but this conversion process is done bit-by-bit. Since the adapters 10 and 11 are relatively far apart, for example between different floors within the same building or between different buildings within the same factory, the interface wire 300 carries bit-serial data. It's becoming like that.

The implementation housing the logic device 50 or 51 is installed in a computer room or a user's workplace,
Adapters 10 and 11 are data communication lines 100
For convenience of connection with the interface line 300, the interface lines 200 and 201 are also configured to carry bit serial data because they are installed at a location relatively distant from the mounting body.

Data converters 20 and 21 operate to convert bit-parallel word-serial data on adapters 10 and 11, respectively, to bit-serial data on interface lines 200 and 201, respectively.
However, although the data definition of the bit serial data on interface lines 200 and 201 matches the data definition of the data in shift registers 40 and 41, respectively, this data definition is
The data definition for bit parallel word serial data in 0 and 11 is different. Therefore, the data converters 20 and 21 need to convert both data format and data definition.

Referring again to FIG. 1, the switching circuit 4 first receives the word WW supplied from the adapter 10 as many times as the number of serial words of the bit parallel word serial data and supplies it to the data storage circuit 1. bit parallel data PD is stored in the word position specified by word WW.

The address storage circuit 2 stores address information specifying the bit position and word position of the data storage circuit 1 as bit serial data SD to be finally output.
It is written in advance so that the number of bits corresponds to the bit permutation of the bit serial data SD, and is constituted by, for example, a read-only memory.

The register 3 is initially set with address information specifying the first bit position of the bit serial data SD.

Bit parallel data to the data storage circuit 1
When the storage of PD is completed, the switching circuit 4 accepts the word RW held in the register 3 and stores it in the storage circuit 1.
It operates to supply to. Bit parallel data at the word position specified by this word RW is read out from the data storage circuit 1 to the selection circuit 5, but among the bits of this parallel data, the bit RB held by the register 3 is specified. Only one bit is selected from the selection circuit 5 and output to the shift register 40.

Word RW and bit held in register 3
RB is also supplied to the address storage circuit 2, and the address information from the address storage circuit 2 is sent to the register 3.
Used as address RA (=RW+RB) for reading to.

FIG. 3, FIG. 4, and FIG. 5 are diagrams specifically explaining the operation of an embodiment of the present invention.

First, FIG. 3 shows the format of data converted in this embodiment, in which bit parallel data PD of 4 bits x 2 words is input, and 8 bit bit serial data SD is output.

Therefore, the data storage circuit 1 in FIG.
Bit x 2 word configuration, address storage circuit 2 is 3
It consists of bits x 8 words, and the word
Both WW and RW consist of 1 bit, address RA consists of 3 bits, and bit RB consists of 2 bits. Word RW is equal to the upper 1 bit of address RA,
Bit RB is equal to the lower two bits of address RA.

FIG. 4 shows the contents of data storage circuit 1 and address storage circuit 2 for each address RA at this time, together with words WW, RW and bit RB. FIG. 5 shows the contents of data storage circuit 1 to shift register 40.
This is a time chart for reading bit serial data SD.

In the above configuration, the operation when storing bit parallel data PD from the adapter 10 to the data storage circuit 1 will be explained.

First, data "ABCD" is output to the bit parallel data PD and address "0" is output to the word WW, and data "ABCD" is stored in word 0 of the data storage circuit 1. After that, the data “EFGH” is stored in the bit parallel data PD.
However, address "1" is output to each word WW, and data "EFGH" is stored in word 1 of data storage circuit 1.

Next, from the data storage circuit 1 to the shift register 4
The operation when reading bit serial data SD to 0 will be explained.

In this case, first, the address "6" is initialized in the address register 3.

Referring to FIG. 5, at timing t ₀ when address register 3 is set to "6", the address
RA is "6", word RW which is the upper 1 bit of address RA is "1", and lower 2 bit of address RA is "1".
Bit RB, which is a bit, becomes "2". Therefore, the output of the data storage circuit 1 becomes "FEGH", which is the content of word 1 of the data storage circuit 1, and the output of the selection circuit 5 becomes "G". Here, the selection circuit 5 is
If the output of data storage circuit 1 is "ABCD",
When bit RB is “0”, set “A”, bit RB
When bit RB is “1”, press “B”, and bit RB is “2”.
When bit RB is "3", "D" is selected and output, and when the output of data storage circuit 1 is "EFGH", bit RB is "0",
"E", "F" corresponding to "1", "2", "3",
This circuit selectively outputs "G" and "H" and inputs them to the shift register 40.

Further, at timing _t0 , the output RA of the address register 3 is "6", so the output of the address storage circuit 2 becomes the content "2" of the word 6 of the address storage circuit 2. Therefore, at timing _t1 , the address register 3 is set to the output "2" of the address storage circuit 2 at timing _t0 . When "2" is set in the address register 3, the word RW becomes "0" and the bit RB becomes "2", so the output of the data storage circuit 1 becomes "ABCD" and the output of the selection circuit 5 becomes "C". Become. Further, the output of the address storage circuit 2 becomes "7" and is set in the address register ₃ at timing t2.
When "7" is set in the address register 3, the output of the selection circuit 5 becomes "H" and thereafter the output of the selection circuit 5 becomes "A" at timing _t3 and "A" at timing _t4.
``F'', timing t <sub>5</sub> , ``D'', timing
At timing t ₆ , it becomes "B", and at timing t ₇ , it becomes "E".

As mentioned above, data "G", "C", "H", "A", "F", "D", "
B”,
“E” is output and input to the shift register 40. Therefore, the data "GCHAFDBE" is finally input to the register 40, and the bit parallel data "ABCD" and "EFGH" shown in FIG. 3 can be converted into the bit serial data "GCHAFDBE".

According to the present invention, by changing the data definition using a program in the bit parallel processing device, instead of converting bit parallel word serial data into bit serial data with a different data definition,
By adopting the above configuration, the data definition change program can be made unnecessary;
Programs can be simplified and system processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, FIG. 2 is an application example of this embodiment, and FIGS. 3, 4, and 5 are diagrams for explaining this embodiment. In the figure, 1...data storage circuit, 2...address storage circuit, 3...register, 4...switching circuit, 5...selection circuit, 10, 11...adapter,
20, 21...data conversion circuit, 30, 31...
Maintenance panel, 40, 41...Shift register, 50,
51...Logical device, 60, 61, 70, 71...
Connection line, 100...Data communication line, 200,2
01,300...Interface line, WW, RW
...word, RB...bit, RA...address,
PD...Bit parallel word serial data, SD...Bit serial data.

Claims (1)

[Claims] 1. In a data conversion method that converts input bit-parallel word-serial data into bit-serial data and outputs the bit-by-bit data, a data storage means for storing the bit-parallel word-serial data and an output bit order of the bit-serial data are provided. address information storage means in which address information for designation is stored in advance; and a register for holding the address information read out from the address information storage means after the bit parallel word serial data is stored in the data storage means. The address information read out to the register is used as the next address information reading address from the address information storage means, and the address information read out from the data storage means is used based on the address information held in the register. A data conversion method characterized in that the bit serial data is output by reading out one bit at a time.