JPS6253099B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing extraction circuit that extracts a timing signal from a received signal.

Conventionally, timing extraction circuits used in subscriber line digital transmission systems, etc. have been known to have a simple circuit configuration, with little jitter to occur, and a timing signal with the correct phase to be maintained even when there is a continuous pulseless state. required.

Conventionally, as a system that satisfies the above-mentioned conditions to some extent, an LC tank circuit has been used when the transmission speed is relatively high, and a digitally controlled phase-locked oscillator circuit (hereinafter referred to as DPLL circuit) is used when the transmission speed is low.
In the former case, the circuit is extremely simple and has the advantage of being relatively resistant to pattern jitter.
Values of ±2 to ±3% are achievable. In the latter case, the circuit can be implemented using only logic elements, and if a highly stable clock source such as a crystal oscillator is used as the basic clock, the correct timing signal can be maintained even when there is no pulse for a long time. It has the advantage of being able to

However, in the former case, the Q value of the LC tank circuit is usually a value of about 100, taking into consideration factors such as temperature changes, aging, detuning of the resonant frequency, and difficulty in realizing L with high Q. However, the number of consecutive zeros allowed in the input pulse train is 10~
For continuous zeros of about 20 bits or more, there is a drawback that S/N (signal-to-noise ratio) deterioration occurs due to timing deviation and attenuation of output amplitude. Also, in the latter case, although it does not have the disadvantages of using an LC tank circuit,
It has the disadvantage that pattern jitter is more likely to occur than a tank circuit, and considering the characteristics of various conventional DPLL circuits, it is difficult to suppress pattern jitter to less than ±10% of the input pulse time interval.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing extraction circuit that eliminates the above-mentioned drawbacks.

The timing extraction circuit of the present invention includes an LC tank circuit that extracts a timing signal from a received pulse train, and a clock signal that is supplied with the timing signal extracted by the LC tank circuit and is synchronized with the received pulse train in response to the timing signal. A digitally controlled phase synchronized oscillation circuit that outputs an output, a determination circuit that determines the presence or absence of a pulse in the received pulse train, and a counting circuit that counts the duration of the pulse-free state, the duration of which is constant at a preset value. 1. A timing extraction circuit characterized in that when a time period is reached, the output phase control operation of the digitally controlled phase synchronized oscillation circuit is stopped until the next pulse is detected.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows the circuit configuration of a conventional timing extraction circuit. In the figure, reference numeral 1 is a full-wave rectifier circuit, reference numeral 2 is an LC tank circuit, reference numeral 3 is a voltage comparator, and reference numeral 4 is a DPLL circuit.

In addition, FIG. 2a shows the input signal of the full-wave rectifier circuit 1,
The figure b shows the output signal of the full-wave rectifier circuit 1, the figure c shows the output signal of the tank circuit 2, and the figure d shows the voltage comparator circuit 3.
shows the output signal of As is clear from FIGS. 2a to 2d, in the conventional circuit, when a long series of zeros occurs in the input pulse train, the output signal level of the tank circuit 2 decreases, the S/N ratio deteriorates, and the output of the voltage comparator 3 However, this method has the disadvantage that output pulses with the correct phase cannot be obtained.

FIG. 3 is a configuration diagram showing an embodiment of the present invention. In the figure, reference number 1 is a full-wave rectifier circuit, reference number 2 is a LC tank circuit, reference number 3 is a voltage comparison circuit, reference number 4 is a DPLL circuit, reference number 5 is an AND gate, reference number 6 is a counter, and reference number is 7 is a set-reset type flip-flop, numeral 8 is a voltage comparison circuit, and numeral 9 is a reference voltage level generation circuit for the voltage comparison circuit 5.

FIGS. 4a to 4h show signal waveforms at various parts of this embodiment. FIG. 4a shows the output signal waveform of the full-wave rectifier circuit 1,
FIG. 2B shows the output waveform of the LC tank circuit 2, FIG. 1C shows the output waveform of the voltage comparison circuit 3, FIG. In the figure, f is a clock signal for operating the counter 6, g is an overflow signal of the counter 6, and h is an output signal of the AND gate 5.

In the figure, when the counter 6 counts up to 4, it outputs an overflow signal and resets the set/reset flip-flop 7. Also,
The output signal of the voltage comparison circuit 8 has the function of resetting the output of the counter 6 and setting the set-reset flip-flop 7 at the same time. Therefore, when a pulse signal is output from the full-wave rectifier circuit 1, the counter 6 is reset by the output signal of the voltage comparison circuit 8, the set/reset flip-flop 7 is set, and the output of the AND gate 5 is as follows. A signal obtained by binarizing the signal extracted by the LC tank circuit 2 from the output signal of the full-wave rectifier circuit 1 by the voltage comparator circuit 3 appears as it is, and becomes an input signal to the DPLL circuit 4. When the output pulse signal appears at the output of the full-wave rectifier circuit 1 at a time interval shorter than the time interval at which the counter 6 overflows, the set/reset flip-flop 7 is always kept in the set state. However, if the state in which no pulse appears at the output of the full-wave rectifier circuit 1 continues, the counter 6 overflows, the set/reset flip-flop 7 is reset, and the AND gate 5 is reset.
is closed, DPLL circuit 4 becomes free run state,
The output phase state just before the AND gate closes is maintained, and the signal with degraded S/N due to continuous zeros is
This can prevent the output jitter of the DPLL circuit from increasing.

As described above, the present invention has the effect of being able to perform highly accurate timing extraction because it is possible to prevent the output jitter of the DPLL circuit from increasing.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a conventional timing extraction circuit, FIGS. 2 a to d are signal waveform diagrams of each part of the circuit in FIG. 1, and FIG. Figures a to h are signal waveform diagrams of each part of this embodiment. In the figure, 1...Full wave rectifier circuit, 2...LC
Tank circuit, 3, 8... Voltage comparator circuit, 4... Digitally controlled phase synchronized oscillator, 5... AND gate, 6... Counter, 7... Set/reset flip-flop.

Claims (1)

[Claims] 1 Extract the timing signal from the received pulse train
an LC tank circuit; a digitally controlled phase synchronized oscillator circuit which is provided with a timing signal extracted by the LC tank circuit and outputs a clock signal synchronized with the received pulse train in response to the timing signal; and a pulse of the received pulse train. a determination circuit that determines the presence or absence of a pulse, and a counting circuit that counts the duration of the pulse-free state, and when the duration reaches a preset constant time, the output of the digitally controlled phase synchronized oscillation circuit A timing extraction circuit characterized in that a phase control operation is stopped until the next pulse is detected.