JPS625375B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an edge-triggered flip-flop circuit having a JK flip-flop function and having a short propagation delay time. Various types of flip-flops (hereinafter abbreviated as F.F) are known. J-K type F.
F means that when two data inputs become high level at the same time at a certain time T _o , the next time T _{o +1}
The output at is F·F, which is the inverse of the output at time T _o . An edge-triggered F-F that has the function of such a J-K type F-F, and whose output is inverted at the leading edge of the clock input, and also has a fast switching speed, has not been known in the past. Nakatsuta. Edge-triggered D type F/F has the advantage of using fewer gates and short propagation delay time, but J
- Does not have the function of K type F/F. On the other hand, the master/slave JK type F/F has stable operation, but has the disadvantage of using a large number of gates and a long propagation delay time. The object of the present invention is to
The purpose of this invention is to propose a new type of F/F circuit that has the KF/F function, uses fewer gates, and has a short propagation delay time. To achieve this object, the flip-flop circuit of the present invention includes an inverter for inverting the clock signal; a first data input signal, an output signal of the inverter, an output signal of the third gate element, and an output signal of the fifth gate element. a first gate element coupled to a second data input signal, an output signal of the inverter, a fourth gate element output signal, and a sixth gate element output signal; gate elements; a third gate element coupled to the output signal of the first gate element and a clock signal; and a fourth gate element coupled to the output signal of the second gate element and the clock signal. a first latch circuit formed by cross-connecting each other so that other outputs are coupled to inputs; a third latch circuit;
a fifth gate element coupled to the output of the fourth gate element; and a sixth gate element coupled to the output of the fourth gate element.
and a second latch circuit formed by cross-connecting gate elements such that the other outputs are coupled to the inputs, and each gate element is a NAND circuit or a second latch circuit.
It is characterized by being one type of NOR circuit. Examples will be described below. FIG. 1 is a circuit diagram showing the structure of an embodiment of a flip-flop circuit according to the present invention. This example is
A flip-flop circuit according to the present invention is constructed using a NAND gate, and is particularly suitable as a TTL element. In the same figure, 1, 2, 3, 4, 5
and 6 is a NAND gate, and 7 is an inverter. 8 and 9 are data input terminals, 10 is a clock input terminal, 11 and 12 are output terminals, 13 is a preset terminal, 14 is a clear terminal,
15, 16, 17 and 18 are output lines of gates 1, 2, 3 and 4, respectively, and 19 is an output line of inverter 7. Hereinafter, a high logic level will be abbreviated as "H" and a logic low level will be abbreviated as "L". FIG. 2 shows the circuit shown in FIG. 1 when the signal at terminal 13 and the signal at terminal 14 are both "H", and the signal K at terminal 8 and the signal J at terminal 9 are both "H". This is a time chart showing the operation state of each part in the case of an operation when the signal CLK at the terminal 10 is alternately inverted, that is, a toggle operation. The operation of this circuit will be explained below using this case as a representative. In the figure, 1 is the signal of the clock input terminal 10.
CLK, 2 is the signal C on the line 17, 3 is the signal D on the line 18, 4 is the signal Q on the output terminal 11, 5 is the signal on the output terminal 12, 6 is the signal on the line 1
9, 7 shows the signal B on the line 16, and (8) shows the signal A on the line 15, respectively. First, in the initial state, each signal is J=K=“H”,
==“H”, CLK=“L”, Q=“L”,

= “H”, then C=D=A=“H”,
B=“L”. This situation is illustrated with timing in FIG. From this state, the clock signal CLK is inverted.
When CLK becomes "H", the inputs of gate 3 become all "H", so the signal C is inverted and C becomes "L", and the output of gate 7 is also inverted and becomes "L".
becomes. This situation is illustrated with timing in FIG. Next, since the signal C is added to one input of the gate 5, the signal Q becomes
is inverted and Q becomes “H”, and since the signal is added to one input of gate 2, =
By becoming “L”, signal B is inverted and B
= “H”. This situation is illustrated with timing in FIG. Further, since the signal Q is applied to one input of the gate 6, when Q becomes "H", the signal is inverted and becomes "L". This state is the second
The timing is shown in the figure. Note that after the above timing, the signal = “L” (signal CLK = “H”), and in this state, data input is prohibited, and no matter what signals come as signals J and K, the output signal is No change occurs in Q. This period is marked a in FIG. Next, the clock signal CLK is inverted and CLK="L"
Then, since the signal CLK is applied to one input of the gate 3, the signal C is inverted and becomes C="H" and restored. Further, due to the inversion of the signal CLK, the signal is also inverted and becomes ``H'' and restored. This situation is illustrated with timing in FIG. Note that since the signal becomes “H”, gates 1 and 2 output signals J and K, respectively.
becomes ready to be loaded. This period is marked b in FIG. Furthermore, since the signal becomes "H", the inputs of the gate 1 become all "H", so that the signal A is inverted and becomes A="L". This situation is illustrated with timing in FIG. The above timing or operation is the operation for one cycle of the clock signal CLK, and by starting the timing state as the initial state again, the timing ,′,′,
At ' and ', the signals D and A, the signals Q, D and signals, and the signals B are inverted, respectively, and the states of each part return to their initial states. In this way, the flip-flop circuit of the present invention shown in FIG. 1 can operate as a positive edge triggered J-KF/F in which the output state is inverted at the leading edge of the rising edge of the clock signal. can. In this case, the propagation delay time from the rise of the clock signal to the inversion of the output signal is the propagation delay time t _PLH = 2 gates passing through when transitioning from low level to high level, and when transitioning from high level to low level. It can be seen from FIG. 2 that when transitioning to the level, the propagation delay time t _PHL = 3 gates passing through. In the conventional master/slave J-K type F/F, t _PLH = 3 gates and t _PHL = 4 gates. Table 1 lists the functions of the flip-flop circuit of FIG. 1 described above.

[Table] In Table 1, Q ₀ , ₀ indicates the output at time T _{o -1 with respect to the output Q at time T o} . FIG. 3 is a circuit diagram showing the structure of another embodiment of the flip-flop circuit of the present invention. This example is
A flip-flop circuit according to the present invention is constructed using a NOR gate, and is particularly suitable as an ECL element. In the same figure, 21, 22, 23,
24, 25 and 26 are NOR gates, and the other symbols represent the same as in FIG. In the case of Figure 3, when a signal is applied to terminal 8, a signal is applied to terminal 9, a signal is applied to terminal 10, a signal is applied to terminal 13, and a signal CLR is applied to terminal 14, terminal 1
The output Q at terminal 1 and the output at terminal 12 are exactly similar to the circuit of FIG. The propagation delay time for this circuit is t _PLH = 3 gates when transitioning from low level to high level, and t _PHL when transitioning from high level to low level.
= 2 gates passed. In addition, in the conventional master-slave J-KF/F, t _PLH = 4 gates, t _PHL
= 3 gates passed. Table 2 lists the functions of the flip-flop circuit of FIG.

[Table] As explained above, according to the flip-flop circuit of the present invention, when a NAND gate is used, the transition of the clock signal from "L" to "H"
When a NOR gate is used, the transition of the clock signal from "H" to "L" causes an inversion of the output Q, and the clock signal becomes "L" or "H".
In the steady state of data inputs J, K (or
) changes, no change occurs in the output Q,. In other words, when using a NAND gate, as a positive edge triggered J-KF/F,
When a NOR gate is used, it operates as a negative edge triggered J-KF/F. The flip-flop circuit of the present invention has a small number of constituent gates, so the number of elements and power consumption are also small.
In addition, it has many advantages such as not only short propagation delay time but also perfect logic as a J-K type F/F and balanced electrical characteristics as the circuit form is completely symmetrical. . Hitherto, there has been no example of a positive edge triggered type J-KF/F being commercialized, and the flip-flop circuit of the present invention has made it possible for the first time. Furthermore, since the flip-flop circuit of the present invention has a circuit configuration using standardized gates, it is very convenient for custom LSI implementation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the flip-flop circuit of the present invention, FIG. 2 is a time chart showing the operation of the circuit of FIG. 1, and FIG. 3 is another embodiment of the flip-flop circuit of the present invention. FIG. 1, 2, 3, 4, 5, 6...NAND gate, 7
...Inverter, 8, 9...Data input terminal, 1
0... Clock input terminal, 11, 12... Output terminal, 13... Preset terminal, 14... Clear terminal, 15, 16, 17, 18, 19... Output line, 21, 22, 23, 24, 25 ,26...
NOR gate.

Claims (1)

[Claims] 1 an inverter for inverting a clock signal; a first gate element coupled to a first data input signal, an output signal of the inverter, an output signal of a third gate element, and an output signal of a fifth gate element; 2
a second gate element coupled to the data input signal of the inverter, the output signal of the fourth gate element, and the output signal of the sixth gate element; a third gate element coupled to the output signal of the second gate element and a fourth gate element coupled to the clock signal; and a fourth gate element coupled to the output signal of the second gate element and the clock signal. a first latch circuit connected to the output of the third gate element;
and a sixth gate element coupled to the output of the fourth gate element are cross-connected to each other so that the other outputs are coupled to the input; Each gate element is NAND
A flip-flop circuit characterized by being either one type of circuit or a NOR circuit.