JPS6254247B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a programmable timer that can arbitrarily generate certain required time data.

Conventional configuration and its problems Conventionally, a presettable timer is a presettable counter integrated circuit in which at least two flip-flop circuits (hereinafter referred to as FF) are integrated in its timekeeping (counting) part. The configuration is such that one or more of these are connected in cascade. And the clock as input is the first stage F-F
The clocks of the next and subsequent stages use the output of the F-F of the previous stage, and the ripple carry asynchronous method in which the response of each F-F is performed like a game of chess, and the clock input of the F-F of all stages is used. In common, there is a synchronization method in which the outputs of all FFs are obtained at the same time. The disadvantage of the above-mentioned asynchronous method is that the F-F of each stage responds in a chess-like manner as described above, so there is a time difference between the clock input timing and the output determination time of the final stage F-F, and the preset value is changed by this time difference. This is the error for It goes without saying that this error increases in proportion to the total number of FFs. On the other hand, in the synchronization method, the outputs of all F-Fs are determined almost simultaneously with respect to the clock input timing, so there is no error with respect to the preset value, but the input data of F-Fs that determines the output state at each stage is is generated between a clock input and the next clock input by the outputs of each stage and their logic circuits, so the disadvantage is that the time interval of the input clock, that is, the maximum frequency, is lower than that of the asynchronous method. be. This is true, for example, in the case of a synchronous type bipolar IC.
While the limit is about 40MHz, the asynchronous method can count up to about 100MHz. Therefore, if the required time data is highly accurate and has very high resolution (for example, if the time data is 10 ns, the input clock frequency will be 100 MHz), it will be necessary to use the above-mentioned synchronous method or asynchronous method only. The current situation is that it is difficult to realize this.

OBJECTS OF THE INVENTION The present invention relates to a necessary time data generation circuit, and particularly relates to a counter constituting this circuit.
The object of the present invention is to provide a programmable timer that can generate arbitrary time data with high accuracy even in the clock frequency domain where the response speed of an IC is a problem.

Structure of the Invention The programmable timer of the present invention includes an asynchronous preset counter circuit that can arbitrarily set a time delay value, and an asynchronous correction counter circuit that counts the time width as an output of the preset counter circuit. and a correction means for correcting the preset value of the preset counter circuit so that the count value of the correction counter circuit matches the target time delay value, and the correction means is configured to correct the preset value of the preset counter circuit from the initial output of the preset counter circuit. It is configured to have a value obtained by subtracting the count data of the correction counter circuit as a correction value, and to use time data obtained by subtracting this correction value as a preset value, thereby reducing the time width due to the response delay factor of the preset counter circuit. It is characterized by correcting the error of and obtaining the desired time delay value with high accuracy.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below based on the drawings.

The drawing shows a block diagram of the programmable timer of the present invention. 1 is a clock generation circuit that determines the resolution of time data (minimum step time unit of time data) and time accuracy, and here it is 100MHz.
It has a built-in crystal oscillator. 2 and 3 are clock signals output from the clock signal generation circuit 1, respectively.
The gate circuit 5 for controlling the passage of CK is an asynchronous preset counter circuit that updates the count value preset by the clock passed through the gate circuit 3 until the count value is completed. Reference numeral 4 denotes an asynchronous correction counter circuit for counting the time width as the output of the preset counter circuit 5, and counts the number of clocks passing through the gate circuit 2. 6 is a flip-flop which is set by the timer start signal 10 and reset by the counting end signal 13 of the preset counter circuit 5; 7 is a microcomputer (hereinafter referred to as μc) having time data input/output and arithmetic processing functions; ]. 14 is a counter reset signal outputted from μc7 to the correction counter circuit 4; 15 is a count data bus for outputting the count value of the correction counter circuit 4 to μc7; and 16 is a preset value given from μc7 to the preset counter circuit (5). This is a preset data bus for

The finally required time data is input to the μc7, and the μc7 initially continuously supplies the value as it is to the preset counter circuit 5 via the preset data bus 16. It is reset by the counter reset signal 14. The flip-flop circuit 6 (hereinafter referred to as F-F6) is reset in the initial state, and the logic of its output puts the preset counter circuit 5 in the preset state,
Time data from μc7 has already been taken in internally. That is, in this reset state of F-F8, time data can always be input to the preset counter circuit 5.
Similarly, when this F-F6 is in a reset state, gate circuits 2 and 3 are closed, and the logic of the output Q of F-F6 as a timer output at this time is non-active (not in an output state). .

When the timer start signal 10 is input, the F-F6 is set to the set state, the timer output 11 is activated (output state), the preset counter circuit 5 is set to the counting mode, and the gate circuits 2 and 3 are opened. Make it. Here, the clock frequency of clock generation circuit 1 is 100M as described above.
Hz, therefore, the correction counter circuit 4 and the preset counter circuit 5 use a 10 ns clock signal.
The count value is updated at the CK cycle. When the preset counter circuit 5 has updated all the preset input data, it outputs a counting end signal 13 and resets F-F6. Therefore, the timer output 11 also becomes inactive, and the gate circuits 2 and 3 are also closed. At this time, the count value of the correction counter circuit 4 matches the number of clocks input to the preset counter circuit 5. However, what is important here is that this count value does not match the value of the time data previously input to the preset counter circuit 5, but is a slightly larger value.
The reason for this is that, as already mentioned in the disadvantages of the asynchronous type, the internal F--
This is because an error occurs corresponding to the response delay of F. That is, if the number of internal FFs constituting this preset counter circuit 5 is, for example, eight, and the input/output delay time per one is, for example, 10 ns, then the clock signal CK is inputted until the final clock signal is input. It will take 80 ns to ensure the internal FF output of the stage. In other words, even if the preset data value is "1", eight 10ns clocks will be input before the updated output of "1" is obtained.Therefore, in this example, 80ns will be applied to all preset values. It will be added. Conversely, it is not possible to obtain a timer output of 80 ns or less. Furthermore, this error value varies depending on the integrated circuit used and is also influenced by environmental conditions such as temperature changes. Thus, the timer output value held in the correction counter circuit 4 is determined by the counting end signal 13.
When the μc7 confirms the error, the error is taken into the μc7, the error is calculated, and the correction value, that is, the value obtained by subtracting the error from the time data input value, is sent to the preset counter circuit 5. Output to. Therefore, the timer output value from the second time onwards completely matches the time data input value.

As described above, according to this embodiment, the preset counter circuit 5 for obtaining the time delay value,
By preparing another counter that counts the number of clocks input to this, and correcting the preset value of the preset counter so that the value counted by this counter matches the target time data value. A highly accurate timer with no errors is realized.

In the above embodiment, the value obtained by subtracting the count data of the correction counter circuit 4 from the initial output of the preset counter circuit 5 is used as a correction value, and the μc7 is used as a correction means that uses time data obtained by subtracting this correction value as a preset value. I am using it, but these are μc
7, and can be easily realized by a hard logic circuit using a comparator or an addition/subtraction integrated circuit. Also, it is not necessary to check and correct the timer output value every time; for example, it may be done only at the initial reset when the power is turned on, or just before a timer output request occurs, depending on the usage conditions. All you have to do is decide.

Effects of the Invention As explained above, according to the program timer of the present invention, in addition to the preset counter circuit for obtaining the original time delay value, the preset value of the preset counter circuit is corrected to check the timer output value. We prepared a correction counter circuit for It is possible to guarantee highly accurate time delay values up to the limit frequency.

[Brief explanation of the drawing]

The drawing is a block diagram of one embodiment of the programmable timer of the present invention. 1... Clock generation circuit, 2, 3... Gate circuit, 4... Correction counter circuit, 5... Preset counter circuit, 6... Flip-flop circuit, 7
...Microcomputer, 13...Counting end signal, 15...Counting data bus, 16...Preset data bus.

Claims (1)

[Claims] 1. An asynchronous preset counter circuit that can arbitrarily set the time delay value, an asynchronous correction counter circuit that counts the time width as an output of this preset counter circuit, and a count value of this correction counter circuit. and a correction means for correcting the preset value of the preset counter circuit so that the time delay value coincides with the target time delay value, and the correction means subtracts the count data of the correction counter circuit from the initial output of the preset counter circuit. A programmable timer characterized in that it has a value as a correction value, and time data obtained by subtracting this correction value is used as a preset value.