JPS6255736B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog waveform modulation/demodulation circuit used in an adaptive delta modulation/demodulation circuit.

A delta modulation method is one method of analog-to-digital conversion or digital-to-analog conversion. Conventional modulation (encoding) in this delta modulation method involves converting the difference between the input analog signal A and the output signal B of the integrator 1 into the synthesizer 2 as shown in FIG.
The residual signal S is then quantized bit by bit in a 1-bit quantization circuit 3. Integrator 1
attempts to bring the integrated output signal B (that is, the internal analog signal for input waveform evaluation) closer to the input analog signal A by integrating this quantized digital signal D through the delay circuit 4.

2a to 2c show timing charts for explaining the modulation operation in FIG. 1. Time t _o
Since the input signal A _o is higher than the evaluation internal signal B _o , the residual signal S _o obtained by calculating the difference between the two signals A _o and B _o has a positive value. In this way, when the residual signal S _o is a positive value, the logical value of the digital signal D is “1”.
The 1-bit quantization circuit 3 performs an operation of giving a logical value of "0" when the residual signal _So is negative. The signal quantized by this circuit 3 is output as a coded sequence D _o as a digital output of analog-to-digital conversion. Further, this digital signal D is delayed by one sampling period by the delay circuit 4 shown in FIG. 1, and is input to the integrator 1 at time t _{o +1} . This integrator 1 receives this delayed signal T _o
When is logic “1”, the _minute amount (Δ;
delta) and create a new B _o+1 signal (B _o+1 = B _o +
Δ), and conversely, when the signal T _o is logic “0”, a certain minute amount of data Δ is subtracted from the signal B _o to create a new B _{o +1} signal (B _{o +1} = B _o − Δ). and input the evaluation internal signal B to the analog signal A.
try to get closer to In other words, the fact that the signal T _o is logic "1" is the result of 1-bit quantization of the signal S _o , which means that the signal B _o is lower than the signal A _o . In order to bring the signal B _o closer to the signal A _o , It is necessary to make the signal B _o high, and conversely, when the signal T _o is a logic "0", the signal B _o needs to be made low. Therefore, the value of the evaluation internal signal B o ₊₁ at time t o ₊₁ is a very small amount Δ compared to the signal B _o at time t _o
It will be made more expensive.

In FIG. 2, at time t _o+1 , the residual signal S o+1 between the input analog signal A _o+1 and the evaluation internal signal (B _{o +1} = B _{o +} Δ) is a positive value, and the logic “1” is output to the encoded string. This logic "1" signal is delayed by one sampling period by the delay circuit 4 and T
It is input to integrator 1 as _o+2 signal, and integrator 1 adds a very small amount Δ to signal B _o++1 to generate B _o+2 signal (B _o+2
=B _o+1 +Δ=B _o +2・Δ).
Moreover, at time t _o+2 , the input analog signal A _o+2 becomes lower than the evaluation internal signal B _o+2 , and the residual signal S _o+2
is a negative value. Therefore, a logic "0" is output to the encoded string, and the integrator 1 subtracts a very small amount Δ from the signal B _o+2 at time t _o+3 to obtain the B _o+3 signal (B _o+3 = B _o+2 −Δ=B _o +Δ) is output.

As described above, the encoded string contains "1, 1,
0, . . .'' are serially output, which means that the input analog signal A _o waveform has been digitized.

Decoding (referred to as digital-to-analog conversion or decoding) is simpler than encoding (referred to as encoding), and is performed by integrating the input digital signal E at each sampling period as shown in FIG. In other words, the digital input is logic “1”
When , there is a very small amount Δ in the demodulated signal
, and conversely, when the logic is "0", a very small amount Δ is subtracted from the signal X. This operating waveform is shown in FIG.

Since the delta modulation method is 1-bit encoding,
With respect to the original analog signal at a steady level, the demodulated signal repeats level changes of +Δ and -Δ as shown in FIG. 5, and this step-like change causes distortion of the original analog signal. This distortion is called granular noise. Furthermore, as shown in FIG. 6, when the original analog signal changes rapidly, the evaluation internal signal cannot follow it, resulting in a delay. This distortion is called overload noise. This granular noise and overload noise are particularly problematic when the original analog signal is voice. In other words, when a voice signal is modulated and then demodulated and listened to, it becomes a ``whirring'' noise and the clarity of the voice decreases. This is a fatal drawback in a system that records audio waveforms, which are analog signals that are susceptible to noise from transmission lines, as digital signals that are resistant to noise and disturbances, and then converts them into analog signals and extracts them when necessary. Generally, to reduce this granular noise, it is sufficient to reduce the Δ amount, and to reduce overload noise, it is sufficient to increase the Δ amount. However, reducing both of these two noises is contradictory and is impossible under the condition that the amount of Δ is constant in the delta modulation method. Therefore, an adaptive delta modulation/demodulation method (adaptive differential pulse code modulation/demodulation method) in which the amount of Δ is varied has been developed.

In this adaptive delta modulation/demodulation method, the Δ amount is reduced in sections where the analog signal does not change significantly to suppress granular noise, and the Δ amount is increased in areas where the analog signal changes significantly to reduce overload noise. The method for determining this Δ amount is to first set a certain initial value, and if the same code continues in the coded string in modulation or the 1-bit coded string in demodulation (for example, “00”)
or "11"), the Δ amount is increased, and in the case of opposite signs (for example, "01" or "10"), the Δ amount is decreased. In other words, the Δ amount is determined using the code D _{o -1} one sampling period before the current code D _o , and this is expressed by the following equation.

Δn=(Δ _o-1 , D _o , D _o-1 ) ...(1) Equation (1) above is an example of determining the Δ amount using the two-bit sign D _o and D _o-1 . However, the code D _o-2 one sampling period earlier may also be used to determine the amount of Δn, as shown in the following equation.

Δn=(Δ _o-1 , D _o , D _o-1 , D _o-2 ) (2) A conventional circuit of such an adaptive delta modulation/demodulation system is shown in FIG. In the figure, an integrator 5 is comprised of an internal register 6 for analog signal evaluation and an addition/subtraction circuit 7 for integral calculation, and the calculation data is approximately 8 to 12 bits. Further, the Δ amount calculation circuit 8 is composed of a Δ amount register 9 and a Δ amount calculation adder/subtractor 10, and the number of data bits thereof is about 8 to 12 bits. The output of the internal register 6 in the integrator 5 is
The signals are guided to a first digital-to-analog converter (D/A converter) 11 for modulation and a second D/A converter 12 for demodulation, each of which is made up of, for example, a resistance ladder. The first D/A converter 11 receives, for example, 10
Digital data input of bits (0 to 1023) is converted into an analog quantity and sent to the voltage comparator 13, where it is compared with the input analog signal to perform 1-bit quantization. Further, during demodulation, the second D/A converter 12 converts the digital signal from the register 6 into analog and outputs an analog signal.

During modulation operation in the circuit of FIG.
It remembers things from the past about the sampling period. That is, the current code _Do , the code Do _-1 from one sampling period ago, and the code Do _-2 from two sampling periods ago are stored. And the control circuit 14 is
A Δ amount addition command and a Δ amount subtraction command are generated according to the sign _Do , and when these signs _Do , _Do-1 , _{and Do-2} are all equal (“0, 0, 0” or “1 ,1,
1”), a Δ amount up signal that increases the Δ amount is output to the Δ amount calculation circuit 8, and in other cases, the Δ amount up signal is output to the Δ amount calculation circuit 8.
A Δ amount down signal that decreases the amount is output. The Δ amount calculation circuit 8 receives such a signal, and
Δ whose initial value is set in advance from the control circuit 14
An adder/subtractor 10 performs a predetermined operation on the contents of the amount register 9 to increase or decrease the Δ amount. In other words, Δ
As shown in equation (2) above, the amount is determined by Δ _o- 1 one sampling period before and the code group D _o , D _o-1 , D _o-2 . This Δ amount is input to the integrator 5, where the Δ amount is added or subtracted (integral calculation) to a value initially set from the control circuit 14 in response to a Δ amount addition command or a Δ amount subtraction command. That is, when the adder/subtractor 7 commands to add the data in the analog signal evaluation internal register 6 (D _o =
Δ amount is added to “1”), and when subtracting command (D _o =
“0”), the amount Δ is subtracted. Therefore, the output of the D/A converter 12 will be increased or decreased depending on the output of the register 6, and will approach the input analog signal. In this way, the adaptive delta modulation operation is performed, and a serial encoded signal is output from the digital output terminal.

In the case of demodulation, data is received at the digital input terminal, and Δ
A second signal for demodulation is obtained by performing quantity calculation and Δ quantity addition/subtraction.
An analog signal is output through the D/A converter 12. In this case, voltage comparator 13 is not used.

When integrating the circuit shown in FIG. 7 described above, the number of elements in the adders/subtracters 7 and 10 becomes a problem. In other words, the number of adders and subtracters 7 and 10 exceeds half of the total number of circuit elements, which increases the chip size of the integrated circuit and increases the cost.

The present invention was made in view of the above circumstances, and
By adopting a circuit configuration in which one arithmetic circuit is used in a time-sharing manner, the number of arithmetic circuits can be reduced, thereby making it possible to reduce the number of integrated circuit elements and chip size, thereby reducing costs. The purpose is to provide an analog waveform modulation/demodulation circuit.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows an analog waveform modulation/demodulation circuit according to the present invention, which is used in an adaptive delta modulation/demodulation circuit. In the figure, the analog signal evaluation internal register 20 is configured to have a data length of, for example, 10 bits, and the Δ amount register 21 is configured to have a data length of, for example, 12 bits. This evaluation internal register 20
Each of the 10-bit outputs is connected to the input terminals _A1 to _A10 of each adder of the arithmetic circuit 22 via a clocked inverter _I1 operated by a clock pulse CP1. Each of the 10-bit outputs of the Δ quantity register 21 is also connected to the input terminals _{A1 to A10 of} each of the adders through a clocked inverter I3 operated by a clock pulse CP3.
The output of the upper 6 bits of the internal evaluation register 20 is sent via the clocked inverter _I2 operated by the clock pulse CP2, and to the Δ quantity register 2.
The output of the upper 6 bits of 1 is clock pulse CP4.
The signals are multiplexed via the clocked inverter I ₄ operated by the input terminals B ₁ to B ₆ of the lower 6 bits of the arithmetic circuit 22 via the corresponding exclusive OR gate 23. It's summery. At this time, the exclusive OR gate 23 is controlled by the output of a logic circuit 24 which performs a logical operation between the clock pulse CP4 and an up-down signal 10, which will be described later. Also,
Input terminal B ₇ of the upper 6 bits of the arithmetic circuit 22
~ _B12 contains the inverted signal 10 of the most significant bit D10 of the evaluation internal register 20 at the time of the clock pulse CP2, the signal EXD for instructing the increase/decrease of the Δ amount at the time of the clock pulse CP3, and the clock pulse.
At the time of CP4, the up-down signal uD that instructs to decrease the evaluation internal register 20 by the amount Δ (however, when the logic is "0", and conversely when the logic is "1", the up-down signal uD is increased by the amount Δ) is multiplexed. The output of the logic circuit 25 is input. Further, the carry input terminal C in each adder of the arithmetic circuit 22 and the carry output terminal Ca of the preceding stage are connected in cascade, and the carry input terminal _C1 of the least significant bit has a logic "1" when the clock pulse CP2 is received.
signal, and when the clock pulse is CP3, the signal EXD
Logic circuit 2 that multiplexes the up-down signal uD at the time of clock pulse CP4.
6 outputs are added. In addition, the Δ amount register 21
The outputs 11 and 12 of the upper two bits are connected to the 11th and 12th bit input terminals A ₁₁ and A ₁₂ of the arithmetic circuit 22 via inverters I ₅ and I ₆ . In addition, each adder output Si of the arithmetic circuit 2 is
It is connected to the input terminal D of the corresponding bit stage of the internal evaluation register 20 and the Δ quantity register 21, respectively.

Next, the analog waveform modulation/demodulation circuit configured as described above is connected to the internal register 6, Δ
The operation when the quantity register 9 and the adders/subtractors 7 and 10 are replaced will be explained with reference to the time chart of FIG. In this circuit, one sampling period is divided into three timing periods T1, T2, and T3. In the timing period T1, the ninth
Clock pulses CP1, CP as shown in figures a and d
2 opens the clocked inverters I ₁ and I ₂ . Therefore, the output data 1 to 10 from the internal evaluation register 20 are input to the input terminals A ₁ to _{A 10} of _each adder of the arithmetic circuit 22 via the clocked inverter I 1 , and the upper 6 bits of the register 20 are The output data 5 to 10 pass through the clocked inverter _I2 , and then are led to the exclusive OR gate 23 together with the output of the logic circuit 24, where they are inverted and sent to the arithmetic circuit 22.
is applied to input terminals B ₁ to C ₆ of each adder. Further, the inverted signal 10 of the most significant bit data D10 of the internal register 20 is inputted from the logic circuit 25 to input terminals B ₇ to _{B 12} of the upper six bits of the adder of the arithmetic circuit 22 . Based on these input data, the arithmetic circuit 22 performs an operation to approximately multiply the absolute value of the value in the evaluation internal register 20 by 15/16. This calculation is performed for the following purposes. For example, during demodulation, if the digital data repeats logic "1" and "0", the analog signal will repeat changes in the amount of Δ as shown in FIG.
511 to -512), it does not necessarily swing near zero, that is, at the center of the amplitude of the analog output signal obtained by analog conversion of the output of this register 20. Therefore, the absolute value of the value in the register 20 is decreased and brought closer to zero so that the analog signal during the repetition of "1" and "0" swings around the amplitude center of the analog output. this is,
Even though the digital data repeats logic "1" and "0", if the integrated circuit receives only logic "1" due to noise, disturbance, etc. on the data transmission line, it will become analog as shown in Figure 12. This is to prevent the analog signal from operating deviated from its amplitude center after the amplitude position of the signal rises. In other words, as shown in FIG. 10, the amplitude of the analog signal is prevented from increasing abnormally, and its amplitude center is brought back to the amplitude center of the analog output.

Then, in the timing period T2 of FIG. 9, the clock pulses as shown in FIGS. 9b and 9c are generated.
CP3 and CP4 create clocked inverters I ₃ and I ₄
opens. Therefore, the output data 1 to 10 of the Δ quantity register 21 are applied to the input terminals A ₁ to A ₁₀ of each adder of the arithmetic circuit 22 via the clocked inverter I ₃ , and the upper 6 bits of the Δ quantity register 21 are Data 7 to 12 are clocked inverters.
It is applied to the input terminals B ₁ to _{B 6} of the arithmetic circuit 22 via I ₄ and the exclusive OR gate 23 . At this time,
If the EXD signal instructing an increase in the amount of Δ is logic “1”, the output “1” of the logic circuit 26 is
It is supplied to the carry input terminal _C1 of 2, and the arithmetic circuit 22
will perform the following operation.

Δ _o+1 =63/64 Δn+1 (3) Furthermore, when the EXD signal is logical “0” and an instruction to decrease the Δ amount is given, the arithmetic circuit 22 performs the following operation.

Δ _o+1 =63/64 Δn (4) In the next timing period T3, clocked inverters I ₁ and I ₄ are opened by clock pulses CP4 and CP1 as shown in FIG. 9c and d. Therefore, output data 1 to 10 of the internal evaluation register 20 are input to each input terminal A ₁ to A ₁₀ of the arithmetic circuit 22 via the clocked inverter I ₁ , and the upper six bits of the Δ quantity register 21 are The outputs 7 to 12 of are led to the exclusive OR gate 23 along with the output of the logic circuit 24 via the clocked inverter _I4 , and the output of this gate 23 is input to the input terminal _B1 of the arithmetic circuit 22.
~B input into ₆ . At this time, the arithmetic circuit 22
If the signal uD instructing an increase/decrease by the amount of Δ in the evaluation internal register 20 is logic "1", the output of the logic circuit 24 at this time is "1", and the gate 23
The output data of, that is, the amount Δ is subtracted from the value of the evaluation internal register 20, and conversely, if the signal uD is logic "0", the output data of the gate 23 due to the output "0" of the logic circuit 24 at this time, In other words, the calculation is performed such that the amount is increased by the amount Δ.

In the circuit shown in Fig. 8, each operation result at T ₁ , T ₂ , and T ₃ is stored in the corresponding register 2.
0 and 21 are supplied with a clock for data reading.

According to the analog waveform modulation/demodulation circuit described above, 1
By using two arithmetic circuits 22 in a time-sharing manner, arithmetic operations can be performed on the analog evaluation internal register 20 and the Δ amount register 21, and there is no need to use two arithmetic circuits as in the conventional case. Therefore, when the circuit is integrated, the number of elements can be reduced to about 3/4 of the conventional one, and the chip size can also be reduced, making it possible to lower the cost.

In the above embodiment, the analog evaluation internal register 20 is configured with 10 bits, the Δ amount register 21 is configured with 12 bits, and the arithmetic circuit 22 is configured with 10 bits, but other bit numbers may be used.

As explained above, according to the present invention, the number of arithmetic circuits is reduced by using a circuit configuration in which one arithmetic circuit is used in a time-sharing manner, thereby reducing the number of integrated circuit elements and chip size. Accordingly, it is possible to provide an analog waveform modulation/demodulation circuit that enables cost reduction.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the conventional delta modulation method.
Fig. 2 is a timing chart shown to explain the modulation operation in the circuit shown in Fig. 1, Fig. 3 is a block diagram of a conventional demodulation circuit, and Fig. 4 is a waveform diagram shown to explain the circuit operation of Fig. 3. , FIG. 5 and FIG. 6 are waveform diagrams for explaining the operation of the delta modulation circuit of FIG. 1, FIG. 7 is a circuit diagram showing a conventional adaptive delta modulation/demodulation circuit, and FIG. 8 is an embodiment of the present invention. A configuration diagram of an analog waveform modulation/demodulation circuit according to an example, FIG. 9 is a timing chart shown to explain the operation of FIG. 8,
FIGS. 10 to 12 are waveform diagrams showing the operation of the circuit of FIG. 8, respectively. 20... Internal register for analog signal evaluation, 21
...Δ quantity register, 22... Arithmetic circuit, 23... Exclusive OR gate, 23-26... Logic circuit, I ₁ - I ₄ ...
clocked inverter.

Claims (1)

[Claims] 1. In an analog waveform modulation/demodulation circuit that performs analog signal evaluation calculations including △ quantity calculation and △ quantity addition/subtraction in an adaptive delta modulation/demodulation circuit, an analog signal evaluation register that holds analog signal input as digital data, and an analog signal evaluation register that holds analog signal input as digital data. A △ quantity register that holds the minute (△) increment/decrement amount of data to be held, a △ quantity operation that increases or decreases this △ quantity, and an analog signal that at least increases or decreases the absolute value of the data in the analog signal evaluation register by △ quantity. comprising an arithmetic circuit that executes an evaluation operation, and a data transfer control circuit that transfers data held in both registers to the arithmetic circuit in a time-sharing manner when the arithmetic circuit performs the Δ quantity operation and the analog signal evaluation operation; An analog waveform modulation/demodulation circuit characterized in that one arithmetic circuit is used in a time-sharing manner to execute analog signal evaluation calculations including Δ quantity calculations and Δ quantity addition/subtraction.