JPS6313606B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a Δ
Related to quantity calculation circuits.

A delta modulation method is one method of analog-to-digital conversion or digital-to-analog conversion. Conventional modulation (encoding) in this delta modulation method involves converting the difference between the input analog signal A and the output signal B of the integrator 1 into the synthesizer 2 as shown in FIG.
The residual signal S is then quantized bit by bit in a 1-bit quantization circuit 3. Integrator 1
attempts to bring the integrated output signal B (that is, the internal analog signal for input waveform evaluation) closer to the input analog signal A by integrating this quantized digital signal D through the delay circuit 4.

2a to 2c show timing charts for explaining the modulation operation in FIG. 1. At time t _o , the input signal A _o is higher than the evaluation internal signal B _o , so the residual signal obtained by taking the difference between both signals A _o and B _o
S _o becomes a positive value. In this way, when the residual signal S _o has a positive value, the logic value of the digital signal D is given "1", and when the residual signal S _o is negative, the logic value "0" is given. The bit quantization circuit 3 performs this. The signal quantized by this circuit 3 is output as a coded sequence D _o as a digital output of analog-to-digital conversion. Further, this digital signal D is delayed by one sampling period by the delay circuit 4 shown in FIG. 1, and is input to the integrator 1 at time t _o+1 . This integrator 1 detects a minute amount (Δ; delta) in the signal B _o when the delayed signal T _o is logic “1”.
is added to create a new B _o+1 signal (B _o+1 = B _o +Δ),
Conversely, when the signal T _o is logic “0”, an integration operation is performed to subtract a certain minute amount of data (Δ) from the signal B _o and create a new B _{o +1} signal (B _{o +1} = B _o − Δ). As I get older,
An attempt is made to bring the evaluation internal signal B closer to the input analog signal A. In other words, the fact that the signal T _o is logic "1" is the result of 1-bit quantization of the signal S _o , which means that the signal B _o is lower than the signal A _o .
In order to bring B _o closer to signal A _o , signal B _o needs to be made high, and conversely, when signal T _o is logic "0", signal B _o needs to be made low. Therefore, the value of the evaluation internal signal B _o+1 at time t _o+1 is
Compared to the signal B _o at t _o , the signal is increased by a very small amount Δ.

In Figure 2, at time t _o+1 , the residual signal _S o+1 between the input analog signal A _o+1 and the evaluation internal signal (B _o+1 = B _o +Δ) is a positive value, and the logic “1” is output to the encoded string. This logic “1” signal is delayed by one sampling period by the delay circuit 4 and T _o+2
is input to integrator 1 as a signal, and integrator 1 receives the signal as
Adding a small amount Δ to B _o+1 produces a B _o+2 signal (B _o+2 = B _o+1
+Δ=B _o +2・Δ). Furthermore, at time T _o+2 , the input analog signal A _o+2 is lower than the evaluation internal signal B _o+2, and the residual signal S _o+2 takes a negative value. Therefore, logic "0" is output to the encoded string, and the integrator 1 subtracts a very small amount Δ from the signal B _o+2 at time t _o+3 to obtain the B _o+3 signal (B _o+3 = B _{o +2} −Δ=
B _o +Δ) is output.

As described above, the encoded string contains "1, 1,
0,...'' will be serially output, meaning that the input analog signal A _o waveform has been digitized.

Decoding (referred to as digital-to-analog conversion or decoding) is simpler than encoding (referred to as encoding), and is performed by integrating the input digital signal E at each sampling period as shown in FIG. In other words, the digital input is logic “1”
When , there is a very small amount Δ in the demodulated signal
, and conversely, when the logic is "0", a very small amount Δ is subtracted from the signal X. This operating waveform is shown in FIG.

Since the delta modulation method is 1-bit encoding,
With respect to the original analog signal at a steady level, the demodulated signal repeats level changes of +Δ and -Δ as shown in FIG. 5, and this step-like change results in distortion of the original analog signal. This distortion is called granular noise. Further, when the original analog signal changes rapidly as shown in FIG. 6, the evaluation internal signal cannot follow it and a delay occurs. This distortion is called overload noise. This granular noise and overload noise are particularly problematic when the original analog signal is voice. In other words, when an audio signal is modulated and then demodulated and listened to, it may become a "sound" noise.
This results in a decrease in the clarity of the voice.
This is a fatal flaw in a system that records audio waveforms, which are analog signals that are susceptible to noise from transmission lines, as digital signals that are resistant to noise and disturbances, and then converts them into analog signals and extracts them when necessary.
Generally, to reduce this granular noise, it is sufficient to reduce the Δ amount, and to reduce overload noise, it is sufficient to increase the Δ amount. However, reducing both of these two noises is contradictory, and is impossible under the condition that the amount of Δ is constant in the delta modulation method. Therefore, an adaptive delta modulation/demodulation method (adaptive differential pulse code modulation/demodulation method) in which the amount of Δ is varied has been developed.

In this adaptive delta modulation method, the Δ amount is reduced in sections where the analog signal does not change significantly to suppress granular noise, and the Δ amount is increased in areas where the analog signal changes significantly to reduce overload noise. The method for determining this Δ amount is to first set a certain initial value, and if the same code continues in the coded string in modulation or the 1-bit coded string in demodulation (for example, “00”)
or "11"), the Δ amount is increased, and in the case of opposite signs (for example, "01" or "10"), the Δ amount is decreased. That is, the current sign
The Δ amount is determined using the code Do _-1 one sampling period before Do, and _this is expressed by the following equation.

Δn=(Δ _o-1 , D _o , D _o-1 ) ...(1) Equation (1) above is an example of determining the Δ quantity using the two-bit sign D _o and D _o-1 . However, the code D _o-2 one sampling period earlier may also be used to determine the amount of Δn, as shown in the following equation.

Δn=(Δ _o-1 , D _o , D _o-1 , D _o-2 ) (2) A conventional circuit of such an adaptive delta modulation/demodulation system is shown in FIG. In the figure, an integrator 5 is comprised of an internal register 6 for analog signal evaluation and an addition/subtraction circuit 7 for integral calculation, and the calculation data is approximately 8 to 12 bits. Further, the Δ amount calculation circuit 8 is composed of a Δ amount register 9 and a Δ amount calculation adder/subtractor 10, and the number of data bits thereof is about 8 to 12 bits. The output of the internal register 6 in the integrator 5 is:
A first digital-to-analog converter (D/A
converter) 11 and a second D/A converter 12 for demodulation. The first D/A converter 11 receives, for example, the data from the register 6 during modulation.
10-bit (0-1023) digital data input is converted into an analog quantity and sent to the voltage comparator 13, where it is compared with the input analog signal to perform 1-bit quantization. Further, during demodulation, the second D/A converter 12 converts the digital signal from the register 6 into analog and outputs an analog signal.

During modulation operation in the circuit of FIG.
It remembers things from the past about the sampling period. In other words, the current code D _o , the code one sampling period ago, D _o-1 , and the code two sampling periods ago
I remember D _o-2 . And the control circuit 14 is
A Δ amount addition command and a Δ amount subtraction command are generated according to the sign D _o , and when these signs D _o , D _o-1 , and D _o-2 are all equal (“0, 0, 0” or “1 ,1,
1”), a Δ amount up signal that increases the Δ amount is output to the Δ amount calculation circuit 8, and in other cases, the Δ amount up signal is output to the Δ amount calculation circuit 8.
A Δ amount down signal that decreases the amount is output. The Δ amount calculation circuit 8 receives such a signal, and
Δ whose initial value is set in advance from the control circuit 14
An adder/subtractor 10 performs a predetermined operation on the contents of the amount register 9 to increase or decrease the Δ amount. In other words, Δ
The amount is determined by Δ _o- 1 one sampling period before and the code groups D _o , D _o-1 , and D _o-2 as shown in equation (2) above. This Δ amount is input to the integrator 5, where the Δ amount is added or subtracted (integral calculation) to a value initially set from the control circuit 14 in response to a Δ amount addition command or a Δ amount subtraction command. In other words, the adder/subtractor 7 adds the data in the analog signal evaluation internal register 6 by an amount of Δ when D _o = “1” when an addition is commanded, and subtracts an amount of Δ when D _o = “0” when a subtraction command is commanded. . Therefore, the output of the D/A converter 12 will be increased or decreased depending on the output of the register 6,
It becomes closer to the input analog signal. In this way, the adaptive delta modulation operation is performed, and a serial encoded signal is output from the digital output terminal.

In the case of demodulation, data is received at the digital input terminal, and Δ
A second signal for demodulation is obtained by performing quantity calculation and Δ quantity addition/subtraction.
An analog signal is output through the D/A converter 12. In this case, voltage comparator 1
3 is not used.

FIG. 8 shows details of the Δ amount calculation circuit 8. In the figure, the Δ quantity register 9 consists of 12 registers, and the Δ quantity calculation adder/subtractor 10 consists of 12 adders. The data Δ1 to Δ12 at each output terminal Q of the register are applied to the input terminals A ₁ to _{A 12} of the corresponding adder. Further, each output terminal S ₁ to _{S 12} of the adder is connected to the data input terminal D of the corresponding register, and each carry input terminal C ₂ to _{C 12} of the adder is connected to the carry output terminal Ca ₁ to Ca of the previous adder. Connected to ₁₁ . Furthermore, the inverted outputs 7 to 12 of the upper 6 bits of the Δ quantity register 9 are added to the input terminals B ₁ to B ₆ of the lower 6 bits of the adder, and the input terminals C ₁ and 6 of the lowest adder of the adder/subtractor 10 Bit adder input terminal B ₇ ~
A signal EXD is applied to _B12 , which instructs to decrease the Δ amount when the logic is "1" and to increase the Δ amount when the logic is "0".

When this signal EXD is logic "1", the output data Δ1 to Δ12 of the Δ amount register 9 are input to the input terminals A ₁ to A ₁₂ of the adder, and the input terminals B ₁ to _{B 6} of the lower 6 bits are output from the Δ quantity register 9.
The inverted outputs Δ7 to 12 of the upper 6 bits of the Δ quantity register 9 are input to the input terminals _B7 to _B12 of the upper 6 bits, and the logic " ₁ " signal is input to the carry input terminal C1 of the least significant bit, respectively. Ru. As a result, the Δ amount calculation circuit 8 calculates the current value of the Δ amount register 9.
Assuming Nn (in this case Nn is 0 to 4095),
By performing calculations such as the following formula, the following Δ amount
Calculate N _o+1 .

The first term on the right side of equation (3) above, _No , is the data added to the A input terminals _A1 to _A12 of the adder, and the second term, _o /64, is N obtained by shifting the value of _No by 6 bits. This data is an inverted signal of 1/64 of the value of _o and is applied to the B input terminals _B1 to _B6 of the adder.
The third term is the logic "1" signal of the signal EXD and is data applied to the adder's carry input terminal _C1 and the upper 6 bits of the B input terminals _B7 to _B12 . The above equation (3) can be calculated as the above equation (4), and in the end the value of N _o is 63/
That's 64 times. The above signal EXD is logic “0”
When , the B input terminal of the upper 6 bits of the adder B ₇
~ B ₁₂ and the data added to the carrier input terminal C ₁ of the least significant bit become “0”, and the other A
Data is applied to the input terminal and the B input terminal using the above signal.
This is the same as when EXD is "1". Therefore, the arithmetic circuit 8 performs calculations as shown in the following equation.

N _o+1 = N _o + {63−I _ot (N _o /64)} ……(5) 63/64N _o +63 ……(6) The first term N _o on the right side of equation (5) above is Data added to the A input terminals A ₁ to A ₁₂ of the adder, the second
The term 63−I _ot (N _o /64) is equivalent to subtracting the inverted data of 1/64 of the value of N _o obtained by shifting the value of N _o by 6 bits from the numerical value 63, and as a result, (6) of the ceremony
63/64N _o +63, which is the data applied to the lower 6 bits of the B input terminals B ₁ to B ₆ .

The Δ amount is calculated by the above calculation, and in order to examine the characteristics of this Δ amount calculation, the above equations (4) and (5) are modified as follows.

N _o+1 −N _o = −1/64N _o signal (EXD) = “1” …(7) N _o+1 −N _o = −1/64N _o +63 signal (EXD) = “0” … (8) In other words, the above equation (7) represents the amount of decrease in the Δ amount when the signal (EXD) = “1”, and when the signal (EXD) = “0”
The above equation (8) expresses the amount of increase in the amount of Δ when . From equations (7) and (8) above, it can be seen that the larger the value of N _o is, the larger the amount of decrease is, and the smaller the amount of increase is.
Conversely, the smaller the value of N _o , the smaller the amount of decrease;
The amount of increment becomes large, and this prevents the amount of Δ from reaching its maximum or minimum.As shown in Figure 9, the amount of Δ is centered around the value of "2048" and is divided into an increment line U and a decrease line D. It will oscillate between.

In this way, in the past, the center of the Δ quantity was set at one half of the number that could be expressed by the Δ quantity, but when the analog waveform changed rapidly, the center of the Δ quantity was set higher (in Figure 9, it was set to the right side). If the Δ amount decrease is not increased, distortion will occur.Conversely, when the amplitude of the analog waveform is small, the Δ amount center is lowered (moved to the left in Figure 9) and the Δ amount increment is increased. This enables good modulation and demodulation. However, conventionally, the Δ
It was impossible to shift the center of the quantity.

The present invention was made in view of the above circumstances, and
In an adaptive delta modulation/demodulation circuit, the center of the Δ amount is raised or lowered when the analog waveform changes rapidly, and the center of the Δ amount is lowered when the amplitude of the analog waveform is small. Provides a Δ amount calculation circuit that reduces noise and distortion associated with modulation and demodulation and enables faithful modulation and demodulation of analog waveforms by having a circuit configuration that allows the center of Δ amount to be moved by executing calculation control. The purpose is to

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 10 shows a Δ amount calculation circuit of the present invention, in which the Δ amount register 20 and the Δ amount calculation unit 21 each have, for example, a 12-bit configuration. Further, each output data Δ1 to Δ12 from the output terminal Q of each register of the Δ quantity register 20 is added to the A input terminal A ₁ to A ₁₂ of each adder of the Δ quantity calculator 21, and is applied to each data input terminal of the register. D is connected to the output terminals S ₁ to S ₁₂ of the corresponding adder. The upper 6 bits of output data Δ7 to Δ12 of the Δ amount register 20 are controlled by a control means such as a clocked inverter _I1 operated by a control signal such as an inverted signal of the signal instructing increase/decrease in the Δ amount described above.
B input terminal _B1 of lower 6 bits of adder through
~ B ₆ and further this Δ amount register 20
The upper 7 bits of the output data Δ6 to Δ12 are applied to the lower 7 bits of the adder at the B input terminals _B1 to _B7 through a control means such as a clocked inverter _I2 operated by a control signal such as the signal EXD. It's summery. In addition, the above signal EXD is
The signal EXD is applied to the carry input terminal _C1 of the least significant bit of the adder and the B input terminals _B8 to _B12 of the upper five bits of the adder, and the above signal EXD is applied to the inverter _I3 and a clocked inverter operated by the signal.
It is applied to the 7th bit B input terminal _B7 of the adder via _I4 . The carry output terminals Ca ₁ to _{Ca 11} of each of these adders are connected to the carry input terminals C ₂ to C ₁₂ of the next-stage adder. Further, a clock pulse is applied to the clock input terminal CK of the Δ amount register 20.

In the Δ amount calculation circuit configured as described above, if the signal EXD is now logic "1", the clocked inverter _I2 operates, and this clocked inverter
The upper 7 bits of data Δ6 to Δ12 of the Δ quantity register 20 are applied to the lower 7 bits of the B input terminals B ₁ to _B7 of the adder through _I2 . Further, a logic "1" signal is input to the carry input terminal _C1 of the least significant bit of the adder and the B input terminals _B8 to _B12 of the upper five bits. Therefore, the current value of the Δ amount register 20 is N _o ,
Assuming that the value after the calculation is N _{o +1} , the calculation circuit executes the calculation of the following relationship based on the above input data.

Next, when the signal EXD is logic "0", the clocked inverter _I1 operates, and through this clocked inverter _I1 , the upper 6 bits of data Δ7 to Δ12 of the Δ amount register 20 are transferred to the lower 6 bits of the adder. is applied to the B input terminals B ₁ to _{B 6} of . In addition, a logic "0" signal is sent to the B input terminals _B8 to _B12 of the upper five bits of the adder, and a logic "0" signal is sent to the B input terminal _B7 of the seventh bit via the inverter _I3 and the clocked inverter _I4 . A logic "0" signal is applied. Therefore, the arithmetic circuit performs the following operations.

N _o+1 = N _o + {63−I _ot (N _o /64)} ...(11) 63/64N _o +63 ...(12) From the above equations (10) and (12), the amount of Δ decreases The amount and the incremental amount are each expressed by the following equations.

N _o+1 −N _o = −N _o /32 (signal EXD="1") ...(13) N _o+1 −N _o = −N _o /64+63 (signal EXD="0") ...( 14) The formulas for the increment and decrease of these Δ amounts are expressed in a graph as shown in FIG. As can be seen from Fig. 11, compared to the conventional Fig. 9, the signal
It shows a characteristic in which the amount of decrease in the Δ amount calculation when EXD = "1" is doubled, and the amplitude center of the Δ amount (that is, the point where the amount of increase and the amount of decrease in the Δ amount are equal) is changed from the conventional "2048" to "1365". '', and as a result, it has Δ amount calculation characteristics suitable even for analog signals with small amplitudes during modulation and demodulation.

FIG. 12 shows a second embodiment of the invention. This circuit uses the clock signal that operates the clocked inverter described above in reverse. That is, an inverted signal is used for the clocked inverter _I2 for transferring the upper 7 bits of output data Δ6 to Δ12 of the Δ quantity register 20, and a clock signal for transferring the upper 6 bits of output data Δ7 to Δ12 is used. The clocked inverter _I1 uses the signal EXD, and the clocked inverter _I4 for transferring the signal EXD uses the signal EXD. By doing this, the above (13)
Equation (14) can be changed as follows.

N _o+1 −N _o = −N _o /64 (When signal EXD="1") ...(15) N _o+1 −N _o = −N _o /32+127 (When signal EXO="0" ) ...(16) Expressing equations (15) and (16) above as a graph, the 13th
The result will be as shown in the figure. According to the characteristics shown in this graph, compared to the conventional figure 9, the amount of increase in the Δ amount calculation when signal EXD = “0” is doubled, and the amplitude center position of the Δ amount is It will move from "2048" to around the value of "2709". As a result, it exhibits Δ amount calculation characteristics that reduce overload noise when the analog signal changes rapidly during modulation and demodulation.

FIG. 14 shows a third embodiment of the invention. In this circuit, the aforementioned clocked inverter _I1 is operated by the first clock pulse φ1, and the clocked inverters _I2 and _I4 are operated by the second clock pulse φ2. The arithmetic circuit is controlled by providing a logic circuit 22 which arbitrarily obtains these first and second clock pulses φ1, φ2 and their inverted clock pulses φ1, 2. That is, this logic circuit 22 connects four AND gates AG, two NOR gates NG, and two inverters I as shown in the figure, and outputs control signals con1 to
These clock pulses φ1, φ2, 1, 2 are obtained by logically processing con3, 1 and the Δ amount increase/decrease instruction signal EXD used as a control signal as described above.
In this logic circuit 22, control signals con1 to con3
By setting the control signal con1 input to logic "1", φ ₁ = "0" and φ ₂ = "1", so that inverter I ₂ operates and inverter I ₁ does not operate, so as shown in FIG. The circuit is equivalent to the circuit shown in FIG. 8 described above. Also, by setting the control signal con2 input to logic “1”, the EXD signal “1”,
Since φ ₂ and φ ₁ become “1” in response to “0”, the first
The circuit shown in FIG. 4 is equivalent to the circuit shown in FIG. 12 described above. In addition, by setting the control signal con3 input to logic "1", φ ₁ and φ ₂ become "1" in response to "1" and "0" of the EXD signal, so the circuit in Fig. 14 is configured as described above. This is equivalent to the circuit shown in FIG. In other words, when using a normal analog signal, the control signal con1
, when the analog signal is small, the control signal con3
When a sudden analog signal occurs, the control signal con2 is set to logic "1" and the control state is changed to Δ
By performing the calculation, granular noise and overload noise can be reduced. By performing such control, it is possible to calculate the appropriate Δ amount according to the state of the analog signal,
It becomes possible to modulate and demodulate analog waveforms faithfully.

As explained above, according to the present invention, in the adaptive delta modulation/demodulation circuit, the calculation control of increasing/decreasing the amount of Δ is executed in accordance with the signal state of the analog signal waveform,
By adopting a circuit configuration that allows the center of the Δ quantity to move, it is possible to provide a Δ quantity calculation circuit that can faithfully modulate and demodulate an analog waveform so as to reduce noise and distortion.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing a conventional delta modulation circuit.
Fig. 2 is a timing chart shown to explain the modulation operation in the circuit of Fig. 1, Fig. 3 is a block diagram showing a conventional delta demodulation circuit, and Fig. 4 is shown to explain the circuit operation of Fig. 3. 5 and 6 are waveform diagrams for explaining the operation of the delta modulation circuit shown in FIG. 1, FIG. 7 is a circuit diagram showing a conventional adaptive delta modulation circuit, and FIG. 9 is a diagram for explaining the calculation characteristics of the circuit shown in FIG. 8. FIG. 10 is a configuration diagram of the Δ amount calculation circuit according to an embodiment of the present invention. 11 is a diagram for explaining the calculation characteristics of the circuit in FIG. 10, FIG. 12 is a block diagram of a Δ amount calculation circuit according to the second embodiment of the present invention, and FIG. 13 is a diagram for explaining the calculation characteristics of the circuit in FIG. 12. Figure 14, which is a diagram for explaining the calculation characteristics, is the third diagram of the present invention.
FIG. 2 is a configuration diagram of a Δ amount calculation circuit according to an embodiment. 8...Δ amount calculation circuit, 9...Δ amount register, 10...
Adder/subtractor, I ₁ , I ₂ , I ₄ ...clocked inverter,
_I3 ...Inverter, _A1 ~ _A12 ...A input terminal, _B1 ~
_B12 ...B input terminal, _C1 to _C12 ...carrying input terminal,
Ca ₁ to Ca ₁₂ ...carry output terminal, _S1 to _S12 ...output terminal, φ1, φ2...clock pulse, EXD...Δ amount increase/decrease instruction signal, con1 to con3...control signal.

Claims (1)

[Claims] 1. In the Δ amount calculation circuit in the adaptive delta modulation/demodulation circuit, the Δ amount calculation circuit of a predetermined bit length that holds the value of the Δ amount
The carrier output terminal of each stage is connected to the carrier input terminal of the next stage, and the carrier input terminal of the least significant bit and the second input terminal of a predetermined upper bit are connected to the carrier input terminal of the next stage. A Δ quantity increase/decrease instruction signal is applied, output data of each stage of the Δ quantity register is guided to the first input terminal of each stage, predetermined data is guided to the second input terminal of a predetermined lower bit stage, and Δ An addition/subtraction circuit that performs quantity calculations outputs the output data of a predetermined upper bit of the Δ quantity register, or the output data of the upper bits that include this bit and exceeds this bit length, and the Δ quantity increase/decrease instruction signal and the Δ quantity of the addition/subtraction circuit. a control signal for setting an arithmetic characteristic of the adder/subtractor, and a control means that selects the addition and subtraction signals of the adder/subtracter and leads them to the second input terminal of the lower bit stage of the adder/subtractor. and a change characteristic of the Δ amount is set in accordance with the input analog signal waveform by changing the arithmetic characteristics of the addition/subtraction circuit by selecting a control signal in the control means. Δ amount calculation circuit. 2. The Δ amount calculation circuit according to claim 1, which is formed into an integrated circuit.