JPS6256671B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a MOS type semiconductor device.

Two-layer polycrystalline silicon structure integrated circuits are manufactured for the purpose of improving the degree of integration in MOS type semiconductor integrated circuits or for the purpose of providing rewritable read-only memories. In this case, the withstand voltage between the insulating film between two polycrystalline silicon layers, the polycrystalline silicon and the metal formed thereon, or the polycrystalline silicon and the substrate formed below it is important in terms of manufacturing yield and equipment reliability. It is also important from a gender perspective. Normally, this dielectric strength voltage is several tens of volts or more, and in special cases it is required to be more than 100 or more volts. On the other hand, the thickness of this insulating film is approximately 1000
Although the thickness is about Å to 1 μm, there are cases where only a thin insulating film is allowed due to other property constraints. The present invention relates to this point.

In the conventional manufacturing method, the first polycrystalline silicon layer is doped with phosphorus as an impurity, and an insulating film is formed on the polycrystalline silicon by thermal oxidation. The film thickness becomes too thick, and after this insulating film is removed by etching, a desired insulating film must be formed again. However, an insulating film formed by thermal oxidation after removing the insulating film until the surface of the first polycrystalline silicon is exposed has a low withstand voltage. It also invades the gate insulating film directly under the polycrystalline silicon.
This also lowers the breakdown voltage between the polycrystalline layer and the substrate.

An object of the present invention is to provide an effective method for manufacturing a semiconductor device that eliminates the drawbacks of the prior art.

The present invention is characterized in that a first polycrystalline silicon layer into which an impurity such as phosphorus is introduced is provided on one main surface side of a semiconductor substrate, and a first insulating film is formed on this first polycrystalline silicon layer. , a method for manufacturing a semiconductor device in which a predetermined region of a first insulating film is etched and a second polycrystalline silicon layer is formed on this region with an insulating film interposed therebetween, in which the first insulating film is etched using a first polycrystalline silicon layer. Either a second polycrystalline silicon layer is formed on the first insulating film without etching until the silicon layer is exposed, that is, a thin first insulating film is left, or a new insulating film is formed on the remaining first insulating film. , and a second polycrystalline silicon layer was formed thereon as a second insulating film.

Next, a manufacturing method will be explained based on the drawings, taking an N-channel two-layer polycrystalline silicon gate MOS as an example of an embodiment of the present invention.

As with a normal N-channel silicon gate MOS integrated circuit, a thin silicon dioxide film 2 is formed on a P-type silicon substrate 1 with the required concentration, and a silicon nitride film 3 is formed on top of it to nitride the parts other than the active region. After removing the silicon film 3 and the silicon dioxide film 2 by a normal photolithography process, a field oxide film 4 is formed by thermal oxidation (FIG. 1). Next, after removing the silicon dioxide film and the silicon nitride film shown in FIG. Remove unnecessary parts using photoetching (Figure 2). After this, this first polycrystalline silicon layer 6
Then, phosphorus is doped as an impurity by thermal diffusion or ion implantation, and an insulating film is formed on this polycrystalline silicon. This insulating film is usually formed by thermal oxidation, but the growth rate of the thermal oxide film on the polycrystalline silicon layer in which phosphorus is diffused is fast, making it difficult to control its thickness. Therefore, for example, when a second polycrystalline silicon layer to be formed for the gate of another transistor is provided on the first polycrystalline silicon layer with an insulating film interposed therebetween, at least the insulation of the overlapping portion of both layers is The film must be removed by a single etching process, and a new insulating film must be formed with a thickness that takes into account the dielectric strength between both layers and other design constraints.

In the prior art, the insulating film in this region was completely removed, that is, etched until the surface of the first polycrystalline silicon layer was exposed. However, if this etching is carried out until the first layer polycrystalline silicon surface is exposed, subsequent thermal oxidation will cause the first layer to become exposed.
An insulating film formed on a polycrystalline silicon layer has a lower breakdown voltage than an insulating film formed without etching until the polycrystalline silicon surface is exposed. Furthermore, if etching is performed until the polycrystalline silicon surface is exposed, the etching solution will generally penetrate along the grain boundaries of the polycrystalline silicon, corroding the gate oxide film 5 directly under the first layer of polycrystalline silicon, and lowering the gate dielectric breakdown voltage. .
In the present invention, in order to avoid these drawbacks, the insulating film formed on the first polycrystalline silicon layer is not removed by etching until the polycrystalline silicon surface is exposed. The components of this insulating film generally have a higher concentration of phosphorus in the upper part of the film than in the lower part, so there is a difference in etching speed with commonly used etching solutions such as hydrofluoric acid and ammonium fluoride. It is easy to leave some of the insulating film behind. The same applies to the case of so-called doped polycrystalline silicon which is doped during the growth of polycrystalline silicon when doping the polycrystalline silicon with phosphorus. Next, N ⁺ in the portion necessary for connecting the second polycrystalline silicon layer 8 and the N ⁺ diffusion region.
After removing the insulating film on the diffusion layer by photolithography, a second layer of polycrystalline silicon 8 is formed, and photolithography is carried out into a required shape (FIG. 3). Therefore, the insulating film 7 shown in FIG. 3 is a film that is formed on the first polycrystalline silicon layer 6 without removing at least a portion of the insulating film. Alternatively, a new insulating film may be grown on the remaining thin film of the initially deposited insulating film. Further, in FIG. 3, all the insulating films 7 have the same thickness, but it is sufficient that such a second insulating film exists at least between both polycrystalline silicon layers. Subsequently, using the second polycrystalline silicon layer 8 as a mask, the insulating film 7 and the first polycrystalline silicon layer 6 are etched away, and after the gate oxide film 5 is etched and removed, the second polycrystalline silicon layer 8 and the source and drain diffusion layers are removed. Phosphorus is diffused to form layers, and an insulating film 9 is formed thereon (FIG. 4). Here, the insulating film and the first polycrystalline silicon layer 6 are etched using the second polycrystalline silicon layer 8 as a mask, but the first polycrystalline silicon layer 6 has already been photo-etched at the time of FIG. In some cases, this may result in

Further, holes for connection to the diffusion layer, the first polycrystalline silicon layer, or the second polycrystalline silicon layer are made by photolithography, and then aluminum wiring 10 is formed by a conventional method (FIG. 5).

Although not mentioned in the middle of the process, an ion implantation process may be used directly under the first layer polycrystalline silicon gate or directly under the second layer polycrystalline silicon gate as necessary.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps. In the figure, 1...P-type silicon substrate, 2
...Silicon dioxide film, 3...Silicon nitride film,
4... Field silicon dioxide film, 5... Gate silicon dioxide film, 6... First polycrystalline silicon layer, 7... Insulating film, 8... Second polycrystalline silicon layer, 9... Insulating film, 10... Aluminum wiring, 11... Phosphorus diffusion layer.

Claims (1)

[Claims] 1. A step of forming a first polycrystalline silicon layer on a semiconductor substrate, a step of introducing an impurity into the first polycrystalline silicon layer, and then performing a thermal oxidation treatment to form a first polycrystalline silicon layer. a step of forming a thermal oxide film on the entire surface of the first polycrystalline silicon layer; A semiconductor characterized by comprising a step of etching the film halfway, and a step of forming the conductive layer on the remaining thermal oxide film or on an insulating film newly grown on the remaining thermal oxide film. Method of manufacturing the device.