JPS5816341B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a one-transistor, one-capacitor dynamic memory element, and particularly relates to a method for manufacturing a dynamic memory element having one transistor and one capacitor, and particularly relates to a method for manufacturing a dynamic memory element having one transistor and one capacitor, and particularly relates to a method for manufacturing a dynamic memory element having one transistor and one capacitor, and particularly relates to a method for manufacturing a dynamic memory element having one transistor and one capacitor. The present invention relates to a method for manufacturing a semiconductor device that improves the characteristics of a memory element having a structure.

Dynamic memory elements with one transistor and one capacitor are suitable for high integration, and are said to become the mainstream of large-capacity memories in the future.

Memory elements with a double polycrystalline silicon structure, in which the first layer of polycrystalline silicon is used for the capacitor electrode and the second layer of polycrystalline silicon for the gate electrode, are being actively developed to further advance high integration. ing.

An example of a conventional method for manufacturing a memory device having a double polycrystalline silicon structure will be described below, followed by a description of a method for manufacturing a memory device having a double polycrystalline silicon structure according to the present invention.

FIGS. 1 to 3 are cross-sectional views for explaining the manufacturing process of a conventional device.

When using an n-channel MO8FET using a Si substrate as a switching transistor, a field oxide film 2 is formed on a p-type silicon substrate 1 by a selective oxidation method using a silicon nitride film, and the silicon surface other than this field oxide film 2 is After forming a silicon oxide film 3 to serve as an interelectrode insulator of a capacitor on the exposed portion, a first layer of polycrystalline silicon film 4 to serve as a capacitor electrode is grown.

In this case, the impurity may be doped during the growth of the polycrystalline silicon film 4 or by a diffusion method after growth.

Next, the polycrystalline silicon film 4 is subjected to etching using plasma gas to form a capacitor electrode.

Subsequently, after exposing the surface of the p-type silicon substrate 10 where a MOSFET is to be formed, a gate oxide film 5 of the MOSFET is formed (FIG. 1).

Next, a second layer of polycrystalline silicon film 6 that will become the gate electrode of the MOSFET is grown, and this is etched to form the gate electrode portion, and then the polycrystalline silicon film 6 and gate oxide film 5 that will become the drain are grown. After removal, phosphorus as an impurity is diffused to form a drain diffusion layer 7 (FIG. 2).

Finally, after forming an overlying oxide film 8, a contact hole is opened in this oxide film 8 and an A1 wiring 9 is formed, thereby obtaining a memory element with one transistor and one capacitor (Fig. 3).
.

In the memory element with the double polycrystalline silicon structure mentioned above, the gate electrode and the capacitor electrode overlap, so the source diffusion region required in the conventional memory element with the single layer polycrystalline silicon structure is unnecessary. High integration becomes possible.

However, a problem with the memory element having the double polycrystalline silicon structure shown in FIG. 3 is the insulation between the overlapping polycrystalline silicones.

Considering the usage conditions, the dielectric strength voltage between the polycrystalline silicon is required to be 60 V or more.

The insulating film between the first and second polycrystalline silicon films 4 and 6 is formed by forming the gate oxide film 5 of the switching transistor as shown in the manufacturing method of FIGS. 1 to 3. It is formed on the polycrystalline silicon film 4.

In order to increase the speed of a switching transistor, it is necessary to shorten the gate length of the switching transistor, but when the gate length is shortened, a so-called short channel effect occurs in which the threshold voltage VTH of the MOSFET rapidly decreases.

As one of the effective means for preventing this, a method of thinning the gate oxide film 5 is commonly used.

For example, it is said that for a transistor of L-1 μm, the thickness of the gate oxide film 5 should be approximately 250λ.

In this way, the gate oxide film 5 of the switching transistor
The thickness of the film is small at °C, and the dielectric strength voltage is also very low, making it difficult to obtain the desired value.

In addition, since the gate oxide film 5 is thin and consists of one layer, pinholes are likely to occur.
The second layer polycrystalline silicon films 4 and 6 are short-circuited, causing a fatal defect.

This invention was made to improve the drawbacks of such conventional memory elements having a double polycrystalline silicon structure, and improves the dielectric strength between the first layer and the second layer of polycrystalline silicon and eliminates pinholes. The purpose is to reduce the number of

This invention will be explained in detail below.

4 to 11 are cross-sectional views showing the manufacturing process of an embodiment of the present invention. First, a field oxide film 2 having a thickness of 0.degree. C. is formed on a p-type silicon substrate 1 by selective oxidation (FIG. 4).

After forming a silicon oxide film 3 to serve as an interelectrode insulator in the capacitor part of the memory element on the exposed silicon surface other than the field oxide film 2 at a temperature of Form.

In this case, the impurity may be doped during the growth of the polycrystalline silicon or by a diffusion method after the growth (FIG. 5).

Thereafter, a silicon nitride film 10 is formed on the first layer polycrystalline silicon film 4 by a CVD method or the like (FIG. 6).

If the thickness of the silicon nitride film 10 is 1000λ or more, the dielectric strength between the first layer and the second layer of polycrystalline silicon films is sufficiently guaranteed.

Thereafter, the silicon nitride film 10 and the first layer polycrystalline silicon film 4 are etched in a plasma gas such as CF4 using the resist 11 as a mask (FIG. 7).

After removing the resist 11, the silicon oxide film 3 is removed to expose the surface of the p-type silicon substrate 10 where a switching transistor is to be formed (FIG. 8).

Next, a gate oxide film 5 of the MOSFET is formed.

In this case, the surface of the silicon nitride film 10 on the first layer polycrystalline silicon film 4 is also oxidized to form a thin oxide film.

Therefore, even if there are pinholes in the silicon nitride film 10, the number of pinholes is reduced due to the presence of the thin oxide film on the silicon nitride film (FIG. 9).

Thereafter, a second layer of polycrystalline silicon film 6 is grown, and this polycrystalline silicon film 6 is further etched to form a gate electrode portion, and then a gate oxide film 5 is formed on the portion that will become the drain and a second layer of polycrystalline silicon film 6 is grown. After removing the silicon film 6,
Drain diffusion layer 7 is formed by diffusing impurity phosphorus (FIG. 10).

Finally, a contact hole is opened in the overlying oxide film 8, and A
By providing the I wiring 9, a memory element having one transistor and one capacitor can be obtained (FIG. 11).

As explained above, in the present invention, a silicon nitride film having a thickness of 1000 Å or more is formed between the first layer polycrystalline silicon film and the second layer polycrystalline silicon film. A predetermined dielectric strength voltage of the polycrystalline silicon film of the first layer and the second layer can be obtained regardless of the dielectric strength.

Further, since the silicon nitride film is oxidized to form an insulating film, there are two layers of the silicon nitride film and the oxide film, which has the advantage of reducing the number of pinholes.

[Brief explanation of the drawing]

FIGS. 1 to 3 are cross-sectional views for explaining a method of manufacturing a memory element having a conventional double polycrystalline silicon structure, and FIGS. 4 to 11 are cross-sectional views having a double polycrystalline silicon structure according to the present invention. FIG. 3 is a cross-sectional view for explaining the manufacturing process of a memory element. In the figure, 1 is a D-type silicon substrate, 2 is a field oxide film,
3 is a silicon oxide film, 4 is a first layer polycrystalline silicon film,
5 is a gate oxide film, 6 is a second layer polycrystalline silicon film, and 7 is a gate oxide film.
is a drain diffusion layer, 8 is an overlying oxide film, 9 is an AI wiring,
10 is a silicon nitride film, and 11 is a resist. Note that the same reference numerals in the figures indicate the same or similar parts.

Claims (1)

[Claims] A method for manufacturing a semiconductor device having 11 transistors and 1 capacitor, which includes the steps of: forming an insulating film such as a silicon oxide film on a silicon substrate having a thick field oxide film; and forming an insulating film such as a silicon oxide film on the silicon oxide film. a step of forming a first layer polycrystalline silicon film including the first layer polycrystalline silicon film; a step of forming a silicon nitride film on the first layer polycrystalline silicon film; and a step of forming a silicon nitride film and the first layer polycrystalline silicon film. 1. A method of manufacturing a semiconductor device, comprising the step of etching by a photolithography process, and then forming a second layer of polycrystalline silicon film to become a gate oxide film and a gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon nitride film formed on the first layer polycrystalline silicon film has a thickness of 1000 Å or more.