JPS6257101B2 - - Google Patents
Info
- Publication number
- JPS6257101B2 JPS6257101B2 JP55061768A JP6176880A JPS6257101B2 JP S6257101 B2 JPS6257101 B2 JP S6257101B2 JP 55061768 A JP55061768 A JP 55061768A JP 6176880 A JP6176880 A JP 6176880A JP S6257101 B2 JPS6257101 B2 JP S6257101B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- bump
- bump electrode
- insulating film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子、特にバンプ電極の周辺部
が絶縁膜を介してバンプ電極とは電位が異なる配
線上に臨む構造の半導体素子（素子）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a structure in which a peripheral portion of a bump electrode faces a wiring having a different potential from that of the bump electrode via an insulating film.
温度補償型ツエナーダイオードの素子として
は、たとえば第１図に示すような構造が考えられ
る。この素子はダブルヒートシンクダイオード
（DHD）型のガラス封止構造用の素子であつて、
Ｎ型のサブストレート１の表層部にN+型のエミ
ツタ領域２を一部に有するＰ型のベース領域３や
Ｐ型の抵抗領域４を有している。また、サブスト
レート１の表層部は全域に亘つて絶縁膜５（たと
えば、SiO2膜、ナイトライド膜、りんガラス
膜、樹脂膜等）で被われている。また、エミツタ
領域２、ベース領域３、抵抗領域４を被う絶縁膜
５部分には孔が開けられ、この孔部分には配線層
６が形成される。この配線層６は耐熱性金属であ
るパラジウムおよびチタンを層状に重ねて形成し
てチタンが直接各導電型領域に接触するように構
成されるとともに、絶縁膜５上を所望方向に延び
ている。ここでは、配線層６は抵抗領域４とベー
ス領域３を結ぶバンプ用配線層７と、エミツタ領
域２から延びる連結用配線層８とが示されてい
る。また、前記バンプ用配線層７の一部以外の配
線層６および絶縁膜５はさらに他の絶縁保護膜９
（材質的には前記の絶縁膜５と同じである。以下
単に絶縁膜とも呼ぶ。）で被われる。また、露出
するバンプ用配線層７部分には50μｍ程度の厚い
銀からなる半球状に盛り上がつたバンプ電極１０
が形成される。さらに、サブストレート１の下面
にはアンチモン（Sb）を含む金層１１が形成さ
れるとともに、この金層１１上には銀層からなる
電極１２が形成されている。 As a temperature-compensated Zener diode element, for example, a structure as shown in FIG. 1 can be considered. This element is a double heat sink diode (DHD) type element for glass-sealed structure.
A P type base region 3 having a part of an N + type emitter region 2 and a P type resistance region 4 are provided on the surface layer of an N type substrate 1 . Further, the entire surface layer of the substrate 1 is covered with an insulating film 5 (eg, SiO 2 film, nitride film, phosphor glass film, resin film, etc.). Further, a hole is formed in a portion of the insulating film 5 covering the emitter region 2, base region 3, and resistance region 4, and a wiring layer 6 is formed in this hole portion. The wiring layer 6 is formed by layering palladium and titanium, which are heat-resistant metals, so that the titanium directly contacts each conductivity type region, and extends on the insulating film 5 in a desired direction. Here, the wiring layer 6 includes a bump wiring layer 7 connecting the resistance region 4 and the base region 3, and a connecting wiring layer 8 extending from the emitter region 2. Further, the wiring layer 6 and the insulating film 5 other than a part of the bump wiring layer 7 are further covered with another insulating protective film 9.
(The material is the same as the above-mentioned insulating film 5. Hereinafter, it is also simply referred to as an insulating film.). In addition, on the exposed part of the bump wiring layer 7, a hemispherical bump electrode 10 made of silver with a thickness of about 50 μm is formed.
is formed. Furthermore, a gold layer 11 containing antimony (Sb) is formed on the lower surface of the substrate 1, and an electrode 12 made of a silver layer is formed on this gold layer 11.
このような半導体素子１６は第２図に示すよう
に、１対のリード１３の端面間に挾むとともに、
外周をガラス管１４で取り囲まれるようにして封
止され、DHD型の半導体装置１５となる。 As shown in FIG. 2, such a semiconductor element 16 is sandwiched between the end faces of a pair of leads 13, and
The outer periphery is surrounded by a glass tube 14 and sealed, forming a DHD type semiconductor device 15.
ところで、前記封止は650℃前後と高い温度下
で行なうため、金属であるバンプ電極１０および
配線層６と半導体であるシリコンからなるサブス
トレート１との間で熱応力が発生して絶縁保護膜
９にクラツクが発生し易くなる。この結果、バン
プ電極１０の一部周辺がバンプ用配線層７とは使
用時電位が異なる連結用配線層８上に臨む構造も
あつて、この間の絶縁保護膜９の領域にクラツク
が発生すると、使用時このクラツク部分でシヨー
トしてしまう。また、一般に絶縁保護膜９は厚く
しすぎると、下部のサブストレート等との熱膨張
率の差によつてクラツクが発生し易くなるため、
1.5μｍ前後止りとなる。このように絶縁保護膜
９が薄いと絶縁膜製造時ピンホールが発生し易く
なり、シヨートの原因ともなる。 By the way, since the above-mentioned sealing is performed at a high temperature of around 650° C., thermal stress is generated between the bump electrodes 10 and wiring layer 6 made of metal and the substrate 1 made of silicon, which is a semiconductor, causing the insulation protective film to deteriorate. 9, cracks are more likely to occur. As a result, there is a structure in which a part of the periphery of the bump electrode 10 faces the connection wiring layer 8 whose potential during use is different from that of the bump wiring layer 7, and if a crack occurs in the area of the insulating protective film 9 between this, When I use it, I end up shooting at this crack part. Additionally, in general, if the insulating protective film 9 is made too thick, cracks are likely to occur due to the difference in thermal expansion coefficient with the underlying substrate, etc.
It stops at around 1.5μm. If the insulating protective film 9 is thin as described above, pinholes are likely to occur during the manufacturing of the insulating film, which may cause shoots.
したがつて、本発明の目的はバンプ電極と配線
層とのシヨートを防止できる半導体素子を提供す
ることにある。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device that can prevent shortening between bump electrodes and wiring layers.
このような目的を達成するための、本発明の要
旨は次のとおりである。すなわち、半導体基板上
に設けられた第１の配線層と第２の配線層と、前
記第１の配線層の一部に電気的に接続されたバン
プ電極と、前記第２の配線層上に設けられた無機
絶縁膜とを有し、前記第２の配線層の電位は、前
記第１の配線層の電位とは異なるものであり、前
記バンブ電極の周縁部は前記絶縁膜を介して前記
第２の配線層を臨むように形成されている半導体
素子において、
前記バンプ電極の周縁部と前記第２の配線層を
覆う前記無機絶縁膜との間には空隙が設けられて
いることを特徴とする半導体素子を要旨とする。
以下、実施例により本発明を説明する。 The gist of the present invention to achieve such objects is as follows. That is, a first wiring layer and a second wiring layer provided on a semiconductor substrate, a bump electrode electrically connected to a part of the first wiring layer, and a bump electrode electrically connected to a part of the first wiring layer, and a bump electrode electrically connected to a part of the first wiring layer. an inorganic insulating film provided thereon, the potential of the second wiring layer is different from the potential of the first wiring layer, and the peripheral edge of the bump electrode is connected to the insulating layer through the insulating film. In the semiconductor element formed so as to face the second wiring layer, a gap is provided between the peripheral edge of the bump electrode and the inorganic insulating film covering the second wiring layer. The gist is a semiconductor device that has the following characteristics.
The present invention will be explained below with reference to Examples.
第３図は本発明の一実施例による半導体素子を
示す断面図である。この実施例は第１図に示す素
子と同様に温度補償型のツエナーダイオード素子
であり、バンプ電極の形状以外は全く同一である
ことから、重複部分の説明は省略する。なお各部
の名称、符号はそのまま用いる。この半導体素子
１６にあつてはバンプ電極１０の周辺部は絶縁保
護膜９から離れて浮き上がり、絶縁保護膜９とバ
ンプ電極１０の周辺下面との間には20μｍ程度の
空隙１７が設けられる。この空隙１７は少なくと
も連結用配線層８上には必ず設けられている。 FIG. 3 is a sectional view showing a semiconductor device according to an embodiment of the present invention. This embodiment is a temperature-compensated Zener diode element similar to the element shown in FIG. 1, and is completely the same except for the shape of the bump electrode, so a description of the overlapping parts will be omitted. The names and symbols of each part will be used as they are. In this semiconductor element 16, the periphery of the bump electrode 10 is lifted apart from the insulating protective film 9, and a gap 17 of about 20 μm is provided between the insulating protective film 9 and the lower surface of the periphery of the bump electrode 10. This gap 17 is always provided at least on the connection wiring layer 8.
ここで、簡単にこの半導体素子の製造方法につ
いて、第４図ａ〜ｆを用いて説明する。同図ａで
示すように、エミツタ領域２、ベース領域３、抵
抗領域４等を有するサブストレート１を用意す
る。このサブストレート１の表面（上面）は部分
的に絶縁膜５で被われ、かつエミツタ領域２に繋
がる連結用配線層８、さらにはベース領域３と抵
抗領域４を結ぶバンプ用配線層７が設けられる。
また、サブストレート１の下面にはアンチモンを
含む金層１１が被着されている。 Here, a method for manufacturing this semiconductor element will be briefly explained using FIGS. 4a to 4f. As shown in FIG. 1A, a substrate 1 having an emitter region 2, a base region 3, a resistance region 4, etc. is prepared. The surface (upper surface) of this substrate 1 is partially covered with an insulating film 5, and is provided with a connecting wiring layer 8 that connects to the emitter region 2, and further a bump wiring layer 7 that connects the base region 3 and the resistance region 4. It will be done.
Further, a gold layer 11 containing antimony is deposited on the lower surface of the substrate 1.
そこで、同図ｂに示すように、サブストレート
１の上面全域をCVDSiO2膜等の絶縁体からなる
絶縁保護膜９で被う。この場合、絶縁保護膜９は
1.5μｍ程度の厚さとする。また、バンプ電極を
形成するために、ホトエツチング技術によつてバ
ンブ用配線層７上の絶縁保護膜９に孔１８を開け
る。この孔１８は連結用配線層８上に達すること
なく、バンプ用配線層７上にのみ位置する。 Therefore, as shown in FIG. 1B, the entire upper surface of the substrate 1 is covered with an insulating protective film 9 made of an insulator such as a CVDSiO 2 film. In this case, the insulating protective film 9
The thickness should be approximately 1.5 μm. Further, in order to form bump electrodes, holes 18 are made in the insulating protective film 9 on the bump wiring layer 7 by photo-etching technology. This hole 18 does not reach above the connection wiring layer 8, but is located only on the bump wiring layer 7.
つぎに、同図ｃで示すように、露出したバンプ
用配線層７上にめつきによつてたとえば20μｍ厚
さにバンプ状銀層１９を形成する。また、サブス
トレート１の下面にも銀層１２を被着する。 Next, as shown in FIG. 3c, a bump-shaped silver layer 19 is formed on the exposed bump wiring layer 7 by plating to a thickness of, for example, 20 μm. A silver layer 12 is also deposited on the lower surface of the substrate 1.
つぎに、同図ｄに示すように、サブストレート
１の上面にバンプ状銀層１９の高さにまでワツク
ス２０を塗布する。この結果、バンプ状銀層１９
の上面は露出する。なお、ワツクスに代えてホト
レジストで被つてもよい。 Next, as shown in FIG. 4D, wax 20 is applied to the upper surface of the substrate 1 up to the height of the bump-shaped silver layer 19. As a result, the bump-shaped silver layer 19
The top surface of is exposed. Note that it may be covered with photoresist instead of wax.
つぎに、同図ｅで示すように、再びめつき処理
を行なつてバンプ状銀層１９上に30μｍ程度の厚
さに銀層を成長させて茸形のバンプ電極１０を形
成し、同図ｆで示すように、ワツクス２０を除去
して所望の半導体素子１６を製造する。 Next, as shown in figure e, a plating process is performed again to grow a silver layer to a thickness of about 30 μm on the bump-shaped silver layer 19 to form a mushroom-shaped bump electrode 10. As shown at f, the wax 20 is removed to produce the desired semiconductor device 16.
このような半導体素子を用いてガラス封止を行
なうと、第５図に示すように、バンプ電極１０の
周辺部２１は熱によつてわずかに垂れ下がるが、
周辺部２１は絶縁保護膜９には接触しない。この
ため、ガラス封止時の温度によつて絶縁保護膜９
にクラツクが発生しても、バンプ電極１０の周辺
部２１とバンプ電極１０と電位が異なる連結用配
線層とは空隙１７がアイソレーシヨンとして働く
ため、シヨートは生じない。また、絶縁保護膜に
ピンホールがあつても同様な効果を得ることがで
きる。したがつて、大電流印加による破懐強度は
向上する。 When glass sealing is performed using such a semiconductor element, as shown in FIG. 5, the peripheral portion 21 of the bump electrode 10 sags slightly due to heat; however, as shown in FIG.
The peripheral portion 21 does not contact the insulating protective film 9. Therefore, depending on the temperature during glass sealing, the insulating protective film 9
Even if a crack occurs in the bump electrode 10, the gap 17 acts as an isolation between the peripheral portion 21 of the bump electrode 10 and the connection wiring layer which has a different potential from that of the bump electrode 10, so that no shot occurs. Furthermore, the same effect can be obtained even if there is a pinhole in the insulating protective film. Therefore, the breaking strength due to the application of a large current is improved.
本発明によれば、バンブ電極と配線層との間に
挿入される表面保護膜（層間絶縁膜）が、樹脂膜
に比較してクラツクが発生しやすいSiO2等の無
機絶縁膜を使用してもシヨートを防止することが
できる。 According to the present invention, the surface protective film (interlayer insulating film) inserted between the bump electrode and the wiring layer uses an inorganic insulating film such as SiO 2 , which is more prone to cracks than a resin film. can also prevent shoots.
なお、本発明は前記実施例に限定されない。す
なわち、ガラス封止構造以外の組立構造の半導体
装置にも適用できる。すなわち、この半導体素子
はフエースダウンボンデイングにも適用できる。 Note that the present invention is not limited to the above embodiments. That is, the present invention can also be applied to semiconductor devices having assembled structures other than glass-sealed structures. That is, this semiconductor element can also be applied to face-down bonding.
以上のように、本発明の半導体素子は大電流印
加による破壊強度が向上する。 As described above, the semiconductor element of the present invention has improved breakdown strength when a large current is applied.
第１図は従来の半導体素子の断面図、第２図は
同じくガラス封止型構造の半導体装置の一部を示
す断面図、第３図は本発明の一実施例による半導
体素子の断面図、第４図ａ〜ｆは同じく半導体素
子の各製造段階における断面図、第５図は同じく
ガラス封止状態での半導体素子の断面図である。
１……サブストレート、２……エミツタ領域、
３……ベース領域、４……抵抗領域、５……絶縁
膜、６……配線層、７……バンプ用配線層、８…
…連結用配線層、９……絶縁保護膜、１０……バ
ンプ電極、１１……金層、１２……電極、１３…
…リード、１４……ガラス管、１５……半導体装
置、１６……半導体素子、１７……空隙、１８…
…孔、１９……バンプ状銀層、２０……ワツク
ス、２１……周辺部。
FIG. 1 is a sectional view of a conventional semiconductor element, FIG. 2 is a sectional view showing a part of a semiconductor device similarly having a glass-sealed structure, and FIG. 3 is a sectional view of a semiconductor element according to an embodiment of the present invention. 4a to 4f are cross-sectional views of the semiconductor element at each manufacturing stage, and FIG. 5 is a cross-sectional view of the semiconductor element in a glass-sealed state. 1...substrate, 2...emitter area,
3...Base region, 4...Resistance region, 5...Insulating film, 6...Wiring layer, 7...Bump wiring layer, 8...
... Connection wiring layer, 9 ... Insulating protective film, 10 ... Bump electrode, 11 ... Gold layer, 12 ... Electrode, 13 ...
...Lead, 14...Glass tube, 15...Semiconductor device, 16...Semiconductor element, 17...Gap, 18...
...hole, 19...bump-shaped silver layer, 20...wax, 21...periphery.
Claims (1)
２の配線層と、前記第１の配線層の一部に電気的
に接続されたバンプ電極と、前記第２の配線層上
に設けられた無機絶縁膜とを有し、前記第２の配
線層の電位は、前記第１の配線層の電位とは異な
るものであり、前記バンプ電極の周縁部は前記絶
縁膜を介して前記第２の配線層を臨むように形成
されている半導体素子において、 前記バンプ電極の周縁部と前記第２の配線層を
覆う前記無機絶縁膜との間には空隙が設けられて
いることを特徴とする半導体素子。[Scope of Claims] 1. A first wiring layer and a second wiring layer provided on a semiconductor substrate, a bump electrode electrically connected to a part of the first wiring layer, and a bump electrode electrically connected to a part of the first wiring layer, and a first wiring layer and a second wiring layer provided on a semiconductor substrate. an inorganic insulating film provided on the wiring layer, the potential of the second wiring layer is different from the potential of the first wiring layer, and the peripheral edge of the bump electrode is In the semiconductor element formed so as to face the second wiring layer through a film, a gap is provided between the peripheral edge of the bump electrode and the inorganic insulating film covering the second wiring layer. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6176880A JPS56158456A (en) | 1980-05-12 | 1980-05-12 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6176880A JPS56158456A (en) | 1980-05-12 | 1980-05-12 | Semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56158456A JPS56158456A (en) | 1981-12-07 |
| JPS6257101B2 true JPS6257101B2 (en) | 1987-11-30 |
Family
ID=13180615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6176880A Granted JPS56158456A (en) | 1980-05-12 | 1980-05-12 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56158456A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54128669A (en) * | 1978-03-29 | 1979-10-05 | Nippon Denso Co Ltd | Flip chip element |
-
1980
- 1980-05-12 JP JP6176880A patent/JPS56158456A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56158456A (en) | 1981-12-07 |
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