JPS6257126B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a white noise generation circuit that generates white noise using the liquid crystal display device in an electronic device having a liquid crystal display device.

In recent years, liquid crystal display devices, which are display devices with low power consumption, have become widely used in electronic devices such as small electronic calculators. Furthermore, electronic devices equipped with a musical tone generation function, such as small electronic calculators that generate musical tones corresponding to the operation keys when a key is operated, are becoming widespread.

By the way, when generating white noise to generate a percussion instrument sound, for example, a cymbal sound, in an electronic device equipped with a conventional musical sound generation function, the first
A white noise generation circuit as shown in the figure is used. For convenience of explanation, it is assumed that the flip-flops are connected in five stages, but the same principle applies even when registers with a larger number of bits are used. That is, as shown in FIG. 1, five stages of D-type flip-flops 1 to 5 connected in series, the Q output signal of the fourth stage flip-flop 4, and the output signal of the fifth stage flip-flop 5 are input. It consists of an exclusive OR gate 6 which outputs a white noise signal W and inputs the white noise signal W to the flip-flop 1 at the first stage. Second
The figure shows the output signals of each flip-flop 1 to 5 and the output waveform of a white noise signal, which are repeatedly output at a period T (21 bit times). Note that when using a multi-stage register, T becomes very large and can be used as white noise.

However, if a white noise generating circuit as shown in FIG. 1 is specially provided in an electronic device, there is a drawback that the circuit configuration becomes complicated.

The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a first electrode drive circuit provided on the input side of the first electrode drive circuit of the liquid crystal display device in an electronic device having a liquid crystal display device. To provide a white noise generation circuit for an electronic device having a liquid crystal display device, which can generate white noise using a shift register, thereby simplifying the circuit configuration of the entire device. .

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. FIG. 3 shows a circuit configuration of a small electronic calculator having a liquid crystal display device and a musical tone generating function. In the figure, numeral 10 is a keyboard, which includes normal numeric keys used for calculators,
It is equipped with various function keys, a power switch, a mode changeover switch, etc. The mode changeover switch has two switching positions: calculation mode and musical sound generation mode, and when the mode changeover switch is set to calculation mode, the small electronic calculator can perform normal calculations; ,
When switched to the musical tone generation mode, musical tones can be generated. In this case, each key provided on the keyboard 10 is capable of specifying a musical tone or rhythm tone of a predetermined pitch, respectively.
Therefore, when the musical tone generation mode is set, musical tones are generated from a sounding body, which will be described later, by operating a desired key.

On the other hand, the keyboard 10 undergoes key sampling periodically under the control of a ROM (read-only memory) 11 to detect the on/off state of each key.
Also, the key data obtained as a result is the bus line
It is applied to the ROM 11 via _B1 .

The ROM 11 stores microprograms that control various operations of this small electronic calculator, and
According to this microprogram, various microinstructions such as address data AD, numerical code data CODE, and instruction data INS are outputted in parallel to bus lines B ₂ , B ₃ , and B ₄ . Then, the above address data AD, numerical code data
The CODE is input to the calculation storage section 12 when the calculation mode is set, and is input to the musical tone memory 13 and the rhythm generation section 30 when the melody tone generation mode is set. Also, instruction data
INS is input to the instruction decoder 14.

The arithmetic storage section 12 consists of an adder circuit, a RAM (random access memory), etc., and when a key on the keyboard 10 is operated while the mode changeover switch is setting the calculation mode, the above key data output from the keyboard 10 is stored. However, ROM1
Address data AD and numerical code data CODE outputted from 1 are input to the calculation storage section 12, and a predetermined calculation is executed. Further, the calculation result data of the calculation storage section 12 is stored in the RAM, but the display data to be displayed among the calculation result data is sent to the decoder 1 via the bus line _B5 .
Sent to 5. In this case, the decoder 15 converts the input display data into data (serial data) that can be displayed on a liquid crystal display device (not shown), and sends it to the first bit of the shift register 17 via the selection circuit 16.

The musical tone memory 13 permanently stores frequency information indicating the pitch of a musical tone corresponding to a key on the keyboard 10, and when a key on the keyboard 10 is operated while the mode changeover switch is set to the musical tone generation mode. Then, the address data from ROM11
AD is given and addressed. As a result, the musical tone frequency information at the address is input to the melody generating section 19 in the musical tone generating section 18 via the bus line B6. And melody generation part 1
9, a basic clock given from a clock pulse generation circuit 31, which will be described later, is divided at a predetermined frequency division ratio.
By dividing the frequency, a melody sound is generated and sent to the sounding body 20 to make it sound.

The instruction decoder 14 decodes the instruction signal INS and outputs clock pulses φA, φB, φC and a switching signal S, respectively. The clock pulse φA is supplied to the shift register 1.
Furthermore, the clock pulse φB is used as a read clock for a display buffer register 21, which will be described later, and the clock pulse φc is inputted to the second electrode drive signal 22 to be used as the second electrode drive signal X, Used to create Y and Z. On the other hand, the switching signal S is outputted as a binary logic level "0" signal when the mode switching switch is set to the calculation mode, and is outputted as a "1" signal when the musical tone generation mode is set. It's a signal. Therefore, the switching signal S is sent to the selection circuit 16.
The signal is input to the first input terminal of the AND gate 23 through the inverter 24, and is directly input to the first input terminal of the AND gate 25. In addition, the output data of the decoder 15 is input to the second input terminal of the AND gate 23, while the white noise signal W output from the exclusive OR gate 26, which will be described later, is input to the second input terminal of the AND gate 25.
is entered. And the output of AND gate 23 or AND gate 25 is outputted by OR gate 27.
The signal is inputted to the first bit of the shift register 17 via the clock pulse φA, and then shifted within the shift register 17 by being driven by the clock pulse φA. The capacity of this shift register 17 is 24 bits,
Furthermore, while the mode changeover switch is set to the calculation mode, the display data (24-bit serial data; 8 digits) output from the decoder 15 is all passed through the AND gate 23 and OR gate 27 of the selection circuit 16. When the input to the shift register 17 is completed, the clock pulse φB is output, and the data in the shift register 17 is simultaneously transferred to the display buffer register 2 as parallel data.
1. Buffer register 2 for this display
The data read into 1 is sent to the first electrode drive circuit 28 and first electrode drive signals a ₁ , b ₁ , c ₁ , . . .
It is converted into a ₈ , b ₈ , and c ₈ and sent to the first electrode panel of the liquid crystal display device. On the other hand, the second electrode panel has a second electrode output from the second electrode drive circuit 22 described above.
Electrode drive signals X, Y, Z are sent, thereby
Eight digits of data are displayed on the liquid crystal display section of the liquid crystal display device. This liquid crystal display device uses a 1/3 bias-1/3 duty drive system,
It has an 8-digit liquid crystal display.

On the other hand, while the mode changeover switch is set to the musical sound generation mode, the AND gate 23 is closed and the AND gate 25 is opened, so that the selection circuit 16 selectively outputs the white noise signal W. . This white noise signal W
is the output of the 23rd bit of shift register 17,
This is a signal obtained by the output of the exclusive OR gate 26 whose input signal is the 24th bit output and the signal passed through the inverter 29. Note that an exclusive NOR gate may be used instead of the exclusive OR gate 26. Then, the white noise signal W output from the exclusive OR gate 26 is sent to the selection circuit 16,
It is circulated by the shift register 17 and the exclusive OR gate 26 during the setting of the white noise generation mode, and the rhythm generation section 3 in the musical tone generation section 18
Sent to 0. At this time, the rhythm generating section 30 has
Code data CODE is given from ROM11,
By controlling the output of the exclusive OR gate 26, that is, the white noise signal W, a predetermined rhythmic sound is generated and the sounding body 20 is made to sound.

The clock pulse generating circuit 31 has a built-in reference oscillator, and is a circuit that generates various clock pulses for driving each circuit in FIG.

Next, the operation of the above embodiment will be explained. First, when the mode changeover switch is set to the calculation mode, the instruction decoder 14 outputs the changeover signal S of "0" signal, and the selection circuit 1
Sent to 6. Therefore, the AND gate 23 in the selection circuit 16 is opened, and the AND gate 25 is opened.
is closed. Therefore, the selection circuit 16 selectively outputs the display data that is the output of the decoder 15, but does not select the white noise signal W that is the output of the exclusive OR gate 26. When a calculation is executed and a key on the keyboard 10 is operated, the key data is transferred to the ROM1 via the bus line B1.
Sent to 1. Further, the ROM 11 outputs address data AD and numerical code data CODE according to the key data and sends them to the calculation storage section 12.
For this reason, a predetermined calculation is executed in the calculation storage section 12. Further, among the calculation results in the calculation storage section 12, display data to be sent to the liquid crystal display device for display is sent to the decoder 15 via the bus line B5 and converted into 24-bit serial data.
Furthermore, this 24-bit serial data is input to the first bit of the shift register 17 via the AND gate 23 and OR gate 27 in the selection circuit 16, and is then driven by the clock pulse φA and sequentially shifted within the shift register 17. . When all of the 24-bit serial data has been input into the shift register 17, a clock pulse φB is output, and the serial data is simultaneously read into the display buffer register 21 as 24-bit parallel data. Therefore, the first electrode drive circuit 28 outputs first electrode drive signals a ₁ to c ₈ having contents corresponding to the contents of the display data, and sends them to the first electrode panel of the liquid crystal display device. On the other hand, the clock pulse φc causes the second electrode drive circuit 22 to
The second electrode drive signals X, Y, and Z output from the second electrode panel are sent to the second electrode panel, so that the 8-digit display data is displayed on the liquid crystal display section of the liquid crystal display device with a 1/3 bias. Displayed by 1/3 duty drive system.

On the other hand, when the mode changeover switch is set to the musical tone generation mode, address data AD and numerical code data CODE outputted from the ROM 11 based on the key data outputted from the keyboard 10 are sent to the musical tone memory 13 and the rhythm generation section 30.
As a result, in the case of a melody tone, the frequency information is specified and read out from the musical tone memory 13 by the address data AD. The information is then given to the melody generating section 19 in the musical tone generating section 18, which divides the frequency of the basic clock from the clock pulse generating circuit 31 to generate a musical tone signal, which is then sounded by the sounding body 20. .

When the musical tone generation mode is set, the instruction decoder 14 outputs a switching signal S of "1" signal, which closes the AND gate 23 in the selection circuit 16 and opens the AND gate 25. be done. As a result, the white noise signal W output from the exclusive OR gate 26 is cyclically held by the selection circuit 16 and the shift register 17.

For example, the rhythm generating section 3 from the ROM 11
When the rhythm of cymbal sounds shown in FIG. body 20
give to As a result, the sounding body 20 produces cymbal sounds in a rhythm as shown in FIG.

In the above embodiment, the capacity of the shift register 17 used in the liquid crystal display device was set to 24 bits (eight digits), but of course, this capacity is arbitrary. Also, the 23rd bit time of the shift register 17
Exclusive OR gate 2 for each output at the 24th bit time
6 to create the white noise signal W, but of course, the white noise signal W is generated by the signal taken out from any bit of the shift register 17.
may be created. Furthermore, the driving method of the liquid crystal display device is not limited to the above embodiment, for example, 1/2 bias -
A 1/2 duty drive method or the like may be used.

Furthermore, in the above embodiment, the keyboard 10
To generate musical sounds in response to key operations, we programmed the music in advance, and then
The white noise W can be read out and played, and the white noise W can also be used in combination with musical tone signals of each pitch, and can also be used as various sound effects.

In addition, in the above embodiments, the case where the present invention is applied to a small electronic calculator has been described, but the present invention is of course applicable to various electronic devices such as an electronic watch having a liquid crystal display device. , and various other changes can be made without departing from the gist of the present invention.

As explained above, the present invention generates white noise by using a shift register provided on the input side of the first electrode drive circuit of the liquid crystal display device in an electronic device having a liquid crystal display device. Since we have provided a white noise generation circuit for electronic equipment having a liquid crystal display device, the shift register originally provided in the liquid crystal display device can also be used for white noise generation, and therefore a special White noise can be generated without adding any circuitry, which has the advantage of simplifying the overall circuitry of the device and making it possible to generate white noise.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram of a conventional white noise generation circuit, Figure 2 is an output waveform diagram of the circuit in Figure 1, and Figure 3 is a circuit configuration diagram of an embodiment in which the present invention is applied to a small electronic calculator. , FIG. 4 is a diagram showing an example of the operation of the same example. 10...Keyboard, 11...ROM, 12...
... Arithmetic storage section, 13 ... Musical tone memory, 14 ... Instruction decoder, 15 ... Decoder,
16...Selection circuit, 17...Shift register, 1
8...Musical tone generating section, 19...Melody generating section, 2
0...pronunciation body, 26...exclusive or gate, 28
...first electrode drive circuit, 30...rhythm generation section.

Claims (1)

[Claims] 1. In an electronic device having a liquid crystal display device, an exclusive OR is performed by inputting two or more predetermined bit data of the shift register provided on the input side of the first electrode drive circuit of the liquid crystal display device. a gate circuit that performs addition or exclusive NOR addition; a selection circuit that inputs the output signal of the gate circuit and the display data signal, selects and outputs one of the signals, and inputs the signal to the shift register;
In this mode, the display data signal is input to the shift register via the selection circuit, and the display data signal input to the shift register is sent to the first electrode drive circuit, and the second
A liquid crystal display comprising control means for circulating the output signal of the gate circuit through the selection circuit and the shift register in the mode, and for outputting the output signal of the gate circuit as a white noise signal. A white noise generation circuit in electronic equipment having a display device.