JPS6257213B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a circuit for synchronously rectifying an unbalance signal in a dynamic balance tester. Generally, in a dynamic balance tester, the unbalance is determined from an AC unbalance detection signal synchronized with the test rotation speed.
A synchronous rectifier circuit is used to extract the DC signal corresponding to the 90° force component. In conventional circuits of this type, even harmonics are removed from the noise contained in the unbalanced signal, but there is a drawback that odd harmonics are mixed in at a rate that is the reciprocal of the order. Therefore, in order to remove the odd harmonics, a filter is installed in front of the rectifier circuit, and the cutoff frequency of this filter is also the input fundamental frequency (rotational frequency of the testing machine).
The disadvantage was that it required tuning in accordance with the , resulting in a complicated circuit configuration. The present invention was made in order to eliminate the above-mentioned drawbacks.The third harmonic, which has a particularly large influence, is removed by a rectifier circuit, and even if the filter installed in front of the rectifier circuit has a rough fixed cutoff frequency, the accuracy is sufficiently high. disproportionate
The purpose of this invention is to provide a synchronous rectifier circuit for a dynamic balance tester that can obtain a DC signal corresponding to a 90° force component. The feature of the present invention is that the unbalanced signal is synchronously rectified over half the cycle of the circuit in synchronization with the rotation of the test machine, and even harmonics are removed using three synchronous rectifier circuits with a phase difference of 60 degrees from each other. Then, add the outputs of the three synchronous rectifier circuits to synthesize a pseudo fundamental wave, and then synchronize with the rotation of the test machine and synchronize the above pseudo fundamental wave over 1/3 of the rotation period. The third harmonic is removed using two synchronous rectifier circuits with a phase difference of 120° from each other, and the outputs of these two synchronous rectifiers are calculated to generate a DC signal corresponding to the unbalanced 90° component of the force. The reason is that it is configured to obtain the following. Embodiments of the present invention will be described below based on the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. The unbalance signals are synchronized with the rotation of the test machine and
It is introduced into a first rectifier circuit group A consisting of three synchronous rectifier circuits having a phase difference of 60 degrees and performing synchronous rectification over a half period of the rotation period. The three synchronous rectifier circuits constituting this first rectifier circuit group A each include resistors 1a, 1b, 1c, switches 2a, 2b, 2c, 3a, 3b, 3c, and capacitors 4a, 4b, 4c, 5a, 5b. , 5c. In each synchronous rectifier circuit, switches 2a and 3a, 2b and 3b, 2c
and 3c repeat opening and closing in opposite phases to each other, and the opening or closing time is 1/2 of the rotation period of the testing machine.
The opening/closing operations of a, 3b, and 3c) have a phase difference of 60° from each other. This switch 2a, 2b, 2
The opening/closing timing of c, 3a, 3b, and 3c is, for example, based on the reference phase symbol for detecting a mark on the test object, and is a square wave having the same frequency as that frequency and a pulse width of 1/2 of the period. Pulse signal, 0°, 60°, 120° with respect to the reference phase signal
Control can be achieved by generating pulses with phase differences of °, 180°, 240°, and 300°.
After the outputs of the three synchronous rectifier circuits are introduced into the adder 6, they are synchronized with the rotation of the test machine, have a phase difference of 120 degrees from each other, and are synchronously rectified over a period of 1/3 of the rotation period. The second rectifier circuit group B consists of two synchronous rectifier circuits. The two synchronous rectifier circuits constituting the second rectifier circuit group B are each comprised of resistors 7a, 7b, switches 8a, 8b, and integrators 9a, 9b. Switches 8a and 8b of each synchronous rectifier circuit are
They have a phase difference of 120° from each other and are closed for 1/3 of the rotation period of the testing machine. Further, the phase of the switch 8a is controlled to be in the same phase as the phase of the switch 2a in the first rectifier circuit group. The opening/closing timing of the switches 8a and 8b is also the same as that of the switch 2a in the first rectifier circuit group.
It can be controlled by means similar to the above. Of the outputs of these two synchronous rectifier circuits, the one output from the integrator 9a is passed through a resistor 10 to the operational amplifier 1.
2 and output from the integrator 9b is input to the operational amplifier 12 via the resistor 11, and outputs one component (Y component) of the DC signal corresponding to the unbalanced 90° component force component. connected to the terminal. Furthermore, the output of the operational amplifier 12 is connected to the output terminal of the other component (X component). Resistors 10 and 11 and operational amplifier 12 are connected to integrator 9
This is provided to extract the unbalanced X component from the outputs of a and 9b.If the resistance values of the resistors 10 and 11 and the feedback resistor 13 of the operational amplifier 12 are R ₁ , R ₂ and R ₃ respectively, then It has a relationship that satisfies the equation. R ₂ = 2R ₁ ……(1) Next, the operation will be explained based on the output waveform diagrams shown in FIGS. 2, 3, and 4. FIG. 2 is a waveform diagram illustrating how the fundamental frequency component of the unbalance detection signal is changed into a condensed fundamental wave by the first rectifier circuit group A and the adder 6. Figure 2a is a waveform diagram of the fundamental frequency component of the unbalance detection signal, and assuming that its period T = 2π/ω, time t, amplitude A, and phase difference θ with respect to the reference phase signal, =A sin (ωt + θ)... (3) FIGS. 2b, 2c, and d are diagrams showing the opening/closing timing of the switches 2a, 2b, and 2c, respectively, and show ON as a high level and OFF as a low level. Note that the switches 3a, 3b, and 3c are controlled in opposite phases to those in FIG. 2b, c, and d, respectively, and are therefore not shown. Figure 2 e, f, and g are output waveform diagrams at the output common terminals of switches 2a and 3a, 2b and 3b, and 2c and 3c, respectively. The signal passes through and becomes such a signal and is input to the adder 6. The adder 6 adds these signals to create a pseudo fundamental wave as shown in FIG. 2h. The amplitudes I ₁ , I ₂ , I ₃ , and I ₄ of each part of this pseudo fundamental wave are _{I 1} = I _{1 =} I ₅ +I ₆ +I ₇ ……(4) I ₂ =I ₅ +I ₆ −I ₇ ……(5) I ₃ =I ₅ −I ₆ +I ₇ ……(6) I ₄ =−I ₅ −I ₆ −I ₇ = −I ₁ ...(7), and each I ₅ , I ₆ , I ₇ is expressed as (3), Therefore, from (4), (5), (6), (7), (8), (9), (10), I ₁ = 2A/π (√3 sin θ + cos θ) ... (11) I ₂ = 4A/πcosθ...(12) _I3 =2A/π(-√3sinθ+cosθ)...(13) _I4 =-2A/π(√3sinθ+cosθ)...(14) FIG. 3 is a waveform diagram showing a process in which the third harmonic of the noise included in the unbalance detection signal is changed by the first rectifier circuit group A and the adder 6. Figure 3a is a waveform diagram showing the third harmonic of the fundamental frequency;
Figure 3 b, c, and d are reproductions of Figure 2 b, c, and d, and Figure 3 e, f, and g are the third harmonic signals that have passed through the first rectifier circuit group A, respectively. , _the adder 6 adds these _, and the amplitudes I ₈ , I ₉ , I ₁₀ at _each part in FIG. Then, I ₈ = I ₁₁ + I ₁₂ + I ₁₃ ……(15) I ₉ = I ₁₁ + I ₁₂ − I ₁₃ ……(16) I ₁₀ = I ₁₁ − I ₁₂ − I ₁₃ ……(17) , if the third harmonic is g(3ωt)=Bsin(3ωt+α)...(18), Therefore, (15), (16), (17), (18), (19)
，
From (20) and (21), I ₈ = −I ₉ = I ₁₀ ...(22). FIG. 4 is a waveform diagram showing a process in which the fundamental frequency component and its third harmonic component that have passed through the first rectifier circuit group A and the adder 6 are changed by the second rectifier circuit group B. Figures 4a and b are reproductions of Figures 2h and 3h, Figure 4c,
d is the switch 8a in the second rectifier circuit group B;
8b is a diagram showing the opening/closing timing of 8b. Figure 4a
The pseudo fundamental wave shown in FIG. 4 is transmitted to the DC signal shown in FIG. is converted into a DC signal shown in FIG. 4f and output. _The voltages I ₁₄ and I ₁₅ of _the signals e _{and f} in FIG _{. 4} )/2 ...(25) is expressed as (11), (12), (13), and (14). becomes. Also, the second rectifier circuit group B for the third harmonic component
The output waveforms from the integrators 9a and 9b are as shown in Figure 4g and h.If the voltages are I ₁₆ and I ₁₇ , then from (22) I ₁₆ = I ₈ + I ₉ = 0...( 28) I ₁₇ = I ₁₀ + I ₉ = 0 ...(29) and is completely removed. Of the two DC signals obtained by synchronously rectifying the above-mentioned pseudo fundamental wave in the second rectifier circuit group B, the signal is output from the integrator 9b.
As is clearer from (27), a DC signal with a voltage of I ₁₅ is Then, Y=C ₁ sinθ (31), which can be used as one DC component (Y component) corresponding to the unbalanced 90° component of force. In addition, the other DC component (X component) corresponding to the unbalanced 90° force component is generated by the DC signal with the voltage I ₁₄ output from the integrator 9a and the DC signal with the voltage I ₁₅ . _In other words _{, to obtain} In order for this (34) to hold true, α/2−β=0…(35),

【formula】 Substituting (36) into (35),

【formula】

[Formula] Therefore, using I ₁₄ and I ₁₅ , the resistance 1
If the relationship between 0 and 11 and the feedback resistor 13 of the operational amplifier 12 is configured as in (1) and (2) above, X of (32) can be obtained. In addition, as shown in FIG. 5, the first rectifier circuit group A has switches 3a, 3b, 3c and capacitors 5a, 5b, 5c removed, and a direct current cut circuit is installed between the adder 6 and the second rectifier circuit group B. A similar effect can be obtained even if the capacitor 14 is provided. As explained above, according to the present invention, it is possible to completely remove the third harmonic within the synchronous rectifier circuit. It is not necessary to provide a filter in front of the filter, and it is possible to obtain sufficiently accurate X and Y components by simply providing a filter with a fixed cutoff frequency.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG.
3 and 4 are action explanatory diagrams showing the output waveforms of each part, and FIG. 5 is a circuit configuration diagram showing the main part of another embodiment of the present invention. 2a, 2b, 2c... switch, 3a, 3b,
3c...Switch, 4a, 4b, 4c...Capacitor, 5a, 5b, 5c...Capacitor, 6...
Adder, 8a, 8b...Switch, 9a, 9b...
... Integrator, 10, 11 ... Resistor, 12 ... Operational amplifier, 13 ... Feedback resistor, 14 ... DC cut capacitor, A ... First rectifier circuit group, B ... Second rectifier circuit group .

Claims (1)

[Claims] 1. A first rectifier circuit group consisting of three synchronous rectifier circuits that are synchronized with the rotation of the testing machine, have a phase difference of 60 degrees from each other, and each synchronously rectify an unbalanced signal over a half period of the rotation period; an adder circuit that adds the outputs of each synchronous rectifier circuit of the first rectifier circuit group; A second rectifier circuit group consisting of two synchronous rectifier circuits that synchronously rectify the circuit output, and an arithmetic circuit that extracts a DC signal corresponding to an unbalanced 90° component of force from the output of the second rectifier circuit group. Synchronous rectifier circuit for dynamic balance tester.