JPS62589B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Summary> The present invention relates to improvement of a high voltage field effect semiconductor device.

More specifically, in a double diffused insulated gate field effect transistor (hereinafter referred to as DSA MOS FET), the N ^- layer that forms the pinch resistance and the P layer that forms the base region are separated by a certain distance, and When the concentration of the N ^- layer is appropriately selected, even if a positive voltage is applied to the gate of the device, it is possible to reach a drain-source voltage V _DS with a high withstand voltage in the on-state of the device. In other words, the present invention provides a semiconductor device that operates stably even at V _DS where the current saturation region in the on-state of the element is high.

<Prior art> There is a demand for an element that can drive capacitive elements that need to be switched at a higher voltage than conventional ones, but when driving a capacitive element, the voltage-current characteristics of the driving element are shown in Figure 1. The same potential is required in both the on and off states. In other words, as shown in FIG. 2, a capacitive load 60 is connected in parallel to the DSA MOS FET 50, and several 100 capacitive loads are connected to this parallel circuit via a voltage supply circuit 70 such as a resistor.
For a circuit that applies a high voltage of 80 volts,
When the DSA MOS FET 50 is in the off state (V _G =0), the load 60 is charged to a high voltage 80, reaching point a in FIG. 1, and then when the DSA MOS FET 50 is in the on state (V _G >0), the load The charged charge is discharged through point b in FIG. 1, and a switch operation is performed to reach point c.

The problems of the conventional device will be explained below using the drawings.

Conventional high-voltage DSA MOS FETs are shown in Figure 3a~
As shown in FIG. d, the semiconductor substrate 1 is, for example, a P-type substrate with a low impurity concentration, and ³¹ P ⁺ ions are implanted onto its surface through a thin insulator (for example, SiO ₂ ) 12 using ion implantation technology. Then, an N ^-pinch resistance layer 2 is formed on the entire surface (FIG. 3a). the next thickest
SiO ₂ 3 is formed on the surface of the substrate 1, a window is opened using photolithography technology, a thin SiO ₂ film 6 is further formed, and then a resist 4 is covered and a window is opened partially using ion implantation technology. , forming a P-type effective channel region, that is, a base region 5 (FIG. 3b). After removing the resist 4 and the thin SiO ₂ film 6, N ⁺ type impurity layers 7 and 8 are formed by diffusion or the like through the first opened window. A part of the N ⁺ type region becomes the drain region 7 and the other part becomes the source region 8 (FIG. 3c). After finally forming the gate region
A metal such as Al is formed by vapor deposition or the like, and unnecessary portions are removed to form a drain electrode 9, a gate electrode 10, and a source electrode 11 (FIG. 3d). The element is P-
It forms an annular shape centered at P′.

N-channel high voltage withstand voltage formed in this way
In the DSA MOS FET-, ³¹ P ⁺ ions are implanted all over the drift region to form the N ^- layer 2, so a sufficient voltage is applied to the gate to form an effective channel. When a positive voltage is applied to the drain, the depletion layer extends significantly into the base region P layer 5, and punch-through occurs at a relatively low drain voltage. This is because a PN junction is formed with the N ^- pinch resistance layer 2 at the end of the base region 5, and a concentration gradient is formed in the channel region by canceling each other. Also N ^-
When forming the pinch resistance layer 2, if ion implantation is performed at a relatively low concentration, the N ^-pinch resistance layer 2 will be depleted as soon as a voltage is applied to the drain, and once depleted, the charge will be reduced. Neutrality conditions must be met. That is, the drain region 7
It is necessary to deplete N ⁺ , and since the drain region 7 has a high concentration, the P layer in the base region 5 is rapidly depleted, causing punch-through at a relatively low voltage. Furthermore, when a high concentration of ions is implanted into the N ^-pinch resistance layer 2, the N ^-pinch resistance layer 2 is difficult to be depleted and therefore cannot absorb the drain voltage completely, increasing the potential in the P layer of the base region 5. , depletion into the P layer 5 is promoted, and as a result, it is thought that a punch-through phenomenon occurs at a relatively low drain voltage.

<Purpose of the present invention> The present invention was invented based on the above idea, and the present invention is based on the above idea, and the present invention is to separate the N ^- layer forming the pinch resistance and the P layer forming the base region by a certain distance. Another feature is that the concentration of the N ^- layer is appropriately selected to increase the withstand voltage in the on state.

<Structure of the Invention> The present invention provides a high voltage withstand voltage that eliminates such drawbacks by simply adding a single glass mask without complicating the process.
It provides MOS FET. A high voltage MOS FET according to an embodiment of the present invention will be described below.

The first point of the present invention is to provide a space between the end of the effective channel portion P layer 5 under the gate insulating layer and the N ^- pinch resistance layer, and the second point is to provide a space between the end of the effective channel portion P layer 5 under the gate insulating layer and the N ^- pinch resistance layer. The goal is to set the dose of ³¹ P ⁺ to an appropriate value.

The process of the high voltage MOS FET according to the present invention is shown in FIGS. 4a to 4d, and the differences from the conventional example will be described. When implanting ^{31P +} ions to form the N ^- pinch resistance layer 2 into the semiconductor substrate 1, a thin SiO ₂ 12
is formed on the surface of the substrate 1, a resist 4 is applied, and a portion is opened (FIG. 4a). SiO ₂ from this opening
³¹ P ⁺ ions are implanted through the membrane 12 by ion implantation technique to form the N ^- pinch resistance layer 2 . When performing ion implantation, the dose must be appropriately selected.

Next, a thick SiO ₂ film 3 is formed on the surface of the substrate 1 excluding the resist 4, and a window is opened using photolithography. The part to be opened is a channel region 5 formed by implanting and diffusing impurity ions.
This is a location where the end portion of the N ^-pinch resistance layer 2 forms a distance d. The SiO ₂ film 3 is covered with a resist 4, and a window is opened only in the portion where the base region 5 is to be formed. Then, impurities are implanted using ion implantation technology to form a P-type effective channel region, that is, a base region 5 (FIG. 4b).

Hereinafter, the processes shown in FIGS. 4c and d are performed in the same manner as those shown in FIGS. 3c and d.

<Effects of the Invention> The high voltage DSA MOS FET according to the present invention has a space between the N ^-pinch resistance layer 2 and the base region P layer 5, and by providing the π layer of the substrate 1 at this space,
The spread of the depletion layer in the direction of the P layer 5 is restricted, making it difficult to cause punch-through phenomenon. In the conventional structure shown in FIG. 1, a constant gate voltage, e.g.
The breakdown voltage when _G = 5V is applied is about 375V, but the element according to the present invention can obtain a breakdown voltage of about 500V. Furthermore, although there is a capacitance between the N ^- pinch resistance layer 2 and the gate electrode 10, this capacitance is reduced. In other words, the input capacity becomes smaller. However, if the value of d shown in Figure 4b is too large, the ionic resistance will increase, and even if the drain voltage is applied after the voltage necessary to form an effective channel is applied to the gate. A state in which no current flows, in other words, an offset voltage occurs. Taking this into consideration, a restriction is naturally placed on the range of d, and in this device, when the distance of the drift region from the drain region 7 and the end to the base region 5 is 30 to 100 μm, d=
It becomes 5 to 15 μm. The concentrations of the base region P layer 5 and the N ^- pinch resistance layer 2 can be determined independently without canceling each other out. Further, the appropriate dose of ³¹ P ⁺ ions is 7×10 ¹¹ /cm ² to 2×10 ¹² /cm ² .

[Brief explanation of the drawing]

Figure 1 is an example of an output static characteristic diagram of a MOS FET, Figure 2 is a drive circuit diagram of a MOS FET, Figure 3 is a cross-sectional view showing an example of a DSA/MOS/FET in a conventional process, and Figure 4 is a diagram of the present invention. High voltage DSA・
1 is a cross-sectional view showing an example of a MOS/FET. 1: Substrate region, 2: N ^- pinch resistance layer, 3: Field oxide film, 4: Resist, 5:
base region, 6: thin oxide film, 7: drain region, 8: source region, 9: drain electrode, 10:
Gate electrode, 11: source electrode.

Claims (1)

[Claims] 1. A source region and a drain region having one conductivity type, a pinch resistance layer continuous with the drain region and having an impurity concentration lower than that of the drain region, and a substrate having an impurity concentration higher than that of the other conductivity type. In a double diffused insulated gate field effect transistor comprising a channel region having an impurity concentration and formed in contact with a source region opposite to a drain, an interval is provided between the channel region and the pinch resistance layer. A high voltage field effect semiconductor device comprising: