JPS6259811B2 - - Google Patents

Description

Detailed Description of the Invention (A) Technical Field of the Invention The present invention relates to a data processing device, particularly a data processing device that has an addition/subtraction processing unit for floating point data and also performs division processing for floating point data. The present invention relates to a data processing device in which the processing previously performed, that is, the comparison processing of the size of a dividend and a divisor, is performed by an operand comparison circuit included in the addition/subtraction processing section.

(B) Technical background and problems When adding and subtracting floating point data OP1 and OP2, (OP1) + (OP2), (OP1) - (OP2), (OP2)
+ (OP1), (OP2) - (OP1), the output may be output as floating point data, and when subtraction is performed, the above data OP1 and OP2 It is necessary to subtract the smaller absolute value from the larger absolute value of each. For this purpose, such an addition/subtraction processing section is provided with an operand comparison circuit that compares the respective absolute values of data OP1 and OP2.

In general, in division, the divisor and dividend are compared before calculating the quotient to determine the number of bits (or number of digits) of the quotient, and then the calculation is performed for the corresponding number of cycles.

FIG. 2 is an explanatory diagram illustrating the number of bits of the quotient to be obtained for cases where the dividend is double precision data and when the dividend is single precision data. Since the mantissa of the dividend or divisor has 4 bits and represents a 1-digit number, the most significant digit of the divisor is
Pattern “1＊＊＊”, “01＊＊”, “001＊”,
There can be any pattern of "0001"("0000" does not exist in the case of normalized numbers), but corresponding to these patterns, there are cases where the quotient Q is greater than or equal to the value "1" and the value "1". As shown in the figure, the number of digits to be obtained as a quotient differs depending on the following cases.

For this reason, in the division process, processing modes are divided into cases where the quotient is greater than or equal to the value "1" and cases where the quotient is less than or equal to the value "1".

Conventionally, the following methods are known for separating processing modes. That is, (1) Calculate (dividend - divisor) using firmware and divide.

(2) In advance, division is performed assuming that the value is less than or equal to "1", and after the calculation, it is determined whether or not the value is greater than or equal to "1", and digit shift is performed.

Methods such as these are known.

However, in the case of the former method (1), for example, the basic part adder is used to execute (dividend minus divisor) during the above-mentioned divisor generation, but there are the following difficulties. That is, (a) In normal cases, the basic adder does not have enough data width to perform floating point calculations, so the calculation time is long.

(b) If the above basic calculation is not completed during preprocessing (while generating the divisor), it is necessary to reset the quotient counter, set the dividend again, and restart the quotient calculation cycle from the beginning.

In the case of the latter method (2), the quotient is calculated using the same number of cycles regardless of whether the quotient is greater than or equal to the value "1", but there are the following difficulties. That is, (c) if the value is "1" or more, unnecessary cycles of quotient calculation cycles (minimum 2 cycles) for 1 digit, that is, 4 bits are executed.

(d) It is necessary to have an extra quotient register of, for example, 4 bits for the value "1" or more.

(C) Object and Structure of the Invention The object of the present invention is to solve the above-mentioned problems, and the data processing device of the present invention has an addition/subtraction processing section for floating point data, and processes two operands in the addition/subtraction processing section. - In a data processing device that has an operand comparison circuit that checks the magnitude relationship of data and also has a division processing section that executes division processing of floating point data, the comparison result by the operand comparison circuit of the addition/subtraction processing section and the most significant digit of the divisor. The invention is characterized in that the number of quotient bits is obtained based on the value of and the calculation precision, and the number of addition/subtraction cycles by the division processing section is controlled based on the number of quotient bits. This will be explained below with reference to the drawings.

(D) Embodiment of the invention FIG. 3 shows the configuration of an embodiment of the invention.
In the figure, 1 is a division processing unit, 2 is an operand comparison circuit according to the present invention, which is present in the existing addition/subtraction processing unit, 3 and 4 are operand registers, 5 is an arithmetic buffer, and 6 is a divisor. generator; 7 is a division processing control unit; 8 is an adder/subtractor (basic adder);
9 is the division remainder register, 10 is the division multiple register,
11 is a remainder shifter, 13 is a quotient generator, 14 is a quotient counter (operation cycle counter), 15 is a quotient holding register, and 16 and 17 are selection circuits, respectively.

When the dividend OP1 and the divisor OP2 are set in operand registers 3 and 4, respectively, the most significant digit of each operand is led to the operand comparison circuit 2, and the quotient Q is determined whether Q≧1 or Q<1. It is checked whether the

On the other hand, the divisor OP2 is shifted through the divisor generator 6, passes through the adder/subtractor 8, and generates a divisor value in the divisor register 10.

Under this condition, from dividend OP1 to register 1
A selected one of the divisors among 0 is subtracted via the adder/subtractor 8, and the result is set in the register 9. Thereafter, as is well known, the addition and subtraction processing is repeated until the quotient counter 14 instructs the end. In other words, whether the quotient Q is ≧1 or Q<1,
The number of quotient bits is determined based on the value of the most significant digit of the divisor and the calculation precision, and based on this number of quotient bits, calculations are performed for the corresponding number of cycles. In other words, this number of times is controlled by the comparison result by the operand comparison circuit 2 described above.

(E) Effects of the Invention As explained above, according to the present invention, compared to the above-mentioned conventional method, there is no need to perform calculations using a basic adder, so no firmware is required. Moreover, there is no need to repeat the quotient calculation cycle, so there is no loss in execution time. Furthermore, compared to the conventional method described above, at least two cycles can be saved when the quotient is greater than or equal to the value "1", and there is no need to substantially increase the number of digits in the quotient register.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram explaining floating point data.
FIG. 2 is an explanatory diagram for explaining the number of digits required for determining the quotient, and FIG. 3 shows the configuration of an embodiment of the present invention. In the figure, 1 is a division processing unit, 2 is an operand comparison circuit, 3 and 4 are operand registers, 6 is a divisor generator, 8 is an adder/subtractor, 9 is a division remainder register, 10 is a divisor register, and 11 is a divisor remainder shifter,
13 represents a quotient generator, 14 represents a quotient counter, and 15 represents a quotient holding register.

Claims (1)

[Claims] 1. Data that has an addition/subtraction processing section for floating point data, an operand comparison circuit that checks the magnitude relationship between two operand data in the addition/subtraction processing section, and a division processing section that executes division processing of the floating point data. In the processing device, the number of quotient bits is determined based on the comparison result by the operand comparison circuit of the addition/subtraction processing section, the value of the most significant digit of the divisor, and the calculation precision, and the number of addition/subtraction cycles by the division processing section is determined based on the number of quotient bits. A data processing device characterized in that it is controlled.