JPS6262459B2 - - Google Patents
Info
- Publication number
- JPS6262459B2 JPS6262459B2 JP54109952A JP10995279A JPS6262459B2 JP S6262459 B2 JPS6262459 B2 JP S6262459B2 JP 54109952 A JP54109952 A JP 54109952A JP 10995279 A JP10995279 A JP 10995279A JP S6262459 B2 JPS6262459 B2 JP S6262459B2
- Authority
- JP
- Japan
- Prior art keywords
- charge
- value
- thickness
- semiconductor wafer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6324—Formation by anodic treatments, e.g. anodic oxidation
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
この発明は、半導体装置の製造方法に係り、特
に半導体の陽極酸化可能な膜を陽極酸化する際に
その酸化膜の膜厚を制御する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for controlling the thickness of an oxide film when anodizing a semiconductor film that can be anodized.
ここでは、半導体の陽極酸化工程の１つである
化成工程を用いて以下説明をする。従来、半導体
の化成工程では化成膜の膜厚制御は時間で行なつ
ていた。この膜厚制御方法は、１回に処理する半
導体ウエハの枚数が少ない時はそれほど問題とな
らない。ところが、１回に処理する半導体ウエハ
の枚数が多くなつたり、半導体ウエハの径が大き
くなると大きな問題となつて来る。それは、各半
導体ウエハの陽極電極の接触具合や化成液との接
触程度により、それぞれの化成膜の膜厚が異なつ
ており、それだけ１回に処理した半導体ウエハ間
で、化成膜の膜厚に大きなバラツキを生じるから
である。又、上記の理由により、化成膜の正確な
膜厚制御は困難であつた。 Here, the following description will be made using a chemical conversion process which is one of the anodic oxidation processes for semiconductors. Conventionally, in semiconductor chemical formation processes, the thickness of chemically formed films has been controlled by time. This film thickness control method does not pose much of a problem when the number of semiconductor wafers processed at one time is small. However, this becomes a serious problem as the number of semiconductor wafers processed at one time increases or as the diameter of the semiconductor wafers increases. The thickness of each chemically formed film differs depending on the degree of contact between the anode electrode of each semiconductor wafer and the degree of contact with the chemical solution. This is because large variations occur. Furthermore, for the above reasons, it has been difficult to accurately control the thickness of the chemically formed film.
本発明は、化成膜の正確な膜厚制御が可能な方
法を提供することにある。本発明の特徴は、化成
可能な膜に流れた電荷量に、化成膜の膜厚は比例
することを用い、電荷量によつて化成膜の膜厚を
制御する方法にある。 An object of the present invention is to provide a method capable of accurately controlling the thickness of a chemically formed film. A feature of the present invention is a method of controlling the thickness of a chemically formed film based on the amount of charge, using the fact that the thickness of the chemically formed film is proportional to the amount of charge flowing through the chemically formable film.
本発明の製造方法にかかる装置は、半導体ウエ
ハ上に形成された陽極酸化される膜に流す電流を
所定の時間間隔で計測する手段と、計測された
各々の電流を累積する手段と、累積された電流の
値が所定値になると陽極酸化を停止する手段とを
備えている。 The apparatus according to the manufacturing method of the present invention includes means for measuring, at predetermined time intervals, a current flowing through a film to be anodized formed on a semiconductor wafer, a means for accumulating each of the measured currents, and a means for accumulating each measured current. and means for stopping the anodic oxidation when the value of the current reaches a predetermined value.
下記に、本発明の実施例を用いて具体的に説明
する。第１図は、化成機構を表わしたものであ
り、半導体ウエハ２ａは陽極電極１ａに吸着さ
れ、下から化成液３ａが半導体ウエハ２ａ面上に
均一にあたり、化成が行なわれる。尚、陰極板４
ａは噴水ヘツド６ａの取り付けてある噴水槽５ａ
の中に固定してある。第２図は、本発明の実施例
の原理を表わしたグラフである。グラフの横軸は
時間（分）、縦軸は、半導体ウエハを流れる電流
値（ｍＡ）である。本発明の制御要素である電荷
量は第２図の斜線部分の面積であり、この面積と
化成膜の膜厚は比例している。この電荷量を求め
る為に、ある走査間隔時間ごとに電流値を検出
し、その電流値と、走査間隔時間の積を累計して
ゆく。その累計値があらかじめ設定した電荷量に
一致するか又は設定値より大きくなつたら、化成
電源を切り、化成を停止させる。尚、本実施例で
の走査間隔時間は６（秒）である。又電荷量の単
位は（ｍＡ・分）である。 The present invention will be specifically explained below using examples. FIG. 1 shows a chemical formation mechanism. A semiconductor wafer 2a is attracted to an anode electrode 1a, and a chemical liquid 3a uniformly hits the surface of the semiconductor wafer 2a from below to perform chemical formation. In addition, the cathode plate 4
a is a fountain tank 5a to which a fountain head 6a is attached;
It is fixed inside. FIG. 2 is a graph representing the principle of an embodiment of the present invention. The horizontal axis of the graph is time (minutes), and the vertical axis is the current value (mA) flowing through the semiconductor wafer. The amount of charge, which is a control element of the present invention, is the area of the shaded area in FIG. 2, and this area is proportional to the thickness of the chemically formed film. In order to determine the amount of charge, a current value is detected at each scanning interval time, and the product of the current value and the scanning interval time is accumulated. When the cumulative value matches the preset amount of charge or becomes larger than the set value, the formation power source is turned off and the formation is stopped. Note that the scanning interval time in this embodiment is 6 (seconds). The unit of charge amount is (mA/min).
第３図は、本発明に基く化成停止制御電気回路
の一ブロツク図である。ウエハ２ａを流れている
電流値を電流検出部３ｂで検出し、その電流値を
用いて、電荷量計算部４ｂで電荷量を求め累計す
る。その累計値と、電荷量設定部６ｂからの値と
を照合部５ｂで比較照合する。その結果を停止制
御部７ｂへ送り、そこで化成を停止させるか否か
を判断して、化成継続の場合には化成及電荷量計
算を継続する。化成停止の場合には、安定化電源
１ｂを切つて化成を停止する。 FIG. 3 is a block diagram of a formation stop control electrical circuit according to the present invention. The current value flowing through the wafer 2a is detected by the current detection section 3b, and using the detected current value, the amount of charge is determined and accumulated by the charge amount calculation section 4b. The cumulative value and the value from the charge amount setting section 6b are compared and verified by the matching section 5b. The result is sent to the stop control unit 7b, where it is determined whether or not to stop the chemical formation, and if the chemical formation is to be continued, the chemical formation and charge amount calculation are continued. In the case of stopping the chemical formation, the stabilized power supply 1b is turned off to stop the chemical formation.
電荷量の求め方は、上記の方法のみとは限ら
ず、電流曲線の方程式を求め、それを用いて必要
な電荷量から、正確な化成停止時間を求めて、膜
厚の制御を行なうことも可能である。 The method for determining the amount of charge is not limited to the method described above; it is also possible to determine the equation of the current curve and use it to determine the accurate chemical formation stop time from the required amount of charge to control the film thickness. It is possible.
本発明の電荷量で膜厚制御を行なうことにより
次のような効果がある。半導体ウエハと陽極電極
との接触状態及噴水ヘツドから出る化成液と半導
体ウエハとの接触状態のいかんにかかわらず、化
成膜の膜厚は、正確に制御される。これにより細
かい半導体のパターンが形成可能である。又各半
導体ウエハの膜厚制御を行なうことにより、１回
に処理する枚数の多少にかかわらず、そのバツチ
内での化成膜厚のバラツキを少なくすることが可
能となる。 By controlling the film thickness using the amount of charge according to the present invention, the following effects can be obtained. Regardless of the contact state between the semiconductor wafer and the anode electrode and the contact state between the chemical solution discharged from the fountain head and the semiconductor wafer, the thickness of the chemically formed film can be accurately controlled. This allows formation of fine semiconductor patterns. Furthermore, by controlling the film thickness of each semiconductor wafer, it is possible to reduce variations in the chemically formed film thickness within a batch, regardless of the number of wafers processed at one time.
これらの効果は、他の陽極酸化工程において
も、同様の効果が得られる。 Similar effects can be obtained in other anodizing processes as well.
第１図は、本発明の実施例の化成機構を示す側
面図であり、図中１ａ……陽極電極、２ａ……半
導体ウエハ、３ａ……化成液、４ａ……噴水槽、
５ａ……陰極電極、６ａ……噴水ヘツドである。
第２図は本発明の実施例の原理を表わした特性
図であり、縦軸は電流で単位はｍＡであり、横軸
は時間で単位は“秒”である。第３図は本発明の
実施例の化成停止制御電気回路のブロツク図であ
り、図中、１ｂ……安定化電源、２ａ……半導体
ウエハ、３ｂ……電流検出部、４ｂ……電荷量計
算部、５ｂ……照合部、６ｂ……電荷量設定部、
７ｂ……停止制御部である。
FIG. 1 is a side view showing the chemical conversion mechanism of the embodiment of the present invention, in which 1a...anode electrode, 2a...semiconductor wafer, 3a...chemical solution, 4a...fountain tank,
5a... cathode electrode, 6a... fountain head. FIG. 2 is a characteristic diagram showing the principle of the embodiment of the present invention, in which the vertical axis is current in mA, and the horizontal axis is time in seconds. FIG. 3 is a block diagram of a chemical formation stop control electric circuit according to an embodiment of the present invention, in which 1b... stabilized power supply, 2a... semiconductor wafer, 3b... current detection section, 4b... charge amount calculation section, 5b... verification section, 6b... charge amount setting section,
7b...This is a stop control section.
Claims (1)
ハに夫々酸化膜を形成する半導体装置の製造方法
において、各半導体ウエハ毎にウエハに流れる陽
極酸化時の電流値を所定の時間間隔で測定してそ
の累積値を求め、該累積値が予め定められた値を
越えると化成を停止することを特徴とする半導体
装置の製造方法。1. In a method for manufacturing a semiconductor device in which oxide films are formed on multiple semiconductor wafers by one-time anodic oxidation, the value of the current flowing through each semiconductor wafer during anodization is measured at predetermined time intervals. A method for manufacturing a semiconductor device, characterized in that a cumulative value of the cumulative value is determined, and when the cumulative value exceeds a predetermined value, chemical formation is stopped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10995279A JPS5633842A (en) | 1979-08-28 | 1979-08-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10995279A JPS5633842A (en) | 1979-08-28 | 1979-08-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5633842A JPS5633842A (en) | 1981-04-04 |
| JPS6262459B2 true JPS6262459B2 (en) | 1987-12-26 |
Family
ID=14523281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10995279A Granted JPS5633842A (en) | 1979-08-28 | 1979-08-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5633842A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0492658U (en) * | 1990-12-29 | 1992-08-12 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3827949A (en) * | 1972-03-29 | 1974-08-06 | Ibm | Anodic oxide passivated planar aluminum metallurgy system and method of producing |
-
1979
- 1979-08-28 JP JP10995279A patent/JPS5633842A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0492658U (en) * | 1990-12-29 | 1992-08-12 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5633842A (en) | 1981-04-04 |
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