JPH0567063B2 - - Google Patents
Info
- Publication number
- JPH0567063B2 JPH0567063B2 JP16955986A JP16955986A JPH0567063B2 JP H0567063 B2 JPH0567063 B2 JP H0567063B2 JP 16955986 A JP16955986 A JP 16955986A JP 16955986 A JP16955986 A JP 16955986A JP H0567063 B2 JPH0567063 B2 JP H0567063B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- etching
- support plate
- electrode
- measuring device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
<産業上の利用分野>
この発明は、半導体の深さ方向の不純物濃度分
布を簡単に求めることができる装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an apparatus that can easily determine the impurity concentration distribution in the depth direction of a semiconductor.
<従来の技術>
半導体素子は、シリコンウエハーに不純物を拡
散して所望の特性を得るものであり、拡散を制御
するためには、深さ方向不純物濃度分布を正確に
測定する必要がある。深さ方向の不純物濃度を測
定する従来技術の1つとして、被測定半導体の表
面を少しずつエツチングしながら、その表面の抵
抗率を測定する技術がある。すなわち、抵抗率ρ
と半導体中の不純物濃度Nとの間には、
ρ=(Neμ)-1
N=正味の不純物濃度
e=電荷
μ=多数のキヤリヤの移動度
の関係があり、抵抗率ρを測定することにより、
不純物濃度Nを決定できる。<Prior Art> Semiconductor devices obtain desired characteristics by diffusing impurities into a silicon wafer, and in order to control the diffusion, it is necessary to accurately measure the impurity concentration distribution in the depth direction. One of the conventional techniques for measuring the impurity concentration in the depth direction is a technique for measuring the resistivity of the surface of a semiconductor to be measured while etching the surface little by little. That is, resistivity ρ
There is a relationship between ρ = (Neμ) -1 N = net impurity concentration e = charge μ = mobility of many carriers, and by measuring the resistivity ρ, ,
The impurity concentration N can be determined.
このような不純物濃度測定の手順を第5図に示
す。第5図において、まず測定すべき半導体の初
期の表面抵抗を測定する。次にこの半導体を治具
に取付け、その表面を極くわずか陽極酸化する。 The procedure for such impurity concentration measurement is shown in FIG. In FIG. 5, first, the initial surface resistance of the semiconductor to be measured is measured. Next, this semiconductor is mounted on a jig, and its surface is anodized very slightly.
第6図に陽極酸化のための治具の一例を示す。
第6図において、1はテフロン製のサンプルホル
ダー、2は電極、3は電解液溜め、4はOリン
グ、5は被測定半導体、6はベークライトホルダ
ー、7はナイロン製ねじ、8はカバー、9,10
は端子である。端子9と電極2および端子10と
の電解溜め3内に設置された電極(図示せず)は
それぞれ電気的に導通している。被測定半導体5
はワツクスにより、ベークライトホルダー6に固
定され、ナイロン製ねじ7により、Oリング4を
介してサンプルホルダー1に固定される。電極2
は、図示しないスプリングにより、被測定半導体
5に押しつけられ、電気的導通が保たれている。
なお、電解液溜め3には、電解液が充満されてい
る。この状態で端子9,10間に電圧を印加する
と、被測定半導体5の表面が陽極酸化される。 FIG. 6 shows an example of a jig for anodizing.
In Fig. 6, 1 is a Teflon sample holder, 2 is an electrode, 3 is an electrolyte reservoir, 4 is an O-ring, 5 is a semiconductor to be measured, 6 is a Bakelite holder, 7 is a nylon screw, 8 is a cover, 9 ,10
is a terminal. Electrodes (not shown) installed in the electrolytic reservoir 3 between the terminal 9, the electrode 2, and the terminal 10 are electrically connected to each other. Semiconductor to be measured 5
is fixed to the Bakelite holder 6 with wax, and fixed to the sample holder 1 with a nylon screw 7 via an O-ring 4. Electrode 2
is pressed against the semiconductor to be measured 5 by a spring (not shown) to maintain electrical continuity.
Note that the electrolytic solution reservoir 3 is filled with electrolytic solution. When a voltage is applied between the terminals 9 and 10 in this state, the surface of the semiconductor to be measured 5 is anodized.
第5図において、陽極酸化された酸化膜厚はエ
リプソメータ等で測定される。その後、フツ酸等
で酸化膜厚をエツチングして除去し、段差および
表面抵抗を測定する。所定の深さまで測定したか
を調べ、測定していなければ陽極酸化から繰り返
し、測定が終了すれば、表面抵抗から不純物濃度
を求め、酸化膜厚、段差の測定値とを合わせて、
深さ方向の不純物濃度を決定する。 In FIG. 5, the thickness of the anodized oxide film is measured using an ellipsometer or the like. Thereafter, the oxide film thickness is removed by etching with hydrofluoric acid or the like, and the step height and surface resistance are measured. Check whether the measurement has been made to the specified depth, and if it has not been measured, repeat the process from anodic oxidation. Once the measurement is complete, calculate the impurity concentration from the surface resistance, combine it with the measured values of oxide film thickness and step,
Determine the impurity concentration in the depth direction.
第7図に表面抵抗測定の原理を示す。表面抵抗
は通常四探針法により求める。第7図において、
11,12は探針、13は可変電圧源、14は電
流計、15は電圧計である。可変電圧源13と電
流計14は接続されて電極11に、電圧計15は
電極12に接続される。探針11,12は適当な
圧力で被測定半導体5に接触させられる。探針1
1,12の間隔が等しいとすると、表面抵抗ρsは
ρs=4.532・V/I
V=電圧計15の指示電圧
I=電流計14の指示電流
で求められる。 Figure 7 shows the principle of surface resistance measurement. Surface resistance is usually determined by the four-point probe method. In Figure 7,
11 and 12 are probes, 13 is a variable voltage source, 14 is an ammeter, and 15 is a voltmeter. The variable voltage source 13 and the ammeter 14 are connected to the electrode 11, and the voltmeter 15 is connected to the electrode 12. The probes 11 and 12 are brought into contact with the semiconductor to be measured 5 with appropriate pressure. Probe 1
Assuming that the spacing between 1 and 12 is equal, the surface resistance ρs is determined as follows: ρs=4.532·V/I V=voltage indicated by the voltmeter 15=voltage indicated by the ammeter 14=current indicated by the ammeter 14.
<発明が解決すべき問題点>
しかしながらこのような不純物濃度分布の測定
技術では、深さ方向1点の測定に陽極酸化、酸化
膜厚測定、エツチング、段差測定、表面抵抗測定
の5工程を経なければならず、その都度被測定半
導体を治具または測定装置に着脱しなければなら
ない。また深さ方向の分布を求めるためには、こ
のような工程を50〜100回繰り返さなければなら
ない。従つて工程が繁雑になり、測定に多大の時
間を要していた。また、測定中に誤つて試料をこ
わしたり、表面を汚して測定が不可能になるよう
なことも発生した。<Problems to be solved by the invention> However, with this impurity concentration distribution measurement technology, measurement of one point in the depth direction requires five steps: anodization, oxide film thickness measurement, etching, step measurement, and surface resistance measurement. The semiconductor to be measured must be attached to and removed from the jig or measuring device each time. Furthermore, in order to obtain the distribution in the depth direction, such a process must be repeated 50 to 100 times. Therefore, the process became complicated and the measurement took a lot of time. Additionally, there were cases where the sample was accidentally broken during measurement or the surface became dirty, making measurement impossible.
<発明の目的>
この発明の目的は、構造が簡単でかつ容易に半
導体の不純物濃度分布が測定できる半導体の特性
測定装置を提供することにある。<Object of the Invention> An object of the invention is to provide a semiconductor characteristic measuring device that has a simple structure and can easily measure the impurity concentration distribution of a semiconductor.
<問題点を解決するための手段>
上記問題点を解決するために本発明は、半導体
表面のエツチングと抵抗測定を繰り返し、前記半
導体の不純物濃度分布を求める半導体の特性測定
装置において、
開口部を有するホルダーと、このホルダーの開
口部の縁部から所定の距離を隔てた内側に可とう
性の支持板により気密に仕切つて形成された室
と、前記支持板上に凸設された抵抗測定用電極
と、前記ホルダーに形成され前記支持板と前記縁
部との間に形成される開口部に連通しエツチング
液の注入及び排出を行う透孔と、前記室に連通す
る圧力導入孔とを有することを特徴とするもので
ある。<Means for Solving the Problems> In order to solve the above-mentioned problems, the present invention provides a semiconductor characteristic measuring device that repeats etching and resistance measurement of the semiconductor surface to determine the impurity concentration distribution of the semiconductor. a holder having a holder, a chamber airtightly partitioned by a flexible support plate inside the holder at a predetermined distance from the edge of the opening of the holder, and a resistance measurement chamber provided protrudingly on the support plate. an electrode, a through hole formed in the holder and communicating with an opening formed between the support plate and the edge for injecting and discharging etching solution, and a pressure introduction hole communicating with the chamber. It is characterized by this.
また、上記手段にエツチング時の電流を測定す
る電流測定手段と、この電流測定手段の出力によ
り、エツチング量を演算する演算手段を付加した
ものである。 Furthermore, the above-mentioned means is further provided with current measuring means for measuring the current during etching, and calculating means for calculating the amount of etching based on the output of the current measuring means.
<作用>
ホルダーを被測定半導体の測定面に密着させ、
透孔より、被測定半導体と支持板およびホルダー
で囲まれた空間にエツチング液を導入してエツチ
ングし、その後エツチング液を排出して、被測定
半導体の表面抵抗を測定する。エツチングと表面
抵抗の測定が同一のホルダーで、かつ被測定半導
体を取り外さなくてもできる。<Function> Bring the holder into close contact with the measurement surface of the semiconductor to be measured,
An etching solution is introduced into the space surrounded by the semiconductor to be measured, a support plate, and a holder through the through hole to perform etching, and then the etching solution is discharged to measure the surface resistance of the semiconductor to be measured. Etching and surface resistance measurement can be performed using the same holder and without removing the semiconductor to be measured.
また、エツチング時のエツチング電流を測定
し、その電流を演算手段で積分して、エツチング
量を求める。 Further, the etching current during etching is measured, and the current is integrated by a calculating means to obtain the etching amount.
<実施例>
第1図に本発明に係る半導体の特性測定装置の
一実施例を示す。第1図において、10は外筒、
11は外筒10に形成された透孔、12は内筒、
13は内筒12に形成された圧力導入口である。
14はダイヤフラムであり、このダイヤフラム1
4には、抵抗測定用の電極15が突設されてい
る。ダイヤフラム14は、内筒12により、隙間
のないように外筒10固定されている。16は電
極15を固定するための固定板であり、ダイヤフ
ラム14と固定板16で支持板を構成している。
17は端子であり、電極15と導線18で接続さ
れている。端子17は充填剤19で固定されてい
る。20は被測定半導体5に取り付けられた端子
である。なお、外筒10、内筒12、充填剤19
でホルダーを形成しており、被測定半導体5に密
着固定されている。<Example> FIG. 1 shows an example of a semiconductor characteristic measuring device according to the present invention. In FIG. 1, 10 is an outer cylinder;
11 is a through hole formed in the outer cylinder 10, 12 is an inner cylinder,
13 is a pressure introduction port formed in the inner cylinder 12.
14 is a diaphragm, and this diaphragm 1
4 is provided with a protruding electrode 15 for resistance measurement. The diaphragm 14 is fixed to the outer cylinder 10 by the inner cylinder 12 without any gaps. 16 is a fixing plate for fixing the electrode 15, and the diaphragm 14 and the fixing plate 16 constitute a support plate.
17 is a terminal, which is connected to the electrode 15 by a conductor 18. Terminal 17 is fixed with filler 19. 20 is a terminal attached to the semiconductor to be measured 5. In addition, the outer cylinder 10, the inner cylinder 12, and the filler 19
The holder is closely fixed to the semiconductor to be measured 5.
次にこの実施例の動作を第2図フローチヤート
に基いて説明する。動作は次の手順で行なう。 Next, the operation of this embodiment will be explained based on the flowchart of FIG. The operation is performed in the following steps.
(1) 圧力導入口13から圧縮空気を導入する。ホ
ルダーの中空部の圧力が高くなり、第3図のよ
うにダイヤフラム14がたわみ、電極15が被
測定半導体5に接触する。(1) Introduce compressed air from the pressure introduction port 13. The pressure in the hollow part of the holder increases, and the diaphragm 14 bends as shown in FIG. 3, causing the electrode 15 to come into contact with the semiconductor to be measured 5.
(2) 被測定半導体5の表面抵抗を測定する。(2) Measure the surface resistance of the semiconductor to be measured 5.
(3) 圧力導入口13を開放にする。ダイヤフラム
14がもとにもどり、電極15が被測定半導体
5から離れる。(3) Open pressure inlet 13. The diaphragm 14 returns to its original position, and the electrode 15 separates from the semiconductor to be measured 5.
(4) 透孔11からエツチング液をダイヤフラム1
4と被測定半導体5の間の空隙に導入する。(4) Pour the etching liquid into the diaphragm 1 through the through hole 11.
4 and the semiconductor to be measured 5.
(5) エツチングする。(5) Etching.
(6) エツチング液を排出する。(6) Drain the etching solution.
(7) 圧力導入口13から圧縮空気を導入し、電極
15を被測定半導体に接触させる。(7) Compressed air is introduced from the pressure introduction port 13 and the electrode 15 is brought into contact with the semiconductor to be measured.
(8) 被測定半導体5の表面抵抗を測定する。(8) Measure the surface resistance of the semiconductor to be measured 5.
(9) 段差を測定して、エツチング深さを求める。(9) Measure the step and find the etching depth.
(10) 所定の深さまで達すれば、表面抵抗と段差か
ら不純物濃度を求めて終了する。達しなければ
(4)にもどる。(10) When a predetermined depth is reached, the impurity concentration is determined from the surface resistance and the step difference, and the process ends. If you don't reach
Return to (4).
表面抵抗は電極15により、第7図で説明した
四探針法を用いて測定する。また、エツチングは
化学的に腐食させるか電解エツチングで行なう。 The surface resistance is measured using the electrode 15 using the four-probe method described in FIG. Further, etching is performed by chemical etching or electrolytic etching.
第4図に電解エツチングを行なう場合の構成を
示す。第4図において、21は可変電圧源、22
は電流測定手段、23は演算手段である。可変電
圧源21と電流測定手段22は直列に接続され、
端子17側が正極になるように端子17,20に
接続されている。電流測定手段22の出力は演算
手段23に出力される。この構成において、電極
15の被測定半導体5の間に電流を流すと、被測
定半導体5の構成原子がイオン化され、エツチン
グ液中に溶け出してエツチングされる。このと
き、エツチング量dと電流I(t)との間には
d=K/S∫T 0I(t)dt
K=比例定数
S=エツチング面積
T=エツチング時間
の関係がある。従つて、演算手段23により、上
式の演算を行えばエツチング量が算出でき、段差
測定が不用になる。電極15は、表面抵抗測定と
電解エツチングに共用するので、図示しない切り
換え器で切り換える。 FIG. 4 shows a configuration for performing electrolytic etching. In FIG. 4, 21 is a variable voltage source, 22
23 is a current measuring means, and 23 is a calculation means. The variable voltage source 21 and the current measuring means 22 are connected in series,
It is connected to terminals 17 and 20 so that the terminal 17 side becomes the positive electrode. The output of the current measuring means 22 is output to the calculating means 23. In this configuration, when a current is passed between the semiconductor to be measured 5 of the electrode 15, the constituent atoms of the semiconductor to be measured 5 are ionized, dissolved into the etching solution, and etched. At this time, there is a relationship between the etching amount d and the current I(t) as follows: d=K/S∫ T 0 I(t)dt K=proportionality constant S=etching area T=etching time. Therefore, if the calculation means 23 performs the calculation of the above equation, the etching amount can be calculated, and step measurement becomes unnecessary. Since the electrode 15 is commonly used for surface resistance measurement and electrolytic etching, it is switched by a switch (not shown).
なお、第4図において、24は光源である。n
型半導体においては、被測定半導体5の表面とエ
ツチング液の境界で逆方向のバリヤが生じるた
め、電流がほとんど流れないので、エツチングが
進行しない。そのため、半導体表面に光を照射し
て電子と正孔を生ぜしめ、電流を流すようにす
る。この場合、ダイアフラム14と固定数16か
らなる支持板を透光性材料で構成し、光が被測定
半導体表面上に十分照射するようにする。光は圧
力導入口13からフアイバ等で導くようにしても
よい。 In addition, in FIG. 4, 24 is a light source. n
In the type semiconductor, a barrier in the opposite direction is created at the boundary between the surface of the semiconductor to be measured 5 and the etching solution, so that almost no current flows, so that etching does not proceed. For this reason, light is irradiated onto the semiconductor surface to generate electrons and holes, causing current to flow. In this case, the support plate consisting of the diaphragm 14 and the fixed number 16 is made of a light-transmitting material, so that the surface of the semiconductor to be measured is sufficiently irradiated with light. The light may be guided from the pressure introduction port 13 using a fiber or the like.
またこの実施例では、抵抗測定用電極と電解エ
ツチング用電極を電極15で共用するようにした
が、電解エツチング用電極を別に設けるようにし
てもよい。この場合、電解エツチング用電極は、
被測定半導体5に接触しない位置でかつ、エツチ
ング液に接触する位置に固定する。 Further, in this embodiment, the electrode 15 is used in common as the resistance measuring electrode and the electrolytic etching electrode, but the electrolytic etching electrode may be provided separately. In this case, the electrode for electrolytic etching is
It is fixed at a position that does not come into contact with the semiconductor to be measured 5 and comes into contact with the etching solution.
また、支持板をダイヤフラム14と固定板16
で構成し、圧力導入口13から圧縮空気を導入し
て電極15を可動するようにしたが、空気シリン
ダや電極シリンダ等で電極15を可動するように
してもよい。 In addition, the support plate is connected to the diaphragm 14 and the fixing plate 16.
Although the electrode 15 is moved by introducing compressed air from the pressure introduction port 13, the electrode 15 may be moved using an air cylinder, an electrode cylinder, or the like.
<発明の効果>
以上実施例に基いて具体的に説明したように、
本発明によれば、エツチングと表面抵抗の測定を
同一の装置で行なうことができる。そのため、被
測定半導体を取り外す回数が少なくなり、不純物
濃度の測定を迅速に行なうことができる。また、
被測定半導体を汚したり、破損したりすることが
少なくなるので、より正確な測定ができる。<Effects of the invention> As specifically explained above based on the examples,
According to the present invention, etching and surface resistance measurement can be performed using the same device. Therefore, the number of times the semiconductor to be measured is removed is reduced, and the impurity concentration can be measured quickly. Also,
Since there is less chance of contaminating or damaging the semiconductor to be measured, more accurate measurements can be made.
また、電解エツチングを用い、エツチング量を
電解電流の積算値から求めようにすることによつ
て、被測定半導体を装置に装着したままで全ての
測定を実行することができる。そのため、測定が
さらに迅速に行なうことができ、被測定半導体を
汚損することもない。 Further, by using electrolytic etching and determining the etching amount from the integrated value of electrolytic current, all measurements can be performed with the semiconductor to be measured attached to the apparatus. Therefore, the measurement can be performed more quickly and the semiconductor to be measured is not contaminated.
さらに、電極の可動手段としてダイヤフラムを
用い、また電解エツチング用電極と抵抗測定用電
極を共用することにより、装置の構造を簡単にす
ることができる。また、支持板に透光性材料を用
いて、被測定半導体表面に光を照射できるように
することにより、n型半導体でも効率よくエツチ
ングできる。 Furthermore, the structure of the apparatus can be simplified by using a diaphragm as a means for moving the electrodes, and by using the electrolytic etching electrode and the resistance measuring electrode in common. Furthermore, by using a light-transmitting material for the support plate so that light can be irradiated onto the surface of the semiconductor to be measured, even n-type semiconductors can be etched efficiently.
第1図は本発明に係る半導体の特性測定装置の
一実施例を示す構成図、第2図は不純物濃度分布
測定の手順を示すフローチヤート、第3図は第1
図実施例の表面抵抗測定時の状態を示す構成図、
第4図は第1図実施例の電解エツチングを説明す
るための構成ブロツク図、第5図は従来の不純物
濃度分布測定を説明するためのフローチヤート、
第6図は従来の陽極酸化用治具の一例を示す構成
図、第7図は四探針法による表面抵抗測定の原理
を示す図である。
5……被測定半導体、10……外筒、11……
透孔、12……内筒、13……圧力導入口、14
……ダイヤフラム、15……電極、16……固定
板、17,20……端子、21……可変電圧源、
22……電流測定手段、23……演算手段、24
……光源。
FIG. 1 is a block diagram showing an embodiment of the semiconductor characteristic measuring device according to the present invention, FIG. 2 is a flowchart showing the procedure for measuring impurity concentration distribution, and FIG.
A configuration diagram showing the state during surface resistance measurement of the example shown in FIG.
FIG. 4 is a configuration block diagram for explaining the electrolytic etching of the embodiment shown in FIG. 1, and FIG. 5 is a flowchart for explaining conventional impurity concentration distribution measurement.
FIG. 6 is a block diagram showing an example of a conventional anodic oxidation jig, and FIG. 7 is a diagram showing the principle of surface resistance measurement using the four-probe method. 5...Semiconductor to be measured, 10...Outer cylinder, 11...
Through hole, 12... Inner cylinder, 13... Pressure introduction port, 14
... diaphragm, 15 ... electrode, 16 ... fixed plate, 17, 20 ... terminal, 21 ... variable voltage source,
22...Current measuring means, 23...Calculating means, 24
……light source.
Claims (1)
し、前記半導体の不純物濃度分布を求める半導体
の特性測定装置において、 開口部を有するホルダーと、このホルダーの開
口部の縁部から所定の距離を隔てた内側に可とう
性の支持板により気密に仕切つて形成された室
と、前記支持板上に凸設された抵抗測定用電極
と、前記ホルダーに形成され前記支持板と前記縁
部との間に形成される開口部に連通しエツチング
液の注入及び排出を行う透孔と、前記 室に連通
する圧力導入孔とを有することを特徴とする半導
体の特性測定装置。 2 前記支持板としてダイアフラムを用いたこと
を特徴とする特許請求の範囲第1項記載の半導体
の特性測定装置。 3 前記支持板として透光性材料を用いたことを
特徴とする特許請求の範囲第1項記載の半導体の
特性測定装置。 4 前記抵抗測定用電極をエツチング用電極とし
て用いることを特徴とする特許請求の範囲第1項
記載の半導体の特性測定装置。 5 半導体表面のエツチングと抵抗測定を繰り返
し、前記半導体の不純物濃度分布を求める半導体
の特性測定装置において、 開口部を有するホルダーと、このホルダーの開
口部の縁部から所定の距離を隔てた内側に可とう
性の支持板により気密に仕切つて形成された室
と、前記支持板上に凸設された抵抗測定用電極
と、前記ホルダーに形成され前記支持板と前記縁
部との間に形成される開口部に連通しエツチング
液の注入及び排出を行う透孔と、前記 室に連通
する圧力導入孔と、前記エツチング時に流れる電
流を測定する電流測定手段と、この電流測定手段
の出力によりエツチング量を演算する演算手段と
を有することを特徴とする半導体の特性測定装
置。 6 前記支持板としてダイアフラムを用いたこと
を特徴とする特許請求の範囲第2項記載の半導体
の特性測定装置。 7 前記支持板として透光性材料を用いたことを
特徴とする特許請求の範囲第2項記載の半導体の
特性測定装置。 8 前記抵抗測定用電極をエツチング用電極とし
て用いることを特徴とする特許請求の範囲第2項
記載の半導体の特性測定装置。[Scope of Claims] 1. A semiconductor characteristic measuring device for repeatedly etching a semiconductor surface and measuring resistance to determine the impurity concentration distribution of the semiconductor, comprising: a holder having an opening; a chamber airtightly partitioned by a flexible support plate on the inner side separated by a distance; a resistance measurement electrode protruding on the support plate; and a resistance measurement electrode formed on the holder and formed on the support plate and the edge. 1. An apparatus for measuring characteristics of a semiconductor, comprising: a through hole communicating with an opening formed between the chambers and for injecting and discharging an etching solution; and a pressure introducing hole communicating with the chamber. 2. The semiconductor characteristic measuring device according to claim 1, wherein a diaphragm is used as the support plate. 3. The semiconductor characteristic measuring device according to claim 1, wherein a light-transmitting material is used as the support plate. 4. The semiconductor characteristic measuring device according to claim 1, wherein the resistance measuring electrode is used as an etching electrode. 5. In a semiconductor characteristic measuring device that repeatedly etches the surface of a semiconductor and measures resistance to determine the impurity concentration distribution of the semiconductor, the device comprises: a holder having an opening; A chamber airtightly partitioned by a flexible support plate, a resistance measuring electrode provided protrudingly on the support plate, and a resistance measuring electrode formed on the holder between the support plate and the edge. a through hole communicating with the opening for injecting and discharging the etching solution, a pressure introducing hole communicating with the chamber, a current measuring means for measuring the current flowing during the etching, and an etching amount determined by the output of the current measuring means. What is claimed is: 1. A semiconductor characteristic measuring device, comprising: calculation means for calculating. 6. The semiconductor characteristic measuring device according to claim 2, wherein a diaphragm is used as the support plate. 7. The semiconductor characteristic measuring device according to claim 2, wherein a light-transmitting material is used as the support plate. 8. The semiconductor characteristic measuring device according to claim 2, wherein the resistance measuring electrode is used as an etching electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16955986A JPS6327031A (en) | 1986-07-18 | 1986-07-18 | Apparatus for measuring characteristics of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16955986A JPS6327031A (en) | 1986-07-18 | 1986-07-18 | Apparatus for measuring characteristics of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6327031A JPS6327031A (en) | 1988-02-04 |
| JPH0567063B2 true JPH0567063B2 (en) | 1993-09-24 |
Family
ID=15888708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16955986A Granted JPS6327031A (en) | 1986-07-18 | 1986-07-18 | Apparatus for measuring characteristics of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6327031A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2907059B2 (en) * | 1995-04-27 | 1999-06-21 | 日本電気株式会社 | Impurity diffusion profile measurement method |
| JP4556698B2 (en) * | 2005-02-14 | 2010-10-06 | ソニー株式会社 | Probe pin unit |
| JP4826882B2 (en) * | 2005-05-18 | 2011-11-30 | 株式会社 アイアイエスマテリアル | Method for sorting and analyzing scrap silicon |
-
1986
- 1986-07-18 JP JP16955986A patent/JPS6327031A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6327031A (en) | 1988-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20050052191A1 (en) | In situ determination of resistivity, mobility and dopant concentration profiles | |
| Zhang et al. | Porous silicon formation and electropolishing of silicon by anodic polarization in HF solution | |
| US4338157A (en) | Method for forming electrical connecting lines by monitoring the etch rate during wet etching | |
| US4891103A (en) | Anadization system with remote voltage sensing and active feedback control capabilities | |
| US3660250A (en) | Method of determining impurity profile of a semiconductor body | |
| US11699622B2 (en) | Methods and apparatus for test pattern forming and film property measurement | |
| US4103228A (en) | Method for determining whether holes in dielectric layers are opened | |
| US3803489A (en) | Liquid contacts for use in semiconductor doping profile analysis | |
| CN1332432C (en) | Method and device for determining backgate characteristics | |
| JPH0567063B2 (en) | ||
| Harten | The surface recombination on silicon contacting an electrolyte | |
| US7190186B2 (en) | Method and apparatus for determining concentration of defects and/or impurities in a semiconductor wafer | |
| US3554891A (en) | Automatic impurity profiling machine | |
| Szeponik et al. | A new structure for chemical sensor devices | |
| Kinder et al. | Carrier profiling of a heterojunction bipolar transistor and p–i–n photodiode structures by electrochemical C–V technique | |
| US7250313B2 (en) | Method of detecting un-annealed ion implants | |
| JPH0630368B2 (en) | Semiconductor characteristic measuring device | |
| Stacey et al. | Using surface charge analysis to characterize the radiation response of Si/SiO/sub 2/structures | |
| US20260005073A1 (en) | Methods for electrical property depth profiling through films with graded composition | |
| Carver et al. | Well‐Defined Contacts Produce Accurate Spreading Resistance Measurements | |
| RU2717259C1 (en) | Method of measuring electrical conductivity of pure and deionised liquid | |
| US20240353472A1 (en) | Methods and tools for electrical property depth profiling using electro-etching | |
| SU1420548A1 (en) | Method of measuring specific resistance | |
| RU1775753C (en) | Method of charge carrier mobility profile determination in semiconductor layers | |
| Kinder et al. | The influence of the electrolyte-semiconductor interface on the doping profile measurement of a GaAs structure |