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JPS6262477B2 - - Google Patents
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JPS6262477B2 - - Google Patents

Info

Publication number
JPS6262477B2
JPS6262477B2 JP56166564A JP16656481A JPS6262477B2 JP S6262477 B2 JPS6262477 B2 JP S6262477B2 JP 56166564 A JP56166564 A JP 56166564A JP 16656481 A JP16656481 A JP 16656481A JP S6262477 B2 JPS6262477 B2 JP S6262477B2
Authority
JP
Japan
Prior art keywords
layer
gaas
receiving element
light receiving
gaas substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56166564A
Other languages
Japanese (ja)
Other versions
JPS5867075A (en
Inventor
Masanori Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56166564A priority Critical patent/JPS5867075A/en
Publication of JPS5867075A publication Critical patent/JPS5867075A/en
Publication of JPS6262477B2 publication Critical patent/JPS6262477B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/103Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/223Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】 本発明は、一のGaAs基板上に受光素子と電界
効果トランジスタ(以下FETと略称する)素子
とが設けられた複合半導体装置の改良に関す。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a composite semiconductor device in which a light receiving element and a field effect transistor (hereinafter abbreviated as FET) element are provided on one GaAs substrate.

GaAs基板上にフオトダイオードを形成し、該
フオトダイオードより得られる信号電流の増幅或
いは演算処理等を行うFET等を同一GaAs基板上
に形成する複合半導体装置が既に試みられてい
る。
Attempts have already been made to create a composite semiconductor device in which a photodiode is formed on a GaAs substrate, and an FET and the like for amplifying a signal current obtained from the photodiode, arithmetic processing, etc. are formed on the same GaAs substrate.

第1図は従来技術による該複合半導体装置の一
例を示す断面図である。第1図において、領域A
は受光素子部、領域BはFET素子部であつて、
受光素子は、半絶縁性n−GaAs基板1上に亜鉛
(Zn)等を深さ1μm程度に拡散することにより
P+層2を形成し、該P+層より電極3、n−GaAs
基板1上に他の電極4を設けることにより形成さ
れる。又、FET素子はn−GaAs基板1上にキヤ
リリア濃度が1×1017cm-13程度のn+−GaAs層5
を厚さ0.2μm程度に成長せしめ、ソース電極6
及びドレイン電極7を金ゲルマニウム(AuGe)
等を用い、又ゲート電極8をアルミニウム
(Al)等を用いて配設することにより形成され、
その後、絶縁層及び所望の配線パターンが設けら
れる。
FIG. 1 is a sectional view showing an example of the composite semiconductor device according to the prior art. In Figure 1, area A
is the light receiving element part, and area B is the FET element part,
The photodetector is made by diffusing zinc (Zn) etc. to a depth of about 1 μm on a semi-insulating n-GaAs substrate 1.
A P + layer 2 is formed, and an electrode 3 is formed from the P + layer, and n-GaAs
It is formed by providing another electrode 4 on the substrate 1. In addition, the FET element has an n + -GaAs layer 5 with a carrier concentration of about 1×10 17 cm -13 on an n - GaAs substrate 1.
The source electrode 6 is grown to a thickness of about 0.2 μm.
and the drain electrode 7 is made of gold germanium (AuGe).
etc., and by disposing the gate electrode 8 using aluminum (Al) or the like,
Thereafter, an insulating layer and a desired wiring pattern are provided.

以上説明した構造の複合半導体装置において
は、半絶縁性GaAs基板1により受光素子の能動
層を構成するとともに、FET素子と受光素子及
びFET素子相互間の素子分離効果を求めている
ものであつて、受光素子がウインド層を有しない
ために、入射光により生じたキヤリアのP+層中
での再結合及び表面結合が短波長側で大きく、そ
の量子効率が第2図に示す如く、短波長側で大幅
に低下する欠点がある。又素子間の分離も充分で
はなく絶縁性を高める必要がある。
In the composite semiconductor device having the structure described above, the semi-insulating GaAs substrate 1 constitutes the active layer of the light-receiving element, and an element isolation effect between the FET element, the light-receiving element, and the FET elements is desired. , because the photodetector does not have a window layer, the recombination and surface bonding of carriers generated by the incident light in the P + layer are large on the short wavelength side, and the quantum efficiency is large on the short wavelength side, as shown in Figure 2. There is a drawback that it drops significantly on the side. Furthermore, the isolation between elements is not sufficient and it is necessary to improve insulation.

本発明の目的は、一のGaAs基板上に受光素子
とFET素子とが設けられた複合半導体装置にお
いて受光素子にウインド層を設けて量子効率を改
善するとともに、素子相互間の絶縁性を高める構
造を提供することにある。
An object of the present invention is to improve the quantum efficiency by providing a window layer on the light receiving element in a composite semiconductor device in which a light receiving element and a FET element are provided on one GaAs substrate, and to create a structure that improves the insulation between the elements. Our goal is to provide the following.

本発明の前記目的は、FET素子の能動層とす
るGaAs層が該GaAs基板上に半絶縁性AlxGa1
xAs(0<X≦1)層を介して形成され、該
AlxGa1−xAs層が該受光素子のウインド層を構
成することにより達成され、更に受光素子の周囲
においてGaAs基板上に形成された層をメサエツ
チングすることにより、受光素子とFET素子群
との分離が完全となる。
The object of the present invention is that the GaAs layer serving as the active layer of the FET element is formed by forming a semi-insulating AlxGa 1 - on the GaAs substrate.
Formed through an xAs (0<X≦1) layer,
This is achieved by making the AlxGa 1 -xAs layer constitute the window layer of the photodetector, and by mesa-etching the layer formed on the GaAs substrate around the photodetector, the photodetector and the FET element group can be separated. Become complete.

以下に、本発明を実施例により図面を参照して
具体的に説明する。
Hereinafter, the present invention will be specifically described by way of examples with reference to the drawings.

第3図は本発明の第一の実施例を示す断面図で
ある。第3図に示す如く、n+−GaAs基板11上
に、分子ビームエピタキシヤル成長法(以下
MBE法と略称する)或いは気相エピタキシヤル
成長法(以下VPE法と略称する)により、キヤ
リア濃度が5×1016cm-3程度以上のn−GaAs層
12を厚さ3μm程度に、次いでキヤリア濃度が
1×1014cm-3程度以下の半絶縁性n-
Al0.3Ga0.7As層13を厚さ2μm程度に、更に
キヤリア濃度が1×101 7cm-3程度のn+−GaAs層
14を厚さ0.2μm程度に順次成長させる。
FIG. 3 is a sectional view showing a first embodiment of the present invention. As shown in FIG. 3, a molecular beam epitaxial growth method (hereinafter referred to as
The n-GaAs layer 12 with a carrier concentration of about 5×10 16 cm -3 or more is formed to a thickness of about 3 μm by using a vapor phase epitaxial growth method (abbreviated as MBE method) or vapor phase epitaxial growth method (hereinafter abbreviated as VPE method). Semi-insulating n - - with a concentration of about 1 x 10 14 cm -3 or less
An Al0.3Ga0.7As layer 13 is grown to a thickness of about 2 μm, and an n + -GaAs layer 14 having a carrier concentration of about 1×10 17 cm −3 is grown to a thickness of about 0.2 μm.

しかる後に、受光素子を形成する領域Aのn+
−GaAs層14を選択的に除去し、二酸化シリコ
ン(SiO2)等をマスクとしてn-−Al0.3Ga0.7As層
13中にZnを濃度1018乃至1019cm-3程度、深さ1
μm程度に拡散してP+領域15を設ける。
After that, n + of the area A where the light receiving element is formed.
- Selectively remove the GaAs layer 14 and use silicon dioxide (SiO 2 ) as a mask to add Zn to the n - -Al0.3Ga0.7As layer 13 at a concentration of about 10 18 to 10 19 cm -3 and a depth of 1
The P + region 15 is provided by diffusing to about μm.

FET素子領域Bについては、通常のフオトリ
ソグラフイ法等によりn+−GaAs層14を各素子
に分離し、夫々ソース16、ドレイン17及びゲ
ート18を形成する。なお、受光素子についても
P領域15及びn+−GaAs基板11に電極19及
び20を設ける。
Regarding the FET element region B, the n + -GaAs layer 14 is separated into each element by a normal photolithography method, and a source 16, a drain 17, and a gate 18 are formed respectively. Note that electrodes 19 and 20 are also provided on the P region 15 and the n + -GaAs substrate 11 for the light receiving element.

その後に、受光素子領域Aの周囲特にこれと
FET素子領域Bとの間のn-−Al0.3Ga0.7As層1
3及びn−GaAs層12を選択的に除去し受光素
子とFET素子とを分離するメサエツチングを施
す。
After that, the area around the light-receiving element area A, especially this area, is
n - -Al0.3Ga0.7As layer 1 between FET element area B
3 and the n-GaAs layer 12 are selectively removed, and mesa etching is performed to separate the light receiving element and the FET element.

以上の如くn-−Al0.3Ga0.7As層13をウイン
ド層とするGaAs pinフオトダイオードとGaAs
FETが同一GaAs基板上に形成される。
As described above, the GaAs pin photodiode and GaAs with the n - -Al0.3Ga0.7As layer 13 as the window layer
FETs are formed on the same GaAs substrate.

第4図は本発明の第二の実施例を示す断面図で
ある。本実施例は基板として半絶縁性GaAs基板
を用いるものであり、半絶縁性GaAs基板21上
に、キヤリア濃度が5×1016cm-3程度以上のn−
GaAs層22を厚さ3μm程度に、次いでキヤリ
ア濃度が1×1014cm-3程度以下の半絶縁性n-
AlxGa1−xAs層23を厚さμm程度に、更にキ
ヤリア濃度が1×1017cm-3程度のn+−GaAs層2
4を厚さ0.2μm程度に、MBE法或いはVPE法に
より形成し、前記第一の実施例と同様に各素子を
設けたものである。ただし、この第二の実施例に
おいては、FET素子領域B側以外で受光素子領
域Aの周辺の一部のメサエツチングをn-
AlxGa1−xAs層23のみとし、フオトダイオー
ドn側電極25をn−GaAs層22上に設けてい
る。
FIG. 4 is a sectional view showing a second embodiment of the present invention. In this embodiment , a semi-insulating GaAs substrate is used as the substrate .
The GaAs layer 22 is made to have a thickness of about 3 μm, and then a semi-insulating layer with a carrier concentration of about 1×10 14 cm -3 or less
The AlxGa 1 -xAs layer 23 has a thickness of about μm, and the n + -GaAs layer 2 has a carrier concentration of about 1×10 17 cm -3 .
4 was formed to a thickness of about 0.2 μm by the MBE method or the VPE method, and each element was provided in the same manner as in the first embodiment. However, in this second embodiment, part of the mesa etching around the light receiving element area A other than the FET element area B side is n - -
Only the AlxGa 1 -xAs layer 23 is used, and the photodiode n-side electrode 25 is provided on the n-GaAs layer 22.

この第二の実施例によれば受光素子領域Aと
FET素子領域Bとの間の分離絶縁が第一の実施
例より向上する。
According to this second embodiment, the light receiving element area A and
The isolation and insulation between the FET element region B and the FET element region B is improved compared to the first embodiment.

第5図は本発明の第三の実施例を示す断面図で
ある。本実施例は半絶縁性GaAs基板31上にキ
ヤリア濃度が1×1017cm-3程度のn+−GaAs層3
2を厚さ2μm程度に、次いでキヤリア濃度が
1014cm-3程度の半絶縁性GaAs層33を厚さ3μ
m程度に形成し、さかる後に前記例と同様に半絶
縁性n-−AlxGa1−xAs層34及びn+−GaAs層3
5を形成し、受光素子領域Aの周辺のメサエツチ
ングにより、FET素子領域B側においては半絶
縁性GaAs基板31のみを残置し、一部において
はn+−GaAs層32を残置して、フオトダイオー
ドのn側電極36を設けた例である。
FIG. 5 is a sectional view showing a third embodiment of the present invention. In this embodiment, an n + −GaAs layer 3 with a carrier concentration of about 1×10 17 cm −3 is formed on a semi-insulating GaAs substrate 31.
2 to a thickness of about 2 μm, and then the carrier concentration was
10 14 cm -3 semi-insulating GaAs layer 33 with a thickness of 3μ
After that, the semi-insulating n - -AlxGa 1 -xAs layer 34 and the n + -GaAs layer 3 are formed as in the previous example.
5, and by mesa etching around the light receiving element area A, only the semi-insulating GaAs substrate 31 is left on the FET element area B side, and the n + -GaAs layer 32 is left in a part, and a photodiode is formed. This is an example in which an n-side electrode 36 is provided.

この第三の実施例によればFET素子相互間及
びFET素子と受光素子との間の分離絶縁が更に
改善されるとともに、フオトダイオードの量子効
率も向上する。
According to this third embodiment, the isolation and insulation between the FET elements and between the FET element and the light receiving element are further improved, and the quantum efficiency of the photodiode is also improved.

第6図は前記第一の実施例について得られた量
子効率の一例を示す図表であつて、横軸は入射光
信号の波長(nm)を、縦軸は量子効率(%)を
示し、第2図に示した従来技術による場合に比較
して波長700nmにおいて約20%の量子効率の上
昇が見られ、100nm以上の帯域についてほぼ平
担な高い量子効率を得ている。
FIG. 6 is a chart showing an example of the quantum efficiency obtained for the first example, in which the horizontal axis shows the wavelength (nm) of the incident optical signal, the vertical axis shows the quantum efficiency (%), and Compared to the conventional technique shown in Figure 2, an increase in quantum efficiency of about 20% is observed at a wavelength of 700 nm, and a high quantum efficiency that is almost flat in the band of 100 nm or more is obtained.

また素子間の絶縁は、GaAsより絶縁性を向上
させ得るGaAlAs層によつてなされている。
Insulation between elements is provided by a GaAlAs layer, which can provide better insulation than GaAs.

以上説明した如く、本発明は一のGaAs基板上
に受光素子とFET素子とを設けた複合半導体装
置において、受光素子に半絶縁性AlxGa1−xAs
よりなるウインド層を設け、FET素子の能動層
を構成するGaAs層を該AlxGa1−xAs層を介して
形成することにより、受光素子の量子効率を向上
するとともに、各素子相互間の分離絶縁を改善
し、更に受光素子の周囲をメサエツチングするこ
とにより受光素子とFET素子群との分離を完全
にするものであつて、該複合半導体装置に対して
大きい改善効果を与える。
As explained above, the present invention provides a composite semiconductor device in which a light receiving element and a FET element are provided on one GaAs substrate, in which a semi-insulating AlxGa 1 -xAs is used for the light receiving element.
By forming a GaAs layer, which constitutes the active layer of the FET element, through the AlxGa 1 -xAs layer, the quantum efficiency of the light receiving element is improved and the isolation and insulation between each element is improved. Furthermore, by mesa-etching the periphery of the light-receiving element, the light-receiving element and the FET element group are completely separated, and this provides a great improvement effect on the composite semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術による実施例を示す断面図、
第2図は従来技術による受光素子の量子効率の一
例を示す図表、第3図乃至第5図は本発明の実施
例を示す断面図、第6図は本発明による受光素子
の量子効率の一例を示す図表である。 図において、1はGaAs基板、2はP+層、3は
電極、4は電極、5はGaAs層、6はソース電
極、7はドレイン電極、8はゲート電極、11は
n+−GaAs基板、12はn−GaAs層、13はn-
−Al0.3Ga0.7As層、14はn+−GaAs層、15は
P+領域、16はソース、17はドレイン、18
はゲート、19は電極、20は電極、21は
GaAs基板、22はn−GaAs層、23はn−
AlxGa1−xAs層、24はn+−GaAs層、25は電
極、31は半絶縁性GaAs基板、32はn+
GaAs層、33はGaAs層、34はn-−AlxGa1
xAs層、35はn+−GaAs層、36は電極を示
す。
FIG. 1 is a sectional view showing an embodiment according to the prior art;
FIG. 2 is a chart showing an example of the quantum efficiency of a light receiving element according to the prior art, FIGS. 3 to 5 are cross-sectional views showing an embodiment of the present invention, and FIG. 6 is an example of the quantum efficiency of a light receiving element according to the present invention. This is a chart showing the following. In the figure, 1 is a GaAs substrate, 2 is a P + layer, 3 is an electrode, 4 is an electrode, 5 is a GaAs layer, 6 is a source electrode, 7 is a drain electrode, 8 is a gate electrode, and 11 is a
n + -GaAs substrate, 12 is n-GaAs layer, 13 is n -
-Al0.3Ga0.7As layer, 14 is n + -GaAs layer, 15 is
P + region, 16 source, 17 drain, 18
is a gate, 19 is an electrode, 20 is an electrode, 21 is a
GaAs substrate, 22 is n-GaAs layer, 23 is n-
AlxGa 1 -xAs layer, 24 is n + -GaAs layer, 25 is electrode, 31 is semi-insulating GaAs substrate, 32 is n + -
GaAs layer, 33 is GaAs layer, 34 is n - -AlxGa 1 -
An xAs layer, 35 an n + -GaAs layer, and 36 an electrode.

Claims (1)

【特許請求の範囲】 1 一のGaAs基板上に受光素子と電界効果トラ
ンジスタ素子とが設けられた複合半導体装置にお
いて、電界効果トランジスタ素子の能動層を構成
するGaAs層が、該GaAs基板上にAlxGa1−xAs
(0<X≦1)層を介して形成され、該AlxGa1
xAs層が該受光素子のウインド層を構成してなる
ことを特徴とする複合半導体装置。 2 前記受光素子の周囲において、 前記GaAs基板上に形成された層の少なくとも
一部が選択的に除去されてなることを特徴とする
特許請求の範囲第1項記載の複合半導体装置。
[Claims] 1. In a composite semiconductor device in which a light receiving element and a field effect transistor element are provided on one GaAs substrate, the GaAs layer constituting the active layer of the field effect transistor element is formed on the GaAs substrate by AlxGa 1 −xAs
(0<X≦1) layer, and the AlxGa 1
A composite semiconductor device characterized in that an xAs layer constitutes a window layer of the light receiving element. 2. The composite semiconductor device according to claim 1, wherein at least a portion of the layer formed on the GaAs substrate is selectively removed around the light receiving element.
JP56166564A 1981-10-19 1981-10-19 Composite semiconductor device Granted JPS5867075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56166564A JPS5867075A (en) 1981-10-19 1981-10-19 Composite semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56166564A JPS5867075A (en) 1981-10-19 1981-10-19 Composite semiconductor device

Publications (2)

Publication Number Publication Date
JPS5867075A JPS5867075A (en) 1983-04-21
JPS6262477B2 true JPS6262477B2 (en) 1987-12-26

Family

ID=15833596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56166564A Granted JPS5867075A (en) 1981-10-19 1981-10-19 Composite semiconductor device

Country Status (1)

Country Link
JP (1) JPS5867075A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350372U (en) * 1989-09-21 1991-05-16

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0746720B2 (en) * 1986-02-20 1995-05-17 キヤノン株式会社 Photoelectric conversion device
JPH0770697B2 (en) * 1986-08-15 1995-07-31 日本電気株式会社 Array type infrared detector

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56104155U (en) * 1980-01-11 1981-08-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350372U (en) * 1989-09-21 1991-05-16

Also Published As

Publication number Publication date
JPS5867075A (en) 1983-04-21

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