JPS627581B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a duplex information line switching method for a system having two information lines connected to one processor. The present invention relates to a duplex information line switching system that prohibits the use of one information line and the switching from one information line to another information line.

FIG. 1 is a diagram showing a conventional information line switching system for a system having two information lines connected to one processor. In the figure, 1 is a processor, 2,
2' is a control/status register, 3 and 3' are information line interfaces, and 4 and 4' are information lines. The processor (hereinafter referred to as CPU) 1 selects which information line to use for transmission, and sends the control signal to the control/status register 2 or 2' on the side that uses the information line interface 3 or 3. ' to the information line 4 or 4'. In the case of reception, the CPU 1 looks at both control/status registers 2, 2', determines which one received the signal, and takes action accordingly. However, this case has the disadvantage that two types of programs are required to control the information lines 4 and 4', respectively. Also, the two information lines 4 and 4' may be disconnected due to noise or malfunction of the opposing equipment.
may be in use at the same time, so that the system can operate normally even in such cases.
I needed to create a complex program.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information line switching system that can stably control opposing equipment with a simple program in order to eliminate the above-mentioned drawbacks.

In order to achieve the above object, the present invention provides a duplex information line switching method for a system having two information lines connected to one processor, in which when one information line is used, the other information line is used; A prohibition circuit is provided to prohibit switching from one information line to the other information line, and when one information line is used in a state where two information lines can be connected to the processor, duplex information, characterized in that a control signal for connecting the information line to the processor is sent to the prohibition circuit to prohibit the use of the other information line and to prohibit switching from one information line to the other information line. Provides line switching method.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an information line switching system according to an embodiment of the present invention, and FIG. 3 is a block configuration diagram seen from the software of the CPU 1 of the present invention. 1st in the diagram
Items with the same functions as those in the figure are indicated by the same symbols. 2″, 2
is a control/status register, 3'', 3, 3 is an information line interface, 4'' is an information line, 5, 5' is an inhibition circuit, 6, 6' is a control signal line, 7, 7' is a signal line It is. A case where data is transmitted from the CPU 1 using one of the information lines 4 will be explained. When the control/status register 2'' selects the information line interface 3'' by a command from the CPU 1, the information line interface 3'' connects the information line 4 to the CPU 1 via the control signal line 6 to the inhibition circuit 5'. control signal to disable the information line interface 3. That is, while the information line 4 is in use, the information line 4'
This prohibits the use of the information line 4 and the switching of the information line from the information line 4 to the information line 4'. When using the information line 4', only one of the information lines can be used and switching to the other information line is prohibited in the same manner as above. When the use of the information line 4 is completed, the CPU 1 issues a prohibition release command to the control/status register 2'' to enable both the information line interfaces 3'' and 3 to be used.
In the case of reception, for example, when receiving from the information line 4, the information line interface 3''
sends a control signal notifying the reception of a signal from the information line 4 to the inhibition circuit 5' via the control signal line 6, thereby disabling the information line interface 3 from use.
That is, signals from the information line 4' are prohibited, and switching of the information line from the information line 4 to the information line 4' is prohibited.
The CPU 1 knows from the information from the control/status register 2 that the signal was received from the information line 4 and can read the received data from the information line 4. At this time, since the information line 4' side is prohibited from use, even if information is received, it is completely ignored.
That is, the signal from the information line 4' is not sent to the CPU 1, and switching to the information line 4' is not performed. The same applies to the case of receiving from the information line 4' side. Therefore, it is the third software for CPU1.
As shown in the figure, the information line interface 3 is recognized as one piece, and it can be set up by simply manipulating the control/status register 2.
It becomes possible to control multiple information line interfaces.

As explained above, according to the present invention, two information lines can be viewed from the software as having one information line interface, which simplifies programming, and when using one information line, Since switching control to the other information line is ignored, reliability can be improved regardless of noise or erroneous signals on the other information line.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an information line switching method of a conventional system having two information lines connected to one processor, and FIG. 2 is a diagram showing an information line switching method of a system showing an embodiment of the present invention. The figure shown in FIG. 3 is a block configuration diagram seen from the software of the CPU 1 in the case of FIG. In the figure, 1 is the CPU, 2, 2', 2'', 2 are the control/
Status register, 3, 3', 3'', 3, 3〓 are information line interfaces, 4, 4', 4'' are information lines,
5, 5' are inhibition circuits, 6, 6' are control signal lines, 7,
7' is a signal line.

Claims (1)

[Claims] 1. In a duplex information line switching method for a system having two information lines connected to one processor, when one information line is used, the other information line is used, and one information line is switched from one to the other. A prohibition circuit is provided to prohibit switching to the other information line, and if one of the information lines is used in a state where two information lines can be connected to the above processor, the one information line must be switched to the above processor. A duplex information switching system characterized in that a control signal for connection is sent to the prohibition circuit to prohibit the use of the other information line and to prohibit switching from one information line to the other information line.