JPS6310604B2 - - Google Patents
Info
- Publication number
- JPS6310604B2 JPS6310604B2 JP18087081A JP18087081A JPS6310604B2 JP S6310604 B2 JPS6310604 B2 JP S6310604B2 JP 18087081 A JP18087081 A JP 18087081A JP 18087081 A JP18087081 A JP 18087081A JP S6310604 B2 JPS6310604 B2 JP S6310604B2
- Authority
- JP
- Japan
- Prior art keywords
- detection
- circuit
- transistors
- double
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 23
- 238000010586 diagram Methods 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D1/00—Demodulation of amplitude-modulated oscillations
- H03D1/14—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles
- H03D1/18—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles of semiconductor devices
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Amplitude Modulation (AREA)
Description
【発明の詳細な説明】
本発明は、AM変調信号を否特性良く検波する
両波整流回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a double-wave rectifier circuit that detects an AM modulated signal with good inverse characteristics.
従来よりAM変調波の検波には、検波効率が良
い、歪特性が良い、搬送波(キヤリア)が2倍に
なることで後段のフイルターが構成し易い等の理
由によつて両波整流回路がよく用いられている。 Traditionally, a double-wave rectifier circuit has been used to detect AM modulated waves because of its good detection efficiency, good distortion characteristics, and doubling of the carrier wave, making it easier to configure the filter in the latter stage. It is used.
第1図は従来例として示す両波整流回路であ
る。第1図において、1は変調された信号の入力
端子、2は整流信号の出力端子、3は検波端子、
4,5は基準電圧端子、6は電源端子、7は接地
電位端子、8,9は同逆相波形形成のための差動
増幅器構成の各トランジスタ、10,11は夫々
上記両トランジスタ8,9の回路における電流源
トランジスタ、12,13は検波用OR回路トラ
ンジスタ、14は差動増幅器のエミツタ抵抗、1
5,16は負荷抵抗、17,18は電流源トラン
ジスタのエミツタ抵抗、19は検波回路の電流
源、20は信号入力のカツプリングコンデンサ、
21は検波後のキヤリアー除去ローパスフイルタ
ー、40,41はバイアス供給用抵抗である。 FIG. 1 shows a double-wave rectifier circuit as a conventional example. In FIG. 1, 1 is an input terminal for a modulated signal, 2 is an output terminal for a rectified signal, 3 is a detection terminal,
4 and 5 are reference voltage terminals, 6 is a power supply terminal, 7 is a ground potential terminal, 8 and 9 are transistors of a differential amplifier configuration for forming the same and opposite phase waveforms, and 10 and 11 are the above-mentioned transistors 8 and 9, respectively. The current source transistor in the circuit, 12 and 13 are OR circuit transistors for detection, 14 is the emitter resistor of the differential amplifier, 1
5 and 16 are load resistances, 17 and 18 are emitter resistances of current source transistors, 19 is a current source of the detection circuit, 20 is a coupling capacitor for signal input,
21 is a low-pass filter for removing carriers after detection, and 40 and 41 are bias supply resistors.
今、変調信号入力端子1に第2図aの信号が入
力されたとすると、上記差動回路中の一方のトラ
ンジスタ8のコレクターには、入力のaとは逆相
でα1倍の信号bが現われ、上記差動回路中の他方
のトランジスタ9のコレクターは上記入力のaと
同相でα2倍の信号cが現われる。この両コレクタ
信号b,cによつて得られる検波用OR回路から
の出力、すなわち、検波端子3での波形はdのご
とく両波整流の形になる。このdの波形の信号ス
ペクトラムは、信号波fsと搬送波fcに対して2fcが
現われる。そこで上記検波端子3に接続するロー
パスフイルター21の特性を第2図eのように決
めればfsとfcが近づいても充分分離できる。この
様にしてAM検波は出来るが、この第1図の回路
を構成する素子のバラツキを考慮すると次にのべ
る構な問題が生じてくる。ここで、第2図b,c
においてα1vin、α2vin、Vo1、Vo2は夫々次のよ
うな各式で表わせる。 Now, if the signal shown in Fig. 2 a is input to the modulation signal input terminal 1, the collector of one of the transistors 8 in the differential circuit receives a signal b whose phase is opposite to that of the input a and which is 1 times α. At the collector of the other transistor 9 in the differential circuit, a signal c which is in phase with the input a and which is twice as large as α appears. The output from the detection OR circuit obtained by these collector signals b and c, that is, the waveform at the detection terminal 3, is in the form of double-wave rectification as shown in d. In the signal spectrum of this waveform d, 2f c appears with respect to the signal wave f s and the carrier wave f c . Therefore, if the characteristics of the low-pass filter 21 connected to the detection terminal 3 are determined as shown in FIG. 2e, it is possible to sufficiently separate fs and fc even if they are close to each other. Although AM detection can be performed in this manner, considering the dispersion of the elements that make up the circuit shown in FIG. 1, the following problem arises. Here, Fig. 2 b, c
α 1 vin, α 2 vin, Vo 1 , and Vo 2 can be expressed by the following formulas.
α1Vin=RL1/REVin ………(1)
α2Vin=RL2/REVin ………(2)
Vo1=VCC−〔VB−VBE3/R1+(LB2RB2+VBE2)−(
IB1RB1+VBE1)/RE〕RL1………(3)
Vo2=VCC−〔VB−VBE4/R2−(IB2RB2+VBE2)−(
IB1RB1+VBE1)/RE〕RL2………(4)
先ずバラツキの要因の一つとして、差動増幅器
構成の両トランジスタ8,9の負荷抵抗15,1
6の各値がRL1≠RL2なる場合を考えてみよう。
RL1>RL2では検波端子3の出力波形は第3図a
のように同逆相ごとの振幅に差ができる。この時
上記トランジスタ8,9の各直流電位Vo1、Vo2
は、Vo1≠Vo2であるが検波出力波形として複雑
になるのを避けるため簡単にVo1Vo2としてい
る。この波形を前記フイルター21を通過させて
も搬送波成分fcは殆んど除去されておらず、第3
図bのようにキヤリアリーク成分として残る。単
純にRL1−RL2/RL1×100=5%(通常使用している
カーボン抵抗の相対比)として考えれば略々5%
のキヤリヤリークとなる。 α 1 Vin=R L1 /R E Vin……(1) α 2 Vin=R L2 /R E Vin……(2) Vo 1 =V CC −[V B −V BE3 /R 1 +(L B2 R B2 +V BE2 )−(
I B1 R B1 +V BE1 )/R E 〕R L1 ………(3) Vo 2 =V CC −[V B −V BE4 /R 2 −(I B2 R B2 +V BE2 )−(
I B1 R B1 +V BE1 )/R E ]R L2 ......(4) First, one of the factors causing the variation is the load resistances 15 and 1 of both transistors 8 and 9 in the differential amplifier configuration.
Let us consider the case where each value of 6 is R L1 ≠ R L2 .
When R L1 > R L2 , the output waveform of detection terminal 3 is as shown in Figure 3a.
There is a difference in amplitude between the same and opposite phases as shown in . At this time, the respective DC potentials Vo 1 and Vo 2 of the transistors 8 and 9
Although Vo 1 ≠ Vo 2 , it is simply set as Vo 1 Vo 2 to avoid complicating the detected output waveform. Even if this waveform is passed through the filter 21, the carrier wave component f c is hardly removed, and the third
It remains as a carrier leak component as shown in Figure b. If you simply consider R L1 −R L2 /R L1 ×100=5% (relative ratio of normally used carbon resistance), it is approximately 5%.
It becomes a carrier leak.
次にRL1=RL2であつても、Vo1<Vo2になる場
合、例えばR1>R2を考えると、検波端子3の出
力波形は第3図cのようになる。この場合も、
RL1>RL2の場合と同様にフイルター21通過後
でみると、小入力信号においては、波形が再現し
得ない部分が出てくる。これは歪となつて両波整
流回路にしたメリツトを損うものである。例えば
RL1=RL2=RE=1KΩ、IE4IE3=1mA、トラン
ジスタhFE=100、信号入力Vinを1Vp-pと選んだ
時、R1−R2/R1×100=5%でると仮定すると
IE4−IE3/IE4×100=5%であり、1mAに対して
50μAの誤差が発生しVo1−Vo2=50mV、出力
500mVp-p波形に対して50/2mV=25mVが誤差
として現われる。これも略々5%の歪成分に相当
すると考えてよい。 Next, even if R L1 =R L2 , if Vo 1 <Vo 2 , for example, considering R 1 >R 2 , the output waveform of the detection terminal 3 will be as shown in FIG. 3c. In this case too,
As in the case of R L1 > R L2 , when looking at the signal after passing through the filter 21, for small input signals, there are parts where the waveform cannot be reproduced. This results in distortion and detracts from the advantage of using a double-wave rectifier circuit. for example
When R L1 = R L2 = R E = 1KΩ, I E4 I E3 = 1 mA, transistor h FE = 100, and signal input Vin is 1V pp , R 1 − R 2 / R 1 × 100 = 5%. Assuming that I E4 - I E3 /I E4 ×100 = 5%, an error of 50 μA occurs for 1 mA, Vo 1 - Vo 2 = 50 mV, and the output
For a 500mV pp waveform, 50/2mV = 25mV appears as an error. This can also be considered to correspond to a distortion component of approximately 5%.
この様に、あまり注意深く抵抗値を選定しない
場合には、5%程度の歪、キヤリアリークが発生
すると考えてよい。本発明では、これらキヤリア
リーク、歪特性に関して著しく特性改善をなした
両波整流器を提供するものである。 In this way, if the resistance value is not selected very carefully, it can be considered that distortion and carrier leakage of about 5% will occur. The present invention provides a double-wave rectifier that has significantly improved carrier leakage and distortion characteristics.
第4図に本発明の一実施例を示し、第5図にそ
の各要部の信号波形を示す。第4図において、2
2,23は負極性の検波を行うPNP OR回路用
トランジスタ、24,25は正極性の検波を行う
NPN OR回路用トランジスタ、26,27はレ
ベルシフトトランジスタ、28,29は正負検波
波形の差動加算回路のトランジスタ、30は出力
エミツタホロワトランジスタ、31は上記差動加
算回路のエミツタ抵抗、32はコレクター負荷抵
抗、33,34,35,36,37,38,39
は定電流源であり、上記以外は第1図と同一構成
となつている。 FIG. 4 shows an embodiment of the present invention, and FIG. 5 shows signal waveforms of its main parts. In Figure 4, 2
2 and 23 are PNP OR circuit transistors that perform negative polarity detection, and 24 and 25 are positive polarity detection.
NPN OR circuit transistors, 26 and 27 are level shift transistors, 28 and 29 are transistors for a differential addition circuit for positive and negative detection waveforms, 30 is an output emitter follower transistor, 31 is an emitter resistor for the differential addition circuit, 32 is the collector load resistance, 33, 34, 35, 36, 37, 38, 39
is a constant current source, and has the same configuration as in FIG. 1 except for the above.
第2図aと同様な変調された信号が入力端子1
に入力されると、22,23のPNP OR回路ト
ランジスタのエミツタ共通点では、負の半波のみ
が取り出され、レベルシフト・トランジスタ26
を通過後上記差動加算回路の一方のトランジスタ
28のベースに第5図cの波形として現われる。
一方、上記OR回路のNPNトランジスタ24,2
5によつて検波された波形は同様にもうひとつの
レベルシヤフトトランジスタ27を介して上記差
動加算回路の他方のトランジスタ29のベースに
第5図bのように正の半波のみが取り出されてい
る。この時差動加算回路の出力、すなわち、トラ
ンジスタ28のコレクターには、常にベース電位
の差の成分が合成され第5図dのようになる。こ
こで
VC=VCC−〔I37+(VB13−VB14)1/RE〕RL
−VBE15
VB13=VREF−IB2RB2−VBE8+VBE11
VB14=VREF−IB1RB1+VBE9−VBE12
I37は電流源37の電流値
第1回の回路のときと同様にバラツキについて
の考察を加えてみよう。 A modulated signal similar to that shown in Figure 2a is input to input terminal 1.
When input to the level shift transistor 26, only the negative half wave is extracted at the common emitter point of the PNP OR circuit transistors 22 and 23.
After passing through, the waveform appears at the base of one transistor 28 of the differential adder circuit as shown in FIG. 5c.
On the other hand, the NPN transistors 24 and 2 of the above OR circuit
Similarly, only the positive half wave of the waveform detected by 5 is taken out to the base of the other transistor 29 of the differential adder circuit through another level shift transistor 27, as shown in FIG. 5b. There is. At this time, the output of the differential adder circuit, ie, the collector of the transistor 28, always combines the base potential difference components, as shown in FIG. 5d. Here, V C = V CC − [I 37 + (V B13 − V B14 ) 1/R E ] R L
−V BE15 V B13 =V REF −I B2 R B2 −V BE8 +V BE11 V B14 =V REF −I B1 R B1 +V BE9 −V BE12 I 37 is the current value of the current source 37 Let's also consider dispersion in the same way.
先ずVB14>VB13を考えるときは第6図aの様に
考えられるから端子3の出力波形は第6図bのご
とくになる。VCOは無信号状態でVB13=VB14の時
のトランジスタ28のコレクター直流電位であ
る。同じ様に、VB14<VB13の状態では第6図cの
波形になると考えられるから、検波端子3の出力
は第6図dの波形が得られる。上述の第6図b,
dの各波形で明らかなようにキヤリア−リーク、
歪等の発生はない。又差動加算回路トランジスタ
28,29のベースまでの経路では、単にエミツ
タホロワと見なしてよいので信号振幅の減衰は少
なく、更にトランジスタ24,26をNPN、ト
ランジスタ22,27がPNPと、それぞれ両信
号を得る回路構成が相補接続にしてあることから
その減衰量のバラツキは殆んどなく、第3図aの
様な現象は起らない。出力端子3におけるVC1,
VC2等のVCOからのズレは単に出力のダイナミツ
クレンジのバラツキとしてのみ問題となり、キヤ
リアリーク、歪には何の影響をも及ぼさない。更
に、トランジスタPNP、NPNを相補使用してい
ることからもVC1,VC2のズレの幅は少ない。 First, when considering V B14 >V B13 , it can be considered as shown in Figure 6a, so the output waveform of terminal 3 will be as shown in Figure 6b. V CO is the collector DC potential of the transistor 28 when V B13 = V B14 in a no-signal state. Similarly, in the state of V B14 <V B13 , the waveform shown in FIG. 6c is considered to be obtained, so that the output of the detection terminal 3 has the waveform shown in FIG. 6d. Figure 6b above,
As is clear from each waveform of d, carrier leakage,
No distortion or the like occurred. In addition, the paths to the bases of the differential adder transistors 28 and 29 can be simply regarded as emitter followers, so there is little attenuation of the signal amplitude, and furthermore, the transistors 24 and 26 are NPN, and the transistors 22 and 27 are PNP, so both signals are connected to each other. Since the obtained circuit configuration has a complementary connection, there is almost no variation in the amount of attenuation, and the phenomenon shown in FIG. 3a does not occur. V C1 at output terminal 3,
A deviation from V CO such as V C2 becomes a problem only as a variation in the output dynamic range, and has no effect on carrier leak or distortion. Furthermore, since the transistors PNP and NPN are used complementary, the deviation between V C1 and V C2 is small.
この様に極性に見合つたトランジスタを組み合
わせるだけで、実質的な両波整流が構成でき、検
波の両極性を差動増幅回路によつて合成する際に
直流成分のズレを消去できる本発明の方式であれ
ば、両波整流器としてのキヤリアリーク、歪の低
減に大なる効果をもたらす。 In this way, by simply combining transistors that match the polarity, a substantial double-wave rectification can be configured, and the present invention can eliminate the deviation of the DC component when combining both polarities of the detection using a differential amplifier circuit. If so, it will have a great effect on reducing carrier leakage and distortion as a double-wave rectifier.
第1図は従来の両波整流器の電気的回路図、第
2図、第3図は従来の両波整流器による各特性
図、第4図は本発明の一実施例である両波整流器
の電気的回路図、第5図、第6図はそれぞれ本発
明による両波整流器による特性例を示す図であ
る。
1……入力端子、2……出力端子、3……検波
端子、4,5……基準電圧端子、6……電源端
子、7……接地電位端子、21……ローパスフイ
ルター、22,23,24,25,26,27,
28,29……トランジスタ、33,34,3
5,36,37,38,39……定電流源。
Figure 1 is an electrical circuit diagram of a conventional double-wave rectifier, Figures 2 and 3 are characteristic diagrams of a conventional double-wave rectifier, and Figure 4 is an electrical circuit diagram of a double-wave rectifier that is an embodiment of the present invention. The circuit diagram of FIG. 5 and FIG. 6 are diagrams each showing an example of the characteristics of the double-wave rectifier according to the present invention. 1... Input terminal, 2... Output terminal, 3... Detection terminal, 4, 5... Reference voltage terminal, 6... Power supply terminal, 7... Ground potential terminal, 21... Low pass filter, 22, 23, 24, 25, 26, 27,
28, 29...transistor, 33, 34, 3
5, 36, 37, 38, 39...constant current source.
Claims (1)
のみを検出する第1の検波トランジスタ対と、上
記第1の検波トランジスタと極性が反対で、前記
基準電圧より低い電圧波形のみを検出する第2の
検波トランジスタ対と、それぞれの上記検波トラ
ンジスタ対より検出された電圧波形を電流変換し
て互いが同極性になるように合成する第3のトラ
ンジスタ対とから成ることを特徴とする両波整流
器。 2 第1の検波トランジスタ対と第2の検波トラ
ンジスタ対とは逆極性でなり、それぞれの上記検
波トランジスタ対より検出された信号を各エミツ
タホロワトランジスタを介してのち第3のトラン
ジスタ対のおのおのの入力としたことを特徴とし
た特許請求範囲第1項に記載の両波整流器。[Scope of Claims] 1. A first detection transistor pair that detects only a voltage waveform higher than a reference voltage with respect to an input signal, and only a voltage waveform whose polarity is opposite to that of the first detection transistor and is lower than the reference voltage. and a third transistor pair that converts the voltage waveforms detected by each of the detection transistor pairs into currents and synthesizes them so that they have the same polarity. A double wave rectifier. 2 The first detection transistor pair and the second detection transistor pair have opposite polarities, and the signals detected from each of the detection transistor pairs are passed through each emitter follower transistor and then transmitted to each of the third transistor pair. A double-wave rectifier according to claim 1, characterized in that the input is:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180870A JPS5881310A (en) | 1981-11-10 | 1981-11-10 | double wave rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180870A JPS5881310A (en) | 1981-11-10 | 1981-11-10 | double wave rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5881310A JPS5881310A (en) | 1983-05-16 |
| JPS6310604B2 true JPS6310604B2 (en) | 1988-03-08 |
Family
ID=16090783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56180870A Granted JPS5881310A (en) | 1981-11-10 | 1981-11-10 | double wave rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5881310A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2575912B2 (en) * | 1990-03-15 | 1997-01-29 | 富士通株式会社 | Signal demodulation circuit |
-
1981
- 1981-11-10 JP JP56180870A patent/JPS5881310A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5881310A (en) | 1983-05-16 |
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